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| lm3s8962 microcontroller da t a sheet copyright ? 2007 luminary micro, inc. ds-lm3s8962-1582 preliminar y
legal disclaimers and t rademark information informa tion in this document is provided in connection with luminar y micro products. no license, express or implied, by est oppel or other wise, t o any intellectual proper ty rights is granted by this document . except as provided in luminar y micro's terms and conditions of sale for such products, luminar y micro assumes no liability wha tsoever, and luminar y micro disclaims any express or implied w arranty , rela ting t o sale and/or use of luminar y micro's products including liability or w arranties rela ting t o fitness for a p ar ticular purpose, merchant ability , or infringement of any p a tent , copyright or other intellectual proper ty right . luminar y micro's products are not intended for use in medical, life sa ving, or life-sust aining applica tions. luminary micro may make changes to specifcations and product descriptions at any time, without notice. contact your local luminary micro sales offce or your distributor to obtain the latest specifcations before placing your product order . designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefned." luminary micro reserves these for future defnition and shall have no responsibility whatsoever for conficts or incompatibilities arising from future changes to them. copyright ? 2007 luminary micro, inc. all rights reserved. stellaris is a registered trademark and luminary micro and the luminary micro logo are trademarks of luminary micro, inc. or its subsidiaries in the united states and other countries. arm and thumb are registered trademarks and cortex is a trademark of arm limited. other names and brands may be claimed as the property of others. luminary micro, inc. 108 w ild basin, suite 350 austin, tx 78746 main: +1-512-279-8800 fax: +1-512-279-8879 http://www .luminarymicro.com september 02, 2007 2 preliminary t able of contents about this document .................................................................................................................... 21 audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 about this manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 related documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 1 architectural overview ...................................................................................................... 23 1.1 product features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 1.2 t arget applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 1.3 high-level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 1.4 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.4.1 arm cortex?-m3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.4.2 motor control peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 1.4.3 analog peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 1.4.4 serial communications peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 1.4.5 system peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.4.6 memory peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 1.4.7 additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 1.4.8 hardware details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 2 arm cortex-m3 processor core ...................................................................................... 38 2.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.2.1 serial wire and jt ag debug . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 2.2.2 embedded t race macrocell (etm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.2.3 t race port interface unit (tpiu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.2.4 rom t able . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.2.5 memory protection unit (mpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 2.2.6 nested v ectored interrupt controller (nvic) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 3 memory map ....................................................................................................................... 44 4 interrupts ............................................................................................................................ 46 5 jt ag interface .................................................................................................................... 49 5.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 5.2.1 jt ag interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5.2.2 jt ag t ap controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 5.2.3 shift registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.2.4 operational considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 5.3 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.4.1 instruction register (ir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 5.4.2 data registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 6 system control ................................................................................................................... 60 6.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.1.1 device identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 6.1.2 reset control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 3 september 02, 2007 preliminary lm3s8962 microcontroller 6.1.3 power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.1.4 clock control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 6.1.5 system control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 6.2 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.3 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 6.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 7 hibernation module .......................................................................................................... 121 7.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.2.1 register access t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 7.2.2 clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 7.2.3 battery management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 7.2.4 real-t ime clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 7.2.5 non-v olatile memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 7.2.6 power control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 7.2.7 interrupts and status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 7.3 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.3.1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.3.2 r tc match functionality (no hibernation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.3.3 r tc match/w ake-up from hibernation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 7.3.4 external w ake-up from hibernation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 7.3.5 r tc/external w ake-up from hibernation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 7.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 7.5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 8 internal memory ............................................................................................................... 140 8.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 8.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 8.2.1 sram memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 8.2.2 flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 8.3 flash memory initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8.3.1 flash programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 8.3.2 nonvolatile register programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 8.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 8.5 flash register descriptions (flash control of fset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 8.6 flash register descriptions (system control of fset) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 9 general-purpose input/outputs (gpios) ....................................................................... 164 9.1 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 9.1.1 data control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 9.1.2 interrupt control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 9.1.3 mode control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 9.1.4 commit control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 9.1.5 pad control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 9.1.6 identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9.2 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 9.3 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 9.4 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 september 02, 2007 4 preliminary t able of contents 10 general-purpose t imers ................................................................................................. 205 10.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 10.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 10.2.1 gptm reset conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 10.2.2 32-bit t imer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 10.2.3 16-bit t imer operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 10.3 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 10.3.1 32-bit one-shot/periodic t imer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 10.3.2 32-bit real-t ime clock (r tc) mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 10.3.3 16-bit one-shot/periodic t imer mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 10.3.4 16-bit input edge count mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 10.3.5 16-bit input edge t iming mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214 10.3.6 16-bit pwm mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 10.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 10.5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 1 1 w atchdog t imer ............................................................................................................... 241 1 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 1 1.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 1 1.3 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 1 1.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 1 1.5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 12 analog-to-digital converter (adc) ................................................................................. 264 12.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 12.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 12.2.1 sample sequencers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 12.2.2 module control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266 12.2.3 hardware sample a veraging circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 12.2.4 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 12.2.5 t est modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 12.2.6 internal t emperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 12.3 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 12.3.1 module initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 12.3.2 sample sequencer configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 12.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 12.5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 13 universal asynchronous receivers/t ransmitters (uart s) ......................................... 297 13.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 13.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 13.2.1 t ransmit/receive logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 13.2.2 baud-rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 13.2.3 data t ransmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 13.2.4 serial ir (sir) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300 13.2.5 fifo operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 13.2.6 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 13.2.7 loopback operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 13.2.8 irda sir block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 13.3 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 302 13.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 5 september 02, 2007 preliminary lm3s8962 microcontroller 13.5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 14 synchronous serial interface (ssi) ................................................................................ 338 14.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 14.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 14.2.1 bit rate generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 14.2.2 fifo operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 14.2.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339 14.2.4 frame formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 14.3 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 14.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 14.5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 349 15 inter-integrated circuit (i 2 c) interface ............................................................................ 375 15.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 15.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 15.2.1 i 2 c bus functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 15.2.2 a vailable speed modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 15.2.3 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 15.2.4 loopback operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 15.2.5 command sequence flow charts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 379 15.3 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 15.4 i 2 c register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 15.5 register descriptions (i 2 c master) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 15.6 register descriptions (i2c slave) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401 16 controller area network (can) module ......................................................................... 410 16.1 controller area network overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 16.2 controller area network features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 410 16.3 controller area network block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 16.4 controller area network functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 16.4.1 initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 412 16.4.2 operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 16.4.3 t ransmitting message objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 16.4.4 configuring a t ransmit message object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413 16.4.5 updating a t ransmit message object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 16.4.6 accepting received message objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 16.4.7 receiving a data frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 16.4.8 receiving a remote frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 16.4.9 receive/t ransmit priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 16.4.10 configuring a receive message object . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415 16.4.1 1 handling of received message objects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 16.4.12 handling of interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 16.4.13 bit t iming configuration error considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 16.4.14 bit t ime and bit rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417 16.4.15 calculating the bit t iming parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 419 16.5 controller area network register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 16.6 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423 17 ethernet controller .......................................................................................................... 451 17.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 september 02, 2007 6 preliminary t able of contents 17.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 17.2.1 internal mii operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 17.2.2 phy configuration/operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 453 17.2.3 mac configuration/operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 17.2.4 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 17.3 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457 17.4 ethernet register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 17.5 ethernet mac register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459 17.6 mii management register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 18 analog comparator ......................................................................................................... 496 18.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 18.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 18.2.1 internal reference programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 18.3 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 18.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 18.5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 19 pulse w idth modulator (pwm) ........................................................................................ 507 19.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 19.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 19.2.1 pwm t imer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 19.2.2 pwm comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 19.2.3 pwm signal generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 19.2.4 dead-band generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 19.2.5 interrupt/adc-t rigger selector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 19.2.6 synchronization methods . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 19.2.7 fault conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 19.2.8 output control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 19.3 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 511 19.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 19.5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 514 20 quadrature encoder interface (qei) ............................................................................... 543 20.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543 20.2 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 20.3 initialization and configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 546 20.4 register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 20.5 register descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 21 pin diagram ...................................................................................................................... 560 22 signal t ables .................................................................................................................... 561 23 operating characteristics ............................................................................................... 575 24 electrical characteristics ................................................................................................ 576 24.1 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 24.1.1 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 24.1.2 recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 24.1.3 on-chip low drop-out (ldo) regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 24.1.4 power specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 24.1.5 flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 7 september 02, 2007 preliminary lm3s8962 microcontroller 24.2 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 24.2.1 load conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 24.2.2 clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 24.2.3 analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 24.2.4 analog comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 24.2.5 i 2 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 24.2.6 ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 24.2.7 hibernation module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 24.2.8 synchronous serial interface (ssi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 24.2.9 jt ag and boundary scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 24.2.10 general-purpose i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 24.2.1 1 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 25 package information ........................................................................................................ 591 a serial flash loader .......................................................................................................... 593 a.1 serial flash loader . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 a.2 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 a.2.1 uar t . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 a.2.2 ssi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593 a.3 packet handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 a.3.1 packet format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 a.3.2 sending packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 a.3.3 receiving packets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594 a.4 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 a.4.1 command_ping (0x20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 a.4.2 command_get_st a tus (0x23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 a.4.3 command_download (0x21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595 a.4.4 command_send_da t a (0x24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 a.4.5 command_run (0x22) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 a.4.6 command_reset (0x25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596 b register quick reference ............................................................................................... 598 c ordering and contact information ................................................................................. 620 c.1 ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 c.2 company information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 c.3 support information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 september 02, 2007 8 preliminary t able of contents list of figures figure 1-1. stellaris? fury-class family high-level block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 2-1. cpu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 2-2. tpiu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 figure 5-1. jt ag module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 figure 5-2. t est access port state machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 figure 5-3. idcode register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 5-4. byp ass register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 5-5. boundary scan register format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 6-1. external circuitry to extend reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 7-1. hibernation module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 figure 8-1. flash block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 figure 9-1. gpioda t a w rite example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 9-2. gpioda t a read example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165 figure 10-1. gptm module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206 figure 10-2. 16-bit input edge count mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210 figure 10-3. 16-bit input edge t ime mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211 figure 10-4. 16-bit pwm mode example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212 figure 1 1-1. wdt module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 241 figure 12-1. adc module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 figure 12-2. internal t emperature sensor characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268 figure 13-1. uar t module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 figure 13-2. uar t character frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299 figure 13-3. irda data modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301 figure 14-1. ssi module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 338 figure 14-2. ti synchronous serial frame format (single t ransfer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340 figure 14-3. ti synchronous serial frame format (continuous t ransfer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341 figure 14-4. freescale spi format (single t ransfer) with spo=0 and sph=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 figure 14-5. freescale spi format (continuous t ransfer) with spo=0 and sph=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342 figure 14-6. freescale spi frame format with spo=0 and sph=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343 figure 14-7. freescale spi frame format (single t ransfer) with spo=1 and sph=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . 344 figure 14-8. freescale spi frame format (continuous t ransfer) with spo=1 and sph=0 . . . . . . . . . . . . . . . . . . . . 344 figure 14-9. freescale spi frame format with spo=1 and sph=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345 figure 14-10. microwire frame format (single frame) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346 figure 14-1 1. microwire frame format (continuous t ransfer) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347 figure 14-12. microwire frame format, ssifss input setup and hold requirements . . . . . . . . . . . . . . . . . . . . . . . . 347 figure 15-1. i 2 c block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 figure 15-2. i 2 c bus configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 figure 15-3. st ar t and st op conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 figure 15-4. complete data t ransfer with a 7-bit address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 figure 15-5. r/s bit in first byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 figure 15-6. data v alidity during bit t ransfer on the i 2 c bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377 figure 15-7. master single send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380 figure 15-8. master single receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381 figure 15-9. master burst send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382 figure 15-10. master burst receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 383 figure 15-1 1. master burst receive after burst send . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 384 9 september 02, 2007 preliminary lm3s8962 microcontroller figure 15-12. master burst send after burst receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385 figure 15-13. slave command sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 figure 16-1. can module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 411 figure 16-2. can bit t ime . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 figure 17-1. ethernet controller block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 figure 17-2. ethernet controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 452 figure 17-3. ethernet frame . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454 figure 18-1. analog comparator module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 496 figure 18-2. structure of comparator unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 figure 18-3. comparator internal reference structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 figure 19-1. pwm module block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507 figure 19-2. pwm count-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508 figure 19-3. pwm count-up/down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 figure 19-4. pwm generation example in count-up/down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509 figure 19-5. pwm dead-band generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 510 figure 20-1. qei block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544 figure 20-2. quadrature encoder and v elocity predivider operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545 figure 21-1. pin connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560 figure 24-1. load conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 figure 24-2. i 2 c t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 figure 24-3. external xtlp oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584 figure 24-4. hibernation module t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 figure 24-5. ssi t iming for ti frame format (frf=01), single t ransfer t iming measurement . . . . . . . . . . . . . . 586 figure 24-6. ssi t iming for microwire frame format (frf=10), single t ransfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586 figure 24-7. ssi t iming for spi frame format (frf=00), with sph=1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 figure 24-8. jt ag t est clock input t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 figure 24-9. jt ag t est access port (t ap) t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 figure 24-10. jt ag trst t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588 figure 24-1 1. external reset t iming ( rst ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 figure 24-12. power-on reset t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 figure 24-13. brown-out reset t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 figure 24-14. software reset t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 figure 24-15. w atchdog reset t iming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590 figure 25-1. 100-pin lqfp package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591 september 02, 2007 10 preliminary t able of contents list of t ables t able 1. documentation conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 t able 3-1. memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 t able 4-1. exception t ypes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 t able 4-2. interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 t able 5-1. jt ag port pins reset state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 t able 5-2. jt ag instruction register commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 t able 6-1. system control register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 t able 7-1. hibernation module register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 t able 8-1. flash protection policy combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 t able 8-2. flash resident registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 t able 8-3. flash register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 t able 9-1. gpio pad configuration examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 t able 9-2. gpio interrupt configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 t able 9-3. gpio register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 t able 10-1. 16-bit t imer with prescaler configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 t able 10-2. t imers register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 t able 1 1-1. w atchdog t imer register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 242 t able 12-1. samples and fifo depth of sequencers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 265 t able 12-2. adc register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 269 t able 13-1. uar t register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303 t able 14-1. ssi register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348 t able 15-1. examples of i 2 c master t imer period versus speed mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378 t able 15-2. inter-integrated circuit (i 2 c) interface register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 t able 15-3. w rite field decoding for i2cmcs[3:0] field (sheet 1 of 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392 t able 16-1. t ransmit message object bit settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 414 t able 16-2. receive message object bit settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416 t able 16-3. can protocol ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 418 t able 16-4. can register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 421 t able 17-1. tx & rx fifo organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 455 t able 17-2. ethernet register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458 t able 18-1. comparator 0 operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497 t able 18-2. internal reference v oltage and acrefctl field v alues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498 t able 18-3. analog comparators register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499 t able 19-1. pwm register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512 t able 20-1. qei register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547 t able 22-1. signals by pin number . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561 t able 22-2. signals by signal name . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565 t able 22-3. signals by function, except for gpio . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569 t able 22-4. gpio pins and alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573 t able 23-1. t emperature characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 t able 23-2. thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575 t able 24-1. maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 t able 24-2. recommended dc operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576 t able 24-3. ldo regulator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577 t able 24-4. detailed power specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578 t able 24-5. flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 1 1 september 02, 2007 preliminary lm3s8962 microcontroller t able 24-6. phase locked loop (pll) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 t able 24-7. clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579 t able 24-8. crystal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 t able 24-9. adc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 t able 24-10. analog comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 t able 24-1 1. analog comparator v oltage reference characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 t able 24-12. i 2 c characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581 t able 24-13. 100base-tx t ransmitter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 t able 24-14. 100base-tx t ransmitter characteristics (informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 t able 24-15. 100base-tx receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 t able 24-16. 10base-t t ransmitter characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 t able 24-17. 10base-t t ransmitter characteristics (informative) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 t able 24-18. 10base-t receiver characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 t able 24-19. isolation t ransformers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583 t able 24-20. ethernet reference crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584 t able 24-21. external xtlp oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584 t able 24-22. hibernation module characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 t able 24-23. ssi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 t able 24-24. jt ag characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587 t able 24-25. gpio characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 t able 24-26. reset characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589 t able c-1. part ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620 september 02, 2007 12 preliminary t able of contents list of registers system control .............................................................................................................................. 60 register 1: device identification 0 (did0), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 register 2: brown-out reset control (pborctl), of fset 0x030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 register 3: ldo power control (ldopctl), of fset 0x034 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 register 4: raw interrupt status (ris), of fset 0x050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 register 5: interrupt mask control (imc), of fset 0x054 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 register 6: masked interrupt status and clear (misc), of fset 0x058 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 register 7: reset cause (resc), of fset 0x05c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 register 8: run-mode clock configuration (rcc), of fset 0x060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 register 9: xt al to pll t ranslation (pllcfg), of fset 0x064 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 register 10: run-mode clock configuration 2 (rcc2), of fset 0x070 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 register 1 1: deep sleep clock configuration (dslpclkcfg), of fset 0x144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 register 12: device identification 1 (did1), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 register 13: device capabilities 0 (dc0), of fset 0x008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 register 14: device capabilities 1 (dc1), of fset 0x010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 register 15: device capabilities 2 (dc2), of fset 0x014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 register 16: device capabilities 3 (dc3), of fset 0x018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 register 17: device capabilities 4 (dc4), of fset 0x01c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 register 18: run mode clock gating control register 0 (rcgc0), of fset 0x100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 register 19: sleep mode clock gating control register 0 (scgc0), of fset 0x1 10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 register 20: deep sleep mode clock gating control register 0 (dcgc0), of fset 0x120 . . . . . . . . . . . . . . . . . . . . . . . . . 99 register 21: run mode clock gating control register 1 (rcgc1), of fset 0x104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 register 22: sleep mode clock gating control register 1 (scgc1), of fset 0x1 14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 register 23: deep sleep mode clock gating control register 1 (dcgc1), of fset 0x124 . . . . . . . . . . . . . . . . . . . . . . . 107 register 24: run mode clock gating control register 2 (rcgc2), of fset 0x108 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 register 25: sleep mode clock gating control register 2 (scgc2), of fset 0x1 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 register 26: deep sleep mode clock gating control register 2 (dcgc2), of fset 0x128 . . . . . . . . . . . . . . . . . . . . . . . 114 register 27: software reset control 0 (srcr0), of fset 0x040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 register 28: software reset control 1 (srcr1), of fset 0x044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 register 29: software reset control 2 (srcr2), of fset 0x048 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 hibernation module ..................................................................................................................... 121 register 1: hibernation r tc counter (hibr tcc), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 register 2: hibernation r tc match 0 (hibr tcm0), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 register 3: hibernation r tc match 1 (hibr tcm1), of fset 0x008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 register 4: hibernation r tc load (hibr tcld), of fset 0x00c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131 register 5: hibernation control (hibctl), of fset 0x010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132 register 6: hibernation interrupt mask (hibim), of fset 0x014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134 register 7: hibernation raw interrupt status (hibris), of fset 0x018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 register 8: hibernation masked interrupt status (hibmis), of fset 0x01c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136 register 9: hibernation interrupt clear (hibic), of fset 0x020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 register 10: hibernation r tc t rim (hibr tct), of fset 0x024 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 register 1 1: hibernation data (hibda t a), of fset 0x030-0x12c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 internal memory ........................................................................................................................... 140 register 1: flash memory address (fma), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 register 2: flash memory data (fmd), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146 13 september 02, 2007 preliminary lm3s8962 microcontroller register 3: flash memory control (fmc), of fset 0x008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 register 4: flash controller raw interrupt status (fcris), of fset 0x00c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 register 5: flash controller interrupt mask (fcim), of fset 0x010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 register 6: flash controller masked interrupt status and clear (fcmisc), of fset 0x014 . . . . . . . . . . . . . . . . . . . . . 151 register 7: usec reload (usecrl), of fset 0x140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 register 8: flash memory protection read enable 0 (fmpre0), of fset 0x130 and 0x200 . . . . . . . . . . . . . . . . . . . 153 register 9: flash memory protection program enable 0 (fmppe0), of fset 0x134 and 0x400 . . . . . . . . . . . . . . . 154 register 10: user debug (user_dbg), of fset 0x1d0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155 register 1 1: user register 0 (user_reg0), of fset 0x1e0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156 register 12: user register 1 (user_reg1), of fset 0x1e4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 register 13: flash memory protection read enable 1 (fmpre1), of fset 0x204 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158 register 14: flash memory protection read enable 2 (fmpre2), of fset 0x208 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 register 15: flash memory protection read enable 3 (fmpre3), of fset 0x20c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160 register 16: flash memory protection program enable 1 (fmppe1), of fset 0x404 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161 register 17: flash memory protection program enable 2 (fmppe2), of fset 0x408 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162 register 18: flash memory protection program enable 3 (fmppe3), of fset 0x40c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 general-purpose input/outputs (gpios) ................................................................................... 164 register 1: gpio data (gpioda t a), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171 register 2: gpio direction (gpiodir), of fset 0x400 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172 register 3: gpio interrupt sense (gpiois), of fset 0x404 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173 register 4: gpio interrupt both edges (gpioibe), of fset 0x408 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 register 5: gpio interrupt event (gpioiev), of fset 0x40c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 register 6: gpio interrupt mask (gpioim), of fset 0x410 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 register 7: gpio raw interrupt status (gpioris), of fset 0x414 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 register 8: gpio masked interrupt status (gpiomis), of fset 0x418 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178 register 9: gpio interrupt clear (gpioicr), of fset 0x41c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179 register 10: gpio alternate function select (gpioafsel), of fset 0x420 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180 register 1 1: gpio 2-ma drive select (gpiodr2r), of fset 0x500 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182 register 12: gpio 4-ma drive select (gpiodr4r), of fset 0x504 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183 register 13: gpio 8-ma drive select (gpiodr8r), of fset 0x508 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184 register 14: gpio open drain select (gpioodr), of fset 0x50c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185 register 15: gpio pull-up select (gpiopur), of fset 0x510 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186 register 16: gpio pull-down select (gpiopdr), of fset 0x514 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187 register 17: gpio slew rate control select (gpioslr), of fset 0x518 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188 register 18: gpio digital enable (gpioden), of fset 0x51c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189 register 19: gpio lock (gpiolock), of fset 0x520 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190 register 20: gpio commit (gpiocr), of fset 0x524 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 191 register 21: gpio peripheral identification 4 (gpioperiphid4), of fset 0xfd0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193 register 22: gpio peripheral identification 5 (gpioperiphid5), of fset 0xfd4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194 register 23: gpio peripheral identification 6 (gpioperiphid6), of fset 0xfd8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195 register 24: gpio peripheral identification 7 (gpioperiphid7), of fset 0xfdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196 register 25: gpio peripheral identification 0 (gpioperiphid0), of fset 0xfe0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 register 26: gpio peripheral identification 1 (gpioperiphid1), of fset 0xfe4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198 register 27: gpio peripheral identification 2 (gpioperiphid2), of fset 0xfe8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199 register 28: gpio peripheral identification 3 (gpioperiphid3), of fset 0xfec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200 register 29: gpio primecell identification 0 (gpiopcellid0), of fset 0xff0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 register 30: gpio primecell identification 1 (gpiopcellid1), of fset 0xff4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202 register 31: gpio primecell identification 2 (gpiopcellid2), of fset 0xff8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 september 02, 2007 14 preliminary t able of contents register 32: gpio primecell identification 3 (gpiopcellid3), of fset 0xffc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 general-purpose t imers ............................................................................................................. 205 register 1: gptm configuration (gptmcfg), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 register 2: gptm t imera mode (gptmt amr), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218 register 3: gptm t imerb mode (gptmtbmr), of fset 0x008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 register 4: gptm control (gptmctl), of fset 0x00c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222 register 5: gptm interrupt mask (gptmimr), of fset 0x018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 register 6: gptm raw interrupt status (gptmris), of fset 0x01c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 227 register 7: gptm masked interrupt status (gptmmis), of fset 0x020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228 register 8: gptm interrupt clear (gptmicr), of fset 0x024 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 register 9: gptm t imera interval load (gptmt ailr), of fset 0x028 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231 register 10: gptm t imerb interval load (gptmtbilr), of fset 0x02c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 register 1 1: gptm t imera match (gptmt ama tchr), of fset 0x030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233 register 12: gptm t imerb match (gptmtbma tchr), of fset 0x034 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 register 13: gptm t imera prescale (gptmt apr), of fset 0x038 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 register 14: gptm t imerb prescale (gptmtbpr), of fset 0x03c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 236 register 15: gptm t imera prescale match (gptmt apmr), of fset 0x040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 237 register 16: gptm t imerb prescale match (gptmtbpmr), of fset 0x044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 238 register 17: gptm t imera (gptmt ar), of fset 0x048 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 239 register 18: gptm t imerb (gptmtbr), of fset 0x04c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 240 w atchdog t imer ........................................................................................................................... 241 register 1: w atchdog load (wdtload), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244 register 2: w atchdog v alue (wdtv alue), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 register 3: w atchdog control (wdtctl), of fset 0x008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 246 register 4: w atchdog interrupt clear (wdticr), of fset 0x00c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247 register 5: w atchdog raw interrupt status (wdtris), of fset 0x010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248 register 6: w atchdog masked interrupt status (wdtmis), of fset 0x014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249 register 7: w atchdog t est (wdttest), of fset 0x418 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250 register 8: w atchdog lock (wdtlock), of fset 0xc00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 251 register 9: w atchdog peripheral identification 4 (wdtperiphid4), of fset 0xfd0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 252 register 10: w atchdog peripheral identification 5 (wdtperiphid5), of fset 0xfd4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253 register 1 1: w atchdog peripheral identification 6 (wdtperiphid6), of fset 0xfd8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 254 register 12: w atchdog peripheral identification 7 (wdtperiphid7), of fset 0xfdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 255 register 13: w atchdog peripheral identification 0 (wdtperiphid0), of fset 0xfe0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 256 register 14: w atchdog peripheral identification 1 (wdtperiphid1), of fset 0xfe4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257 register 15: w atchdog peripheral identification 2 (wdtperiphid2), of fset 0xfe8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258 register 16: w atchdog peripheral identification 3 (wdtperiphid3), of fset 0xfec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 register 17: w atchdog primecell identification 0 (wdtpcellid0), of fset 0xff0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 register 18: w atchdog primecell identification 1 (wdtpcellid1), of fset 0xff4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 register 19: w atchdog primecell identification 2 (wdtpcellid2), of fset 0xff8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 262 register 20: w atchdog primecell identification 3 (wdtpcellid3 ), of fset 0xffc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 analog-to-digital converter (adc) ............................................................................................. 264 register 1: adc active sample sequencer (adcactss), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 register 2: adc raw interrupt status (adcris), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272 register 3: adc interrupt mask (adcim), of fset 0x008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273 register 4: adc interrupt status and clear (adcisc), of fset 0x00c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 register 5: adc overflow status (adcost a t), of fset 0x010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 register 6: adc event multiplexer select (adcemux), of fset 0x014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276 15 september 02, 2007 preliminary lm3s8962 microcontroller register 7: adc underflow status (adcust a t), of fset 0x018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 register 8: adc sample sequencer priority (adcsspri), of fset 0x020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 register 9: adc processor sample sequence initiate (adcpssi), of fset 0x028 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281 register 10: adc sample a veraging control (adcsac), of fset 0x030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 register 1 1: adc sample sequence input multiplexer select 0 (adcssmux0), of fset 0x040 . . . . . . . . . . . . . . . 283 register 12: adc sample sequence control 0 (adcssctl0), of fset 0x044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 register 13: adc sample sequence result fifo 0 (adcssfifo0), of fset 0x048 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 register 14: adc sample sequence result fifo 1 (adcssfifo1), of fset 0x068 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 register 15: adc sample sequence result fifo 2 (adcssfifo2), of fset 0x088 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 register 16: adc sample sequence result fifo 3 (adcssfifo3), of fset 0x0a8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288 register 17: adc sample sequence fifo 0 status (adcssfst a t0), of fset 0x04c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 register 18: adc sample sequence fifo 1 status (adcssfst a t1), of fset 0x06c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 register 19: adc sample sequence fifo 2 status (adcssfst a t2), of fset 0x08c . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 register 20: adc sample sequence fifo 3 status (adcssfst a t3), of fset 0x0ac . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 register 21: adc sample sequence input multiplexer select 1 (adcssmux1), of fset 0x060 . . . . . . . . . . . . . . . 290 register 22: adc sample sequence input multiplexer select 2 (adcssmux2), of fset 0x080 . . . . . . . . . . . . . . . 290 register 23: adc sample sequence control 1 (adcssctl1), of fset 0x064 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 register 24: adc sample sequence control 2 (adcssctl2), of fset 0x084 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 register 25: adc sample sequence input multiplexer select 3 (adcssmux3), of fset 0x0a0 . . . . . . . . . . . . . . . 293 register 26: adc sample sequence control 3 (adcssctl3), of fset 0x0a4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 register 27: adc t est mode loopback (adctmlb), of fset 0x100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295 universal asynchronous receivers/t ransmitters (uart s) ..................................................... 297 register 1: uar t data (uar tdr), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305 register 2: uar t receive status/error clear (uar trsr/uar tecr), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 register 3: uar t flag (uar tfr), of fset 0x018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309 register 4: uar t irda low-power register (uar tilpr), of fset 0x020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311 register 5: uar t integer baud-rate divisor (uar tibrd), of fset 0x024 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 register 6: uar t fractional baud-rate divisor (uar tfbrd), of fset 0x028 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 register 7: uar t line control (uar tlcrh), of fset 0x02c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 register 8: uar t control (uar tctl), of fset 0x030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316 register 9: uar t interrupt fifo level select (uar tifls), of fset 0x034 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318 register 10: uar t interrupt mask (uar tim), of fset 0x038 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320 register 1 1: uar t raw interrupt status (uar tris), of fset 0x03c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 322 register 12: uar t masked interrupt status (uar tmis), of fset 0x040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 register 13: uar t interrupt clear (uar ticr), of fset 0x044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324 register 14: uar t peripheral identification 4 (uar tperiphid4), of fset 0xfd0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 register 15: uar t peripheral identification 5 (uar tperiphid5), of fset 0xfd4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 327 register 16: uar t peripheral identification 6 (uar tperiphid6), of fset 0xfd8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 register 17: uar t peripheral identification 7 (uar tperiphid7), of fset 0xfdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 register 18: uar t peripheral identification 0 (uar tperiphid0), of fset 0xfe0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 register 19: uar t peripheral identification 1 (uar tperiphid1), of fset 0xfe4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331 register 20: uar t peripheral identification 2 (uar tperiphid2), of fset 0xfe8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 register 21: uar t peripheral identification 3 (uar tperiphid3), of fset 0xfec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 register 22: uar t primecell identification 0 (uar tpcellid0), of fset 0xff0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334 register 23: uar t primecell identification 1 (uar tpcellid1), of fset 0xff4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 335 register 24: uar t primecell identification 2 (uar tpcellid2), of fset 0xff8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336 register 25: uar t primecell identification 3 (uar tpcellid3), of fset 0xffc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337 september 02, 2007 16 preliminary t able of contents synchronous serial interface (ssi) ............................................................................................ 338 register 1: ssi control 0 (ssicr0), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350 register 2: ssi control 1 (ssicr1), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 register 3: ssi data (ssidr), of fset 0x008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 register 4: ssi status (ssisr), of fset 0x00c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 register 5: ssi clock prescale (ssicpsr), of fset 0x010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357 register 6: ssi interrupt mask (ssiim), of fset 0x014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358 register 7: ssi raw interrupt status (ssiris), of fset 0x018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360 register 8: ssi masked interrupt status (ssimis), of fset 0x01c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 361 register 9: ssi interrupt clear (ssiicr), of fset 0x020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362 register 10: ssi peripheral identification 4 (ssiperiphid4), of fset 0xfd0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 register 1 1: ssi peripheral identification 5 (ssiperiphid5), of fset 0xfd4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 register 12: ssi peripheral identification 6 (ssiperiphid6), of fset 0xfd8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 365 register 13: ssi peripheral identification 7 (ssiperiphid7), of fset 0xfdc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366 register 14: ssi peripheral identification 0 (ssiperiphid0), of fset 0xfe0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 367 register 15: ssi peripheral identification 1 (ssiperiphid1), of fset 0xfe4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 register 16: ssi peripheral identification 2 (ssiperiphid2), of fset 0xfe8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 register 17: ssi peripheral identification 3 (ssiperiphid3), of fset 0xfec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 register 18: ssi primecell identification 0 (ssipcellid0), of fset 0xff0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 register 19: ssi primecell identification 1 (ssipcellid1), of fset 0xff4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 register 20: ssi primecell identification 2 (ssipcellid2), of fset 0xff8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 register 21: ssi primecell identification 3 (ssipcellid3), of fset 0xffc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 374 inter-integrated circuit (i 2 c) interface ........................................................................................ 375 register 1: i 2 c master slave address (i2cmsa), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 register 2: i 2 c master control/status (i2cmcs), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390 register 3: i 2 c master data (i2cmdr), of fset 0x008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 394 register 4: i 2 c master t imer period (i2cmtpr), of fset 0x00c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 395 register 5: i 2 c master interrupt mask (i2cmimr), of fset 0x010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 396 register 6: i 2 c master raw interrupt status (i2cmris), of fset 0x014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397 register 7: i 2 c master masked interrupt status (i2cmmis), of fset 0x018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398 register 8: i 2 c master interrupt clear (i2cmicr), of fset 0x01c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399 register 9: i 2 c master configuration (i2cmcr), of fset 0x020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400 register 10: i 2 c slave own address (i2csoar), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402 register 1 1: i 2 c slave control/status (i2cscsr), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 403 register 12: i 2 c slave data (i2csdr), of fset 0x008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 405 register 13: i 2 c slave interrupt mask (i2csimr), of fset 0x00c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406 register 14: i 2 c slave raw interrupt status (i2csris), of fset 0x010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 407 register 15: i 2 c slave masked interrupt status (i2csmis), of fset 0x014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408 register 16: i 2 c slave interrupt clear (i2csicr), of fset 0x018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 409 controller area network (can) module ..................................................................................... 410 register 1: can control (canctl), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 424 register 2: can status (cansts), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426 register 3: can error counter (canerr), of fset 0x008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 429 register 4: can bit t iming (canbit), of fset 0x00c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 430 register 5: can interrupt (canint), of fset 0x010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 432 register 6: can t est (cantst), of fset 0x014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 433 register 7: can baud rate prescalar extension (canbrpe), of fset 0x018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435 17 september 02, 2007 preliminary lm3s8962 microcontroller register 8: can if1 command request (canif1crq), of fset 0x020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 register 9: can if2 command request (canif2crq), of fset 0x080 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436 register 10: can if1 command mask (canif1cmsk), of fset 0x024 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 register 1 1: can if2 command mask (canif2cmsk), of fset 0x084 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437 register 12: can if1 mask 1 (canif1msk1), of fset 0x028 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 register 13: can if2 mask 1 (canif2msk1), of fset 0x088 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440 register 14: can if1 mask 2 (canif1msk2), of fset 0x02c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 register 15: can if2 mask 2 (canif2msk2), of fset 0x08c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 441 register 16: can if1 arbitration 1 (canif1arb1), of fset 0x030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 register 17: can if2 arbitration 1 (canif2arb1), of fset 0x090 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 442 register 18: can if1 arbitration 2 (canif1arb2), of fset 0x034 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 register 19: can if2 arbitration 2 (canif2arb2), of fset 0x094 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443 register 20: can if1 message control (canif1mctl), of fset 0x038 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 register 21: can if2 message control (canif2mctl), of fset 0x098 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444 register 22: can if1 data a1 (canif1da1), of fset 0x03c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 register 23: can if1 data a2 (canif1da2), of fset 0x040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 register 24: can if1 data b1 (canif1db1), of fset 0x044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 register 25: can if1 data b2 (canif1db2), of fset 0x048 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 register 26: can if2 data a1 (canif2da1), of fset 0x09c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 register 27: can if2 data a2 (canif2da2), of fset 0x0a0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 register 28: can if2 data b1 (canif2db1), of fset 0x0a4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 register 29: can if2 data b2 (canif2db2), of fset 0x0a8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 446 register 30: can t ransmission request 1 (cantxrq1), of fset 0x100 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 register 31: can t ransmission request 2 (cantxrq2), of fset 0x104 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447 register 32: can new data 1 (cannwda1), of fset 0x120 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 register 33: can new data 2 (cannwda2), of fset 0x124 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448 register 34: can message 1 interrupt pending (canmsg1int), of fset 0x140 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 register 35: can message 2 interrupt pending (canmsg2int), of fset 0x144 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 449 register 36: can message 1 v alid (canmsg1v al), of fset 0x160 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 register 37: can message 2 v alid (canmsg2v al), of fset 0x164 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 450 ethernet controller ...................................................................................................................... 451 register 1: ethernet mac raw interrupt status (macris), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460 register 2: ethernet mac interrupt acknowledge (maciack), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462 register 3: ethernet mac interrupt mask (macim), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 463 register 4: ethernet mac receive control (macrctl), of fset 0x008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464 register 5: ethernet mac t ransmit control (mactctl), of fset 0x00c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465 register 6: ethernet mac data (macda t a), of fset 0x010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466 register 7: ethernet mac individual address 0 (macia0), of fset 0x014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468 register 8: ethernet mac individual address 1 (macia1), of fset 0x018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469 register 9: ethernet mac threshold (macthr), of fset 0x01c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 register 10: ethernet mac management control (macmctl), of fset 0x020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471 register 1 1: ethernet mac management divider (macmdv), of fset 0x024 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 register 12: ethernet mac management t ransmit data (macmtxd), of fset 0x02c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473 register 13: ethernet mac management receive data (macmrxd), of fset 0x030 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474 register 14: ethernet mac number of packets (macnp), of fset 0x034 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 475 register 15: ethernet mac t ransmission request (mactr), of fset 0x038 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476 register 16: ethernet mac t imer support (macts), of fset 0x03c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477 register 17: ethernet phy management register 0 C control (mr0), address 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478 september 02, 2007 18 preliminary t able of contents register 18: ethernet phy management register 1 C status (mr1), address 0x01 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 480 register 19: ethernet phy management register 2 C phy identifier 1 (mr2), address 0x02 . . . . . . . . . . . . . . . . . 482 register 20: ethernet phy management register 3 C phy identifier 2 (mr3), address 0x03 . . . . . . . . . . . . . . . . . 483 register 21: ethernet phy management register 4 C auto-negotiation advertisement (mr4), address 0x04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 484 register 22: ethernet phy management register 5 C auto-negotiation link partner base page ability (mr5), address 0x05 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 486 register 23: ethernet phy management register 6 C auto-negotiation expansion (mr6), address 0x06 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487 register 24: ethernet phy management register 16 C v endor-specific (mr16), address 0x10 . . . . . . . . . . . . . 488 register 25: ethernet phy management register 17 C interrupt control/status (mr17), address 0x1 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490 register 26: ethernet phy management register 18 C diagnostic (mr18), address 0x12 . . . . . . . . . . . . . . . . . . . . . 492 register 27: ethernet phy management register 19 C t ransceiver control (mr19), address 0x13 . . . . . . . 493 register 28: ethernet phy management register 23 C led configuration (mr23), address 0x17 . . . . . . . . . 494 register 29: ethernet phy management register 24 Cmdi/mdix control (mr24), address 0x18 . . . . . . . . . . 495 analog comparator ..................................................................................................................... 496 register 1: analog comparator masked interrupt status (acmis), of fset 0x00 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500 register 2: analog comparator raw interrupt status (acris), of fset 0x04 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501 register 3: analog comparator interrupt enable (acinten), of fset 0x08 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 502 register 4: analog comparator reference v oltage control (acrefctl), of fset 0x10 . . . . . . . . . . . . . . . . . . . . . . . . . 503 register 5: analog comparator status 0 (acst a t0), of fset 0x20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504 register 6: analog comparator control 0 (acctl0), of fset 0x24 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505 pulse w idth modulator (pwm) .................................................................................................... 507 register 1: pwm master control (pwmctl), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515 register 2: pwm t ime base sync (pwmsync), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 516 register 3: pwm output enable (pwmenable), of fset 0x008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517 register 4: pwm output inversion (pwminver t), of fset 0x00c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 518 register 5: pwm output fault (pwmf aul t), of fset 0x010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519 register 6: pwm interrupt enable (pwminten), of fset 0x014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 520 register 7: pwm raw interrupt status (pwmris), of fset 0x018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521 register 8: pwm interrupt status and clear (pwmisc), of fset 0x01c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522 register 9: pwm status (pwmst a tus), of fset 0x020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523 register 10: pwm0 control (pwm0ctl), of fset 0x040 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 register 1 1: pwm1 control (pwm1ctl), of fset 0x080 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 register 12: pwm2 control (pwm2ctl), of fset 0x0c0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524 register 13: pwm0 interrupt and t rigger enable (pwm0inten), of fset 0x044 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 register 14: pwm1 interrupt and t rigger enable (pwm1inten), of fset 0x084 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 register 15: pwm2 interrupt and t rigger enable (pwm2inten), of fset 0x0c4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526 register 16: pwm0 raw interrupt status (pwm0ris), of fset 0x048 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 register 17: pwm1 raw interrupt status (pwm1ris), of fset 0x088 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 register 18: pwm2 raw interrupt status (pwm2ris), of fset 0x0c8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528 register 19: pwm0 interrupt status and clear (pwm0isc), of fset 0x04c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 register 20: pwm1 interrupt status and clear (pwm1isc), of fset 0x08c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 register 21: pwm2 interrupt status and clear (pwm2isc), of fset 0x0cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529 register 22: pwm0 load (pwm0load), of fset 0x050 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 register 23: pwm1 load (pwm1load), of fset 0x090 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 register 24: pwm2 load (pwm2load), of fset 0x0d0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530 19 september 02, 2007 preliminary lm3s8962 microcontroller register 25: pwm0 counter (pwm0count), of fset 0x054 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 register 26: pwm1 counter (pwm1count), of fset 0x094 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 register 27: pwm2 counter (pwm2count), of fset 0x0d4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 register 28: pwm0 compare a (pwm0cmp a), of fset 0x058 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 register 29: pwm1 compare a (pwm1cmp a), of fset 0x098 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 register 30: pwm2 compare a (pwm2cmp a), of fset 0x0d8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532 register 31: pwm0 compare b (pwm0cmpb), of fset 0x05c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 register 32: pwm1 compare b (pwm1cmpb), of fset 0x09c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 register 33: pwm2 compare b (pwm2cmpb), of fset 0x0dc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533 register 34: pwm0 generator a control (pwm0gena), of fset 0x060 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 register 35: pwm1 generator a control (pwm1gena), of fset 0x0a0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 register 36: pwm2 generator a control (pwm2gena), of fset 0x0e0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534 register 37: pwm0 generator b control (pwm0genb), of fset 0x064 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 register 38: pwm1 generator b control (pwm1genb), of fset 0x0a4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 register 39: pwm2 generator b control (pwm2genb), of fset 0x0e4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537 register 40: pwm0 dead-band control (pwm0dbctl), of fset 0x068 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 register 41: pwm1 dead-band control (pwm1dbctl), of fset 0x0a8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 register 42: pwm2 dead-band control (pwm2dbctl), of fset 0x0e8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540 register 43: pwm0 dead-band rising-edge delay (pwm0dbrise), of fset 0x06c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 register 44: pwm1 dead-band rising-edge delay (pwm1dbrise), of fset 0x0ac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 register 45: pwm2 dead-band rising-edge delay (pwm2dbrise), of fset 0x0ec . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541 register 46: pwm0 dead-band falling-edge-delay (pwm0dbf all), of fset 0x070 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 register 47: pwm1 dead-band falling-edge-delay (pwm1dbf all), of fset 0x0b0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 register 48: pwm2 dead-band falling-edge-delay (pwm2dbf all), of fset 0x0f0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542 quadrature encoder interface (qei) .......................................................................................... 543 register 1: qei control (qeictl), of fset 0x000 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 548 register 2: qei status (qeist a t), of fset 0x004 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550 register 3: qei position (qeipos), of fset 0x008 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551 register 4: qei maximum position (qeimaxpos), of fset 0x00c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 552 register 5: qei t imer load (qeiload), of fset 0x010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553 register 6: qei t imer (qeitime), of fset 0x014 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554 register 7: qei v elocity counter (qeicount), of fset 0x018 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555 register 8: qei v elocity (qeispeed), of fset 0x01c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556 register 9: qei interrupt enable (qeiinten), of fset 0x020 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557 register 10: qei raw interrupt status (qeiris), of fset 0x024 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558 register 1 1: qei interrupt status and clear (qeiisc), of fset 0x028 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559 september 02, 2007 20 preliminary t able of contents about this document this data sheet provides reference information for the lm3s8962 microcontroller , describing the functional blocks of the system-on-chip (soc) device designed around the arm? cortex?-m3 core. audience this manual is intended for system software developers, hardware designers, and application developers. about this manual this document is organized into sections that correspond to each major feature. related documents the following documents are referenced by the data sheet, and available on the documentation cd or from the luminary micro web site at www .luminarymicro.com: arm? cortex?-m3 t echnical reference manual arm? coresight t echnical reference manual arm? v7-m architecture application level reference manual the following related documents are also referenced: ieee standard 1 149.1-t est access port and boundary-scan architecture this documentation list was current as of publication date. please check the luminary micro web site for additional documentation, including application notes and white papers. documentation conventions this document uses the conventions shown in t able 1 on page 21 . t able 1. documentation conventions meaning notation general register notation apb registers are indicated in uppercase bold. for example, pborctl is the power-on and brown-out reset control register . if a register name contains a lowercase n, it represents more than one register . for example, srcrn represents any (or all) of the three software reset control registers: srcr0, srcr1 , and srcr2 . register a single bit in a register . bit t wo or more consecutive and related bits. bit field a hexadecimal increment to a register's address, relative to that module's base address as specified in memory map on page 44 . of fset 0x nnn registers are numbered consecutively throughout the document to aid in referencing them. the register number has no meaning to software. register n 21 september 02, 2007 preliminary lm3s8962 microcontroller meaning notation register bits marked reserved are reserved for future use. in most cases, reserved bits are set to 0; however , user software should not rely on the value of a reserved bit. t o provide software compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. reserved the range of register bits inclusive from xx to yy . for example, 31:15 means bits 15 through 31 in that register . yy:xx this value in the register bit diagram indicates whether software running on the controller can change the value of the bit field. register bit/field t ypes software can read this field. the bit or field is cleared by hardware after reading the bit/field. rc software can read this field. always write the chip reset value. ro software can read or write this field. r/w software can read or write this field. a write of a 0 to a w1c bit does not af fect the bit value in the register . a write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. this register type is primarily used for clearing interrupt status bits where the read operation provides the interrupt status and the write of the read value clears only the interrupts being reported at the time the register was read. r/w1c software can write this field. a write of a 0 to a w1c bit does not af fect the bit value in the register . a write of a 1 clears the value of the bit in the register; the remaining bits remain unchanged. a read of the register returns no meaningful data. this register is typically used to clear the corresponding bit in an interrupt register . w1c only a write by software is valid; a read of the register returns no meaningful data. wo this value in the register bit diagram shows the bit/field value after any reset, unless noted. register bit/field reset v alue bit cleared to 0 on chip reset. 0 bit set to 1 on chip reset. 1 nondeterministic. - pin/signal notation pin alternate function; a pin defaults to the signal without the brackets. [ ] refers to the physical connection on the package. pin refers to the electrical signal encoding of a pin. signal change the value of the signal from the logically false state to the logically t rue state. for active high signals, the asserted signal value is 1 (high); for active low signals, the asserted signal value is 0 (low). the active polarity (high or low) is defined by the signal name (see signal and signal below). assert a signal change the value of the signal from the logically t rue state to the logically false state. deassert a signal signal names are in uppercase and in the courier font. an overbar on a signal name indicates that it is active low . t o assert signal is to drive it low; to deassert signal is to drive it high. signal signal names are in uppercase and in the courier font. an active high signal has no overbar . t o assert signal is to drive it high; to deassert signal is to drive it low . signal numbers an uppercase x indicates any of several values is allowed, where x can be any legal pattern. for example, a binary value of 0x00 can be either 0100 or 0000, a hex value of 0xx is 0x0 or 0x1, and so on. x hexadecimal numbers have a prefix of 0x. for example, 0x00ff is the hexadecimal number ff . all other numbers within register tables are assumed to be binary . within conceptual information, binary numbers are indicated with a b suf fix, for example, 101 1b, and decimal numbers are written without a prefix or suf fix. 0x september 02, 2007 22 preliminary about this document 1 architectural overview the luminary micro stellaris ? family of microcontrollersthe first arm? cortex?-m3 based controllersbrings high-performance 32-bit computing to cost-sensitive embedded microcontroller applications. these pioneering parts deliver customers 32-bit performance at a cost equivalent to legacy 8- and 16-bit devices, all in a package with a small footprint. the stellaris ? family of fers ef ficient performance and extensive integration, favorably positioning the device into cost-conscious applications requiring significant control-processing and connectivity capabilities. the stellaris ? lm3s2000 series, designed for controller area network (can) applications, extends the stellaris family with bosch can networking technology , the golden standard in short-haul industrial networks. the stellaris ? lm3s2000 series also marks the first integration of can capabilities with the revolutionary cortex-m3 core. the stellaris ? lm3s6000 series combines both a 10/100 ethernet media access control (mac) and physical (phy) layer , marking the first time that integrated connectivity is available with an arm cortex-m3 mcu and the only integrated 10/100 ethernet mac and phy available in an arm architecture mcu. the lm3s8962 microcontroller is targeted for industrial applications, including remote monitoring, electronic point-of-sale machines, test and measurement equipment, network appliances and switches, factory automation, hv ac and building control, gaming equipment, motion control, medical instrumentation, and fire and security . for applications requiring extreme conservation of power , the lm3s8962 microcontroller features a battery-backed hibernation module to ef ficiently power down the lm3s8962 to a low-power state during extended periods of inactivity . with a power-up/power-down sequencer , a continuous time counter (r tc), a pair of match registers, an apb interface to the system bus, and dedicated non-volatile memory , the hibernation module positions the lm3s8962 microcontroller perfectly for battery applications. in addition, the lm3s8962 microcontroller of fers the advantages of arm's widely available development tools, system-on-chip (soc) infrastructure ip applications, and a large user community . additionally , the microcontroller uses arm's thumb?-compatible thumb-2 instruction set to reduce memory requirements and, thereby , cost. finally , the lm3s8962 microcontroller is code-compatible to all members of the extensive stellaris ? family; providing flexibility to fit our customers' precise needs. luminary micro of fers a complete solution to get to market quickly , with evaluation and development boards, white papers and application notes, an easy-to-use peripheral driver library , and a strong support, sales, and distributor network. 1.1 product features the lm3s8962 microcontroller includes the following product features: 32-bit risc performance C 32-bit arm? cortex?-m3 v7m architecture optimized for small-footprint embedded applications C system timer (syst ick), providing a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism C thumb?-compatible thumb-2-only instruction set processor core for high code density C 50-mhz operation 23 september 02, 2007 preliminary lm3s8962 microcontroller C hardware-division and single-cycle-multiplication C integrated nested v ectored interrupt controller (nvic) providing deterministic interrupt handling C 36 interrupts with eight priority levels C memory protection unit (mpu), providing a privileged mode for protected operating system functionality C unaligned data access, enabling data to be ef ficiently packed into memory C atomic bit manipulation (bit-banding), delivering maximum memory utilization and streamlined peripheral control internal memory C 256 kb single-cycle flash ? user-managed flash block protection on a 2-kb block basis ? user-managed flash data programming ? user-defined and managed flash-protection block C 64 kb single-cycle sram general-purpose t imers C four general-purpose t imer modules (gptm), each of which provides two 16-bit timer/counters. each gptm can be configured to operate independently as timers or event counters: as a single 32-bit timer , as one 32-bit real-t ime clock (r tc) to event capture, for pulse width modulation (pwm), or to trigger analog-to-digital conversions C 32-bit t imer modes ? programmable one-shot timer ? programmable periodic timer ? real-t ime clock when using an external 32.768-khz clock as the input ? user-enabled stalling in periodic and one-shot mode when the controller asserts the cpu halt flag during debug ? adc event trigger C 16-bit t imer modes ? general-purpose timer function with an 8-bit prescaler ? programmable one-shot timer ? programmable periodic timer ? user-enabled stalling when the controller asserts cpu halt flag during debug september 02, 2007 24 preliminary architectural overview ? adc event trigger C 16-bit input capture modes ? input edge count capture ? input edge time capture C 16-bit pwm mode ? simple pwm mode with software-programmable output inversion of the pwm signal arm firm-compliant w atchdog t imer C 32-bit down counter with a programmable load register C separate watchdog clock with an enable C programmable interrupt generation logic with interrupt masking C lock register protection from runaway software C reset generation logic with an enable/disable C user-enabled stalling when the controller asserts the cpu halt flag during debug controller area network (can) C supports can protocol version 2.0 part a/b C bit rates up to 1mb/s C 32 message objects, each with its own identifier mask C maskable interrupt C disable automatic retransmission mode for ttcan C programmable loop-back mode for self-test operation 10/100 ethernet controller C conforms to the ieee 802.3-2002 specification C ieee 1588-2002 precision t ime protocol (ptp) compliant C full- and half-duplex for both 100 mbps and 10 mbps operation C integrated 10/100 mbps t ransceiver (phy) C automatic mdi/mdi-x cross-over correction C programmable mac address C power-saving and power-down modes synchronous serial interface (ssi) 25 september 02, 2007 preliminary lm3s8962 microcontroller C master or slave operation C programmable clock bit rate and prescale C separate transmit and receive fifos, 16 bits wide, 8 locations deep C programmable interface operation for freescale spi, microwire, or t exas instruments synchronous serial interfaces C programmable data frame size from 4 to 16 bits C internal loopback test mode for diagnostic/debug testing uar t C t wo fully programmable 16c550-type uar t s with irda support C separate 16x8 transmit (tx) and 16x12 receive (rx) fifos to reduce cpu interrupt service loading C programmable baud-rate generator with fractional divider C programmable fifo length, including 1-byte deep operation providing conventional double-buf fered interface C fifo trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 C standard asynchronous communication bits for start, stop, and parity C false-start-bit detection C line-break generation and detection adc C single- and dif ferential-input configurations C four 10-bit channels (inputs) when used as single-ended inputs C sample rate of 500 thousand samples/second C flexible, configurable analog-to-digital conversion C four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result fifos C each sequence triggered by software or internal event (timers, analog comparators, pwm or gpio) C on-chip temperature sensor analog comparators C one integrated analog comparator september 02, 2007 26 preliminary architectural overview C configurable for output to: drive an output pin, generate an interrupt, or initiate an adc sample sequence C compare external pin input to external pin input or to internal programmable voltage reference i 2 c C master and slave receive and transmit operation with transmission speed up to 100 kbps in standard mode and 400 kbps in fast mode C interrupt generation C master with arbitration and clock synchronization, multimaster support, and 7-bit addressing mode pwm C three pwm generator blocks, each with one 16-bit counter , two comparators, a pwm generator , and a dead-band generator C one 16-bit counter ? runs in down or up/down mode ? output frequency controlled by a 16-bit load value ? load value updates can be synchronized ? produces output signals at zero and load value C t wo pwm comparators ? comparator value updates can be synchronized ? produces output signals on match C pwm generator ? output pwm signal is constructed based on actions taken as a result of the counter and pwm comparator output signals ? produces two independent pwm signals C dead-band generator ? produces two pwm signals with programmable dead-band delays suitable for driving a half-h bridge ? can be bypassed, leaving input pwm signals unmodified C flexible output control block with pwm output enable of each pwm signal ? pwm output enable of each pwm signal ? optional output inversion of each pwm signal (polarity control) 27 september 02, 2007 preliminary lm3s8962 microcontroller ? optional fault handling for each pwm signal ? synchronization of timers in the pwm generator blocks ? synchronization of timer/comparator updates across the pwm generator blocks ? interrupt status summary of the pwm generator blocks C can initiate an adc sample sequence qei C t wo qei modules C hardware position integrator tracks the encoder position C v elocity capture using built-in timer C interrupt generation on index pulse, velocity-timer expiration, direction change, and quadrature error detection gpios C 5-42 gpios, depending on configuration C 5-v-tolerant input/outputs C programmable interrupt generation as either edge-triggered or level-sensitive C bit masking in both read and write operations through address lines C can initiate an adc sample sequence C programmable control for gpio pad configuration: ? w eak pull-up or pull-down resistors ? 2-ma, 4-ma, and 8-ma pad drive ? slew rate control for the 8-ma drive ? open drain enables ? digital input enables power C on-chip low drop-out (ldo) voltage regulator , with programmable output user-adjustable from 2.25 v to 2.75 v C hibernation module handles the power-up/down 3.3 v sequencing and control for the core digital logic and analog circuits C low-power options on controller: sleep and deep-sleep modes C low-power options for peripherals: software controls shutdown of individual peripherals september 02, 2007 28 preliminary architectural overview C user-enabled ldo unregulated voltage detection and automatic reset C 3.3-v supply brown-out detection and reporting via interrupt or reset flexible reset sources C power-on reset (por) C reset pin assertion C brown-out (bor) detector alerts to system power drops C software reset C w atchdog timer reset C internal low drop-out (ldo) regulator output goes unregulated additional features C six reset sources C programmable clock source control C clock gating to individual peripherals for power savings C ieee 1 149.1-1990 compliant t est access port (t ap) controller C debug access via jt ag and serial wire interfaces C full jt ag boundary scan industrial-range 100-pin rohs-compliant lqfp package 1.2 t arget applications remote monitoring electronic point-of-sale (pos) machines t est and measurement equipment network appliances and switches factory automation hv ac and building control gaming equipment motion control medical instrumentation fire and security power and energy 29 september 02, 2007 preliminary lm3s8962 microcontroller t ransportation 1.3 high-level block diagram figure 1-1 on page 30 shows the features on the stellaris? fury-class family of devices. note: figure 1-1 on page 30 indicates the full set of features available on all the devices in the stellaris? fury-class family , not all the features on this specific device. figure 1-1. stellaris? fury-class family high-level block diagram september 02, 2007 30 preliminary architectural overview ldo voltage regulator 3 analog comparators analog 10-bit adc 8 channel 1 msps temp sensor clocks, reset system control 4 timer/pwm/ccp each 32-bit or 2x16-bit watchdog timer gpios system battery-backed hibernate r t c systick timer 64 kb sram 256 kb flash 2 quadrature encoder inputs 6 pwm outputs motion control dead-band generator comparators pwm generator pwm interrupt timer 3 uarts 2 ssi/spi 10/100 ethernet mac + phy 2 can 2 i 2 c serial interfaces arm ? cortex ? -m3 50 mhz jtag nvic swd 32 32 1.4 functional overview the following sections provide an overview of the features of the lm3s8962 microcontroller . the page number in parenthesis indicates where that feature is discussed in detail. ordering and support information can be found in ordering and contact information on page 620 . 1.4.1 arm cortex?-m3 1.4.1.1 processor core (see page 38 ) all members of the stellaris ? product family , including the lm3s8962 microcontroller , are designed around an arm cortex?-m3 processor core. the arm cortex-m3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low-power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. arm cortex-m3 processor core on page 38 provides an overview of the arm core; the core is detailed in the arm? cortex?-m3 t echnical reference manual . 1.4.1.2 system t imer (syst ick) cortex-m3 includes an integrated system timer , syst ick. syst ick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. the counter can be used in several dif ferent ways, for example: an r t os tick timer which fires at a programmable rate (for example, 100 hz) and invokes a syst ick routine. a high-speed alarm timer using the system clock. a variable rate alarm or signal timerthe duration is range-dependent on the reference clock used and the dynamic range of the counter . a simple counter . software can use this to measure time to completion and time used. an internal clock source control based on missing/meeting durations. the countflag bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. 1.4.1.3 nested v ectored interrupt controller (nvic) the lm3s8962 controller includes the arm nested v ectored interrupt controller (nvic) on the arm cortex-m3 core. the nvic and cortex-m3 prioritize and handle all exceptions. all exceptions are handled in handler mode. the processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the interrupt service routine (isr). the vector is fetched in parallel to the state saving, which enables ef ficient interrupt entry . the processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. software can set eight priority levels on 7 exceptions (system handlers) and 36 interrupts. interrupts on page 46 provides an overview of the nvic controller and the interrupt map. exceptions and interrupts are detailed in the arm? cortex?-m3 t echnical reference manual . 1.4.2 motor control peripherals t o enhance motor control, the lm3s8962 controller features pulse width modulation (pwm) outputs and the quadrature encoder interface (qei). 31 september 02, 2007 preliminary lm3s8962 microcontroller 1.4.2.1 pwm (see page 211 ) pulse width modulation (pwm) is a powerful technique for digitally encoding analog signal levels. high-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. t ypical applications include switching power supplies and motor control. on the lm3s8962, pwm motion control functionality can be achieved through dedicated, flexible motion control hardware (the pwm pins) or through the motion control features of the general-purpose timers (using the ccp pins). pwm pins (see page 507 ) the lm3s8962 pwm module consists of three pwm generator blocks and a control block. each pwm generator block contains one timer (16-bit down or up/down counter), two comparators, a pwm signal generator , a dead-band generator , and an interrupt/adc-trigger selector . the control block determines the polarity of the pwm signals, and which signals are passed through to the pins. each pwm generator block produces two pwm signals that can either be independent signals or a single pair of complementary signals with dead-band delays inserted. the output of the pwm generation blocks are managed by the output control block before being passed to the device pins. ccp pins (see page 211 ) the general-purpose t imer module's ccp (capture compare pwm) pins are software programmable to support a simple pwm mode with a software-programmable output inversion of the pwm signal. 1.4.2.2 qei (see page 543 ) a quadrature encoder , also known as a 2-channel incremental encoder , converts linear displacement into a pulse signal. by monitoring both the number of pulses and the relative phase of the two signals, you can track the position, direction of rotation, and speed. in addition, a third channel, or index signal, can be used to reset the position counter . the stellaris quadrature encoder with index (qei) module interprets the code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. in addition, it can capture a running estimate of the velocity of the encoder wheel. the lm3s8962 microcontroller includes two qei modules, which enables control of two motors at the same time. 1.4.3 analog peripherals t o handle analog signals, the lm3s8962 microcontroller of fers an analog-to-digital converter (adc). for support of analog signals, the lm3s8962 microcontroller of fers one analog comparator . 1.4.3.1 adc (see page 264 ) an analog-to-digital converter (adc) is a peripheral that converts a continuous analog voltage to a discrete digital number . the lm3s8962 adc module features 10-bit conversion resolution and supports four input channels, plus an internal temperature sensor . four buf fered sample sequences allow rapid sampling of up to eight analog input sources without controller intervention. each sample sequence provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequence priority . september 02, 2007 32 preliminary architectural overview 1.4.3.2 analog comparators (see page 496 ) an analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. a comparator can compare a test voltage against any one of these voltages: an individual external reference voltage a shared single external reference voltage a shared internal reference voltage the comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts or triggers to the adc to cause it to start capturing a sample sequence. the interrupt generation and adc triggering logic is separate. this means, for example, that an interrupt can be generated on a rising edge and the adc triggered on a falling edge. 1.4.4 serial communications peripherals the lm3s8962 controller supports both asynchronous and synchronous serial communications with: t wo fully programmable 16c550-type uar t s one ssi module one i 2 c module one can unit 1.4.4.1 uart (see page 297 ) a universal asynchronous receiver/t ransmitter (uar t) is an integrated circuit used for rs-232c serial communications, containing a transmitter (parallel-to-serial converter) and a receiver (serial-to-parallel converter), each clocked separately . the lm3s8962 controller includes two fully programmable 16c550-type uar t s that support data transfer speeds up to 460.8 kbps. (although similar in functionality to a 16c550 uar t , it is not register-compatible.) in addition, each uar t is capable of supporting irda. separate 16x8 transmit (tx) and 16x12 receive (rx) fifos reduce cpu interrupt service loading. the uar t can generate individually masked interrupts from the rx, tx, modem status, and error conditions. the module provides a single combined interrupt when any of the interrupts are asserted and are unmasked. 1.4.4.2 ssi (see page 338 ) synchronous serial interface (ssi) is a four-wire bi-directional communications interface. the lm3s8962 controller includes one ssi module that provides the functionality for synchronous serial communications with peripheral devices, and can be configured to use the freescale spi, microwire, or ti synchronous serial interface frame formats. the size of the data frame is also configurable, and can be set between 4 and 16 bits, inclusive. 33 september 02, 2007 preliminary lm3s8962 microcontroller the ssi module performs serial-to-parallel conversion on data received from a peripheral device, and parallel-to-serial conversion on data transmitted to a peripheral device. the tx and rx paths are buf fered with internal fifos, allowing up to eight 16-bit values to be stored independently . the ssi module can be configured as either a master or slave device. as a slave device, the ssi module can also be configured to disable its output, which allows a master device to be coupled with multiple slave devices. the ssi module also includes a programmable bit rate clock divider and prescaler to generate the output serial clock derived from the ssi module's input clock. bit rates are generated based on the input clock and the maximum bit rate is determined by the connected peripheral. 1.4.4.3 i 2 c (see page 375 ) the inter-integrated circuit (i 2 c) bus provides bi-directional data transfer through a two-wire design (a serial data line sda and a serial clock line scl). the i 2 c bus interfaces to external i 2 c devices such as serial memory (rams and roms), networking devices, lcds, tone generators, and so on. the i 2 c bus may also be used for system testing and diagnostic purposes in product development and manufacture. the lm3s8962 controller includes one i 2 c module that provides the ability to communicate to other ic devices over an i 2 c bus. the i 2 c bus supports devices that can both transmit and receive (write and read) data. devices on the i 2 c bus can be designated as either a master or a slave. the i 2 c module supports both sending and receiving data as either a master or a slave, and also supports the simultaneous operation as both a master and a slave. the four i 2 c modes are: master t ransmit, master receive, slave t ransmit, and slave receive. a stellaris ? i 2 c module can operate at two speeds: standard (100 kbps) and fast (400 kbps). both the i 2 c master and slave can generate interrupts. the i 2 c master generates interrupts when a transmit or receive operation completes (or aborts due to an error). the i 2 c slave generates interrupts when data has been sent or requested by a master . 1.4.4.4 controller area network (see page 410 ) controller area network (can) is a multicast shared serial-bus standard for connecting electronic control units (ecus). can was specifically designed to be robust in electromagnetically noisy environments and can utilize a dif ferential balanced line like rs-485 or a more robust twisted-pair wire. originally created for automotive purposes, now it is used in many embedded control applications (for example, industrial or medical). bit rates up to 1mb/s are possible at network lengths below 40 meters. decreased bit rates allow longer network distances (for example, 125 kb/s at 500m). a transmitter sends a message to all can nodes (broadcasting). each node decides on the basis of the identifier received whether it should process the message. the identifier also determines the priority that the message enjoys in competition for bus access. each can message can transmit from 0 to 8 bytes of user information. the lm3s8962 includes one can units. 1.4.4.5 ethernet controller (see page 451 ) ethernet is a frame-based computer networking technology for local area networks (lans). ethernet has been standardized as ieee 802.3. it defines a number of wiring and signaling standards for the physical layer , two means of network access at the media access control (mac)/data link layer , and a common addressing format. september 02, 2007 34 preliminary architectural overview the stellaris? ethernet controller consists of a fully integrated media access controller (mac) and network physical (phy) interface device. the ethernet controller conforms to ieee 802.3 specifications and fully supports 10base-t and 100base-tx standards. in addition, the ethernet controller supports automatic mdi/mdi-x cross-over correction. 1.4.5 system peripherals 1.4.5.1 programmable gpios (see page 164 ) general-purpose input/output (gpio) pins of fer flexibility for a variety of connections. the stellaris ? gpio module is composed of seven physical gpio blocks, each corresponding to an individual gpio port. the gpio module is firm-compliant (compliant to the arm foundation ip for real-t ime microcontrollers specification) and supports 5-42 programmable input/output pins. the number of gpios available depends on the peripherals being used (see signal t ables on page 561 for the signals available to each gpio pin). the gpio module features programmable interrupt generation as either edge-triggered or level-sensitive on all pins, programmable control for gpio pad configuration, and bit masking in both read and write operations through address lines. 1.4.5.2 four programmable t imers (see page 205 ) programmable timers can be used to count or time external events that drive the t imer input pins. the stellaris ? general-purpose t imer module (gptm) contains four gptm blocks. each gptm block provides two 16-bit timer/counters that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit real-t ime clock (r tc). t imers can also be used to trigger analog-to-digital (adc) conversions. when configured in 32-bit mode, a timer can run as a one-shot timer , periodic timer , or real-t ime clock (r tc). when in 16-bit mode, a timer can run as a one-shot timer or periodic timer , and can extend its precision by using an 8-bit prescaler . a 16-bit timer can also be configured for event capture or pulse width modulation (pwm) generation. 1.4.5.3 w atchdog t imer (see page 241 ) a watchdog timer can generate nonmaskable interrupts (nmis) or a reset when a time-out value is reached. the watchdog timer is used to regain control when a system has failed due to a software error or to the failure of an external device to respond in the expected way . the stellaris ? w atchdog t imer module consists of a 32-bit down counter , a programmable load register , interrupt generation logic, and a locking register . the w atchdog t imer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. once the w atchdog t imer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 1.4.6 memory peripherals the lm3s8962 controller of fers both single-cycle sram and single-cycle flash memory . 1.4.6.1 sram (see page 140 ) the lm3s8962 static random access memory (sram) controller supports 64 kb sram. the internal sram of the stellaris ? devices is located at of fset 0x0000.0000 of the device memory map. t o reduce the number of time-consuming read-modify-write (rmw) operations, arm has introduced bit-banding technology in the new cortex-m3 processor . with a bit-band-enabled processor , certain 35 september 02, 2007 preliminary lm3s8962 microcontroller regions in the memory map (sram and peripheral space) can use address aliases to access individual bits in a single, atomic operation. 1.4.6.2 flash (see page 141 ) the lm3s8962 flash controller supports 256 kb of flash memory . the flash is organized as a set of 1-kb blocks that can be individually erased. erasing a block causes the entire contents of the block to be reset to all 1s. these blocks are paired into a set of 2-kb blocks that can be individually protected. the blocks can be marked as read-only or execute-only , providing dif ferent levels of code protection. read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger . 1.4.7 additional features 1.4.7.1 memory map (see page 44 ) a memory map lists the location of instructions and data in memory . the memory map for the lm3s8962 controller can be found in memory map on page 44 . register addresses are given as a hexadecimal increment, relative to the module's base address as shown in the memory map. the arm? cortex?-m3 t echnical reference manual provides further information on the memory map. 1.4.7.2 jt ag t ap controller (see page 49 ) the joint t est action group (jt ag) port provides a standardized serial interface for controlling the t est access port (t ap) and associated test logic. the t ap , jt ag instruction register , and jt ag data registers can be used to test the interconnects of assembled printed circuit boards, obtain manufacturing information on the components, and observe and/or control the inputs and outputs of the controller during normal operation. the jt ag port provides a high degree of testability and chip-level access at a low cost. the jt ag port is comprised of the standard five pins: trst , tck , tms , tdi , and tdo . data is transmitted serially into the controller on tdi and out of the controller on tdo . the interpretation of this data is dependent on the current state of the t ap controller . for detailed information on the operation of the jt ag port and t ap controller , please refer to the ieee standard 1 149.1-t est access port and boundary-scan architecture . the luminary micro jt ag controller works with the arm jt ag controller built into the cortex-m3 core. this is implemented by multiplexing the tdo outputs from both jt ag controllers. arm jt ag instructions select the arm tdo output while luminary micro jt ag instructions select the luminary micro tdo outputs. the multiplexer is controlled by the luminary micro jt ag controller , which has comprehensive programming for the arm, luminary micro, and unimplemented jt ag instructions. 1.4.7.3 system control and clocks (see page 60 ) system control determines the overall operation of the device. it provides information about the device, controls the clocking of the device and individual peripherals, and handles reset detection and reporting. 1.4.7.4 hibernation module (see page 121 ) the hibernation module provides logic to switch power of f to the main processor and peripherals, and to wake on external or time-based events. the hibernation module includes power-sequencing logic, a real-time clock with a pair of match registers, low-battery detection circuitry , and interrupt september 02, 2007 36 preliminary architectural overview signalling to the processor . it also includes 64 32-bit words of non-volatile memory that can be used for saving state during hibernation. 1.4.8 hardware details details on the pins and package can be found in the following sections: pin diagram on page 560 signal t ables on page 561 operating characteristics on page 575 electrical characteristics on page 576 package information on page 591 37 september 02, 2007 preliminary lm3s8962 microcontroller 2 arm cortex-m3 processor core the arm cortex-m3 processor provides the core for a high-performance, low-cost platform that meets the needs of minimal memory implementation, reduced pin count, and low power consumption, while delivering outstanding computational performance and exceptional system response to interrupts. features include: compact core. thumb-2 instruction set, delivering the high-performance expected of an arm core in the memory size usually associated with 8- and 16-bit devices; typically in the range of a few kilobytes of memory for microcontroller class applications. rapid application execution through harvard architecture characterized by separate buses for instruction and data. exceptional interrupt handling, by implementing the register manipulations required for handling an interrupt in hardware. memory protection unit (mpu) to provide a privileged mode of operation for complex applications. migration from the arm7? processor family for better performance and power ef ficiency . full-featured debug solution with a: C serial wire jt ag debug port (swj-dp) C flash patch and breakpoint (fpb) unit for implementing breakpoints C data w atchpoint and t rigger (dwt) unit for implementing watchpoints, trigger resources, and system profiling C instrumentation t race macrocell (itm) for support of printf style debugging C t race port interface unit (tpiu) for bridging to a t race port analyzer the stellaris ? family of microcontrollers builds on this core to bring high-performance 32-bit computing to cost-sensitive embedded microcontroller applications, such as factory automation and control, industrial control power devices, building and home automation, and stepper motors. for more information on the arm cortex-m3 processor core, see the arm? cortex?-m3 t echnical reference manual . for information on swj-dp , see the arm? coresight t echnical reference manual . september 02, 2007 38 preliminary arm cortex-m3 processor core 2.1 block diagram figure 2-1. cpu block diagram 2.2 functional description important: the arm? cortex?-m3 t echnical reference manual describes all the features of an arm cortex-m3 in detail. however , these features dif fer based on the implementation. this section describes the stellaris ? implementation. luminary micro has implemented the arm cortex-m3 core as shown in figure 2-1 on page 39 . as noted in the arm? cortex?-m3 t echnical reference manual , several cortex-m3 components are flexible in their implementation: sw/jt ag-dp , etm, tpiu, the rom table, the mpu, and the nested v ectored interrupt controller (nvic). each of these is addressed in the sections that follow . 2.2.1 serial w ire and jt ag debug luminary micro has replaced the arm sw-dp and jt ag-dp with the arm coresight?-compliant serial wire jt ag debug port (swj-dp) interface. this means chapter 12, debug port, of the arm? cortex?-m3 t echnical reference manual does not apply to stellaris ? devices. the swj-dp interface combines the swd and jt ag debug ports into one module. see the coresight? design kit t echnical reference manual for details on swj-dp . 39 september 02, 2007 preliminary lm3s8962 microcontroller private peripheral bus ( internal) data w atchpoint and t race interrupts debug sleep instrumentation t race macrocell t race port interface unit cm3 core instructions data flash patch and breakpoint memory protection unit adv . high- perf . bus access port nested v ectored interrupt controller serial wire jt ag debug port bus matrix adv . peripheral bus i-code bus d-code bus system bus rom t able private peripheral bus ( external) serial wire output t race port ( swo) arm cortex -m3 2.2.2 embedded t race macrocell (etm) etm was not implemented in the stellaris ? devices. this means chapters 15 and 16 of the arm? cortex?-m3 t echnical reference manual can be ignored. 2.2.3 t race port interface unit (tpiu) the tpiu acts as a bridge between the cortex-m3 trace data from the itm, and an of f-chip t race port analyzer . the stellaris ? devices have implemented tpiu as shown in figure 2-2 on page 40 . this is similar to the non-etm version described in the arm? cortex?-m3 t echnical reference manual , however , swj-dp only provides swv output for the tpiu. figure 2-2. tpiu block diagram 2.2.4 rom t able the default rom table was implemented as described in the arm? cortex?-m3 t echnical reference manual . 2.2.5 memory protection unit (mpu) the memory protection unit (mpu) is included on the lm3s8962 controller and supports the standard armv7 protected memory system architecture (pmsa) model. the mpu provides full support for protection regions, overlapping protection regions, access permissions, and exporting memory attributes to the system. 2.2.6 nested v ectored interrupt controller (nvic) the nested v ectored interrupt controller (nvic): facilitates low-latency exception and interrupt handling controls power management implements system control registers september 02, 2007 40 preliminary arm cortex-m3 processor core a tb interface asynchronous fifo apb interface t race out ( serializer) debug a tb slave port apb slave port serial wire t race port ( swo) the nvic supports up to 240 dynamically reprioritizable interrupts each with up to 256 levels of priority . the nvic and the processor core interface are closely coupled, which enables low latency interrupt processing and ef ficient processing of late arriving interrupts. the nvic maintains knowledge of the stacked (nested) interrupts to enable tail-chaining of interrupts. y ou can only fully access the nvic from privileged mode, but you can pend interrupts in user-mode if you enable the configuration control register (see the arm? cortex?-m3 t echnical reference manual). any other user-mode access causes a bus fault. all nvic registers are accessible using byte, halfword, and word unless otherwise stated. all nvic registers and system debug registers are little endian regardless of the endianness state of the processor . 2.2.6.1 interrupts the arm? cortex?-m3 t echnical reference manual describes the maximum number of interrupts and interrupt priorities. the lm3s8962 microcontroller supports 36 interrupts with eight priority levels. 2.2.6.2 system t imer (syst ick) cortex-m3 includes an integrated system timer , syst ick. syst ick provides a simple, 24-bit clear-on-write, decrementing, wrap-on-zero counter with a flexible control mechanism. the counter can be used in several dif ferent ways, for example: an r t os tick timer which fires at a programmable rate (for example, 100 hz) and invokes a syst ick routine. a high-speed alarm timer using the system clock. a variable rate alarm or signal timerthe duration is range-dependent on the reference clock used and the dynamic range of the counter . a simple counter . software can use this to measure time to completion and time used. an internal clock source control based on missing/meeting durations. the countflag bit-field in the control and status register can be used to determine if an action completed within a set duration, as part of a dynamic clock management control loop. functional description the timer consists of three registers: a control and status counter to configure its clock, enable the counter , enable the syst ick interrupt, and determine counter status. the reload value for the counter , used to provide the counter's wrap value. the current value of the counter . a fourth register , the syst ick calibration v alue register , is not implemented in the stellaris ? devices. when enabled, the timer counts down from the reload value to zero, reloads (wraps) to the value in the syst ick reload v alue register on the next clock edge, then decrements on subsequent clocks. w riting a value of zero to the reload v alue register disables the counter on the next wrap. when the counter reaches zero, the countflag status bit is set. the countflag bit clears on reads. 41 september 02, 2007 preliminary lm3s8962 microcontroller w riting to the current v alue register clears the register and the countflag status bit. the write does not trigger the syst ick exception logic. on a read, the current value is the value of the register at the time the register is accessed. if the core is in debug state (halted), the counter will not decrement. the timer is clocked with respect to a reference clock. the reference clock can be the core clock or an external clock source. syst ick control and status register use the syst ick control and status register to enable the syst ick features. the reset is 0x0000.0000. description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:17 returns 1 if timer counted to 0 since last time this was read. clears on read by application. if read by the debugger using the dap , this bit is cleared on read-only if the mastert ype bit in the ahb-ap control register is set to 0. otherwise, the countflag bit is not changed by the debugger read. 0 r/w countflag 16 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:3 0 = external reference clock. (not implemented for stellaris microcontrollers.) 1 = core clock. if no reference clock is provided, it is held at 1 and so gives the same time as the core clock. the core clock must be at least 2.5 times faster than the reference clock. if it is not, the count values are unpredictable. 0 r/w clksource 2 1 = counting down to 0 pends the syst ick handler . 0 = counting down to 0 does not pend the syst ick handler . software can use the countflag to determine if ever counted to 0. 0 r/w tickint 1 1 = counter operates in a multi-shot way . that is, counter loads with the reload value and then begins counting down. on reaching 0, it sets the countflag to 1 and optionally pends the syst ick handler , based on tickint . it then loads the reload value again, and begins counting. 0 = counter disabled. 0 r/w enable 0 syst ick reload v alue register use the syst ick reload v alue register to specify the start value to load into the current value register when the counter reaches 0. it can be any value between 1 and 0x00ff .ffff . a start value of 0 is possible, but has no ef fect because the syst ick interrupt and countflag are activated when counting from 1 to 0. therefore, as a multi-shot timer , repeated over and over , it fires every n+1 clock pulse, where n is any value from 1 to 0x00ff .ffff . so, if the tick interrupt is required every 100 clock pulses, 99 must be written into the reload. if a new value is written on each tick interrupt, so treated as single shot, then the actual count down must be written. for example, if a tick is next required after 400 clock pulses, 400 must be written into the reload. description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:24 september 02, 2007 42 preliminary arm cortex-m3 processor core description reset t ype name bit/field v alue to load into the syst ick current v alue register when the counter reaches 0. - w1c reload 23:0 syst ick current v alue register use the syst ick current v alue register to find the current value in the register . description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:24 current value at the time the register is accessed. no read-modify-write protection is provided, so change with care. this register is write-clear . w riting to it with any value clears the register to 0. clearing this register also clears the countflag bit of the syst ick control and status register . - w1c current 23:0 syst ick calibration v alue register the syst ick calibration v alue register is not implemented. 43 september 02, 2007 preliminary lm3s8962 microcontroller 3 memory map the memory map for the lm3s8962 controller is provided in t able 3-1 on page 44 . in this manual, register addresses are given as a hexadecimal increment, relative to the module s base address as shown in the memory map. see also chapter 4, memory map in the arm? cortex?-m3 t echnical reference manual . important: in t able 3-1 on page 44 , addresses not listed are reserved. t able 3-1. memory map a for details on registers, see page ... description end start memory 144 on-chip flash b 0x0003.ffff 0x0000.0000 144 bit-banded on-chip sram c 0x2000.ffff 0x2000.0000 - reserved non-bit-banded sram space 0x21ff .ffff 0x2010.0000 140 bit-band alias of 0x2000.0000 through 0x200f .ffff 0x23ff .ffff 0x2200.0000 - reserved non-bit-banded sram space 0x3fff .ffff 0x2400.0000 firm peripherals 243 w atchdog timer 0x4000.0fff 0x4000.0000 170 gpio port a 0x4000.4fff 0x4000.4000 170 gpio port b 0x4000.5fff 0x4000.5000 170 gpio port c 0x4000.6fff 0x4000.6000 170 gpio port d 0x4000.7fff 0x4000.7000 349 ssi0 0x4000.8fff 0x4000.8000 304 uar t0 0x4000.cfff 0x4000.c000 304 uar t1 0x4000.dfff 0x4000.d000 peripherals 388 i2c master 0 0x4002.07ff 0x4002.0000 401 i2c slave 0 0x4002.0fff 0x4002.0800 170 gpio port e 0x4002.4fff 0x4002.4000 170 gpio port f 0x4002.5fff 0x4002.5000 170 gpio port g 0x4002.6fff 0x4002.6000 514 pwm 0x4002.8fff 0x4002.8000 547 qei0 0x4002.cfff 0x4002.c000 547 qei1 0x4002.dfff 0x4002.d000 216 t imer0 0x4003.0fff 0x4003.0000 216 t imer1 0x4003.1fff 0x4003.1000 216 t imer2 0x4003.2fff 0x4003.2000 216 t imer3 0x4003.3fff 0x4003.3000 270 adc 0x4003.8fff 0x4003.8000 496 analog comparators 0x4003.cfff 0x4003.c000 423 can0 controller 0x4004.0fff 0x4004.0000 september 02, 2007 44 preliminary memory map for details on registers, see page ... description end start 459 ethernet controller 0x4004.8fff 0x4004.8000 127 hibernation module 0x400f .cfff 0x400f .c000 144 flash control 0x400f .dfff 0x400f .d000 67 system control 0x400f .efff 0x400f .e000 - bit-banded alias of 0x4000.0000 through 0x400f .ffff 0x43ff .ffff 0x4200.0000 private peripheral bus arm? cortex?-m3 t echnical reference manual instrumentation t race macrocell (itm) 0xe000.0fff 0xe000.0000 data w atchpoint and t race (dwt) 0xe000.1fff 0xe000.1000 flash patch and breakpoint (fpb) 0xe000.2fff 0xe000.2000 reserved 0xe000.dfff 0xe000.3000 nested v ectored interrupt controller (nvic) 0xe000.efff 0xe000.e000 reserved 0xe003.ffff 0xe000.f000 t race port interface unit (tpiu) 0xe004.0fff 0xe004.0000 - reserved 0xe004.1fff 0xe004.1000 - reserved 0xe00f .ffff 0xe004.2000 - reserved for vendor peripherals 0xffff .ffff 0xe010.0000 a. all reserved space returns a bus fault when read or written. b. the unavailable flash will bus fault throughout this range. c. the unavailable sram will bus fault throughout this range. 45 september 02, 2007 preliminary lm3s8962 microcontroller 4 interrupts the arm cortex-m3 processor and the nested v ectored interrupt controller (nvic) prioritize and handle all exceptions. all exceptions are handled in handler mode. the processor state is automatically stored to the stack on an exception, and automatically restored from the stack at the end of the interrupt service routine (isr). the vector is fetched in parallel to the state saving, which enables ef ficient interrupt entry . the processor supports tail-chaining, which enables back-to-back interrupts to be performed without the overhead of state saving and restoration. t able 4-1 on page 46 lists all the exceptions. software can set eight priority levels on seven of these exceptions (system handlers) as well as on 36 interrupts (listed in t able 4-2 on page 47 ). priorities on the system handlers are set with the nvic system handler priority registers. interrupts are enabled through the nvic interrupt set enable register and prioritized with the nvic interrupt priority registers. y ou can also group priorities by splitting priority levels into pre-emption priorities and subpriorities. all the interrupt registers are described in chapter 8, nested v ectored interrupt controller in the arm? cortex?-m3 t echnical reference manual . internally , the highest user-settable priority (0) is treated as fourth priority , after a reset, nmi, and a hard fault. note that 0 is the default priority for all the settable priorities. if you assign the same priority level to two or more interrupts, their hardware priority (the lower the position number) determines the order in which the processor activates them. for example, if both gpio port a and gpio port b are priority level 1, then gpio port a has higher priority . see chapter 5, exceptions and chapter 8, nested v ectored interrupt controller in the arm? cortex?-m3 t echnical reference manual for more information on exceptions and interrupts. note: in t able 4-2 on page 47 interrupts not listed are reserved. t able 4-1. exception t ypes description priority a position exception t ype stack top is loaded from first entry of vector table on reset. - 0 - invoked on power up and warm reset. on first instruction, drops to lowest priority (and then is called the base level of activation). this is asynchronous. -3 (highest) 1 reset cannot be stopped or preempted by any exception but reset. this is asynchronous. an nmi is only producible by software, using the nvic interrupt control state register . -2 2 non-maskable interrupt (nmi) all classes of fault, when the fault cannot activate due to priority or the configurable fault handler has been disabled. this is synchronous. -1 3 hard fault mpu mismatch, including access violation and no match. this is synchronous. the priority of this exception can be changed. settable 4 memory management pre-fetch fault, memory access fault, and other address/memory related faults. this is synchronous when precise and asynchronous when imprecise. y ou can enable or disable this fault. settable 5 bus fault usage fault, such as undefined instruction executed or illegal state transition attempt. this is synchronous. settable 6 usage fault reserved. - 7-10 - system service call with svc instruction. this is synchronous. settable 1 1 svcall september 02, 2007 46 preliminary interrupts description priority a position exception t ype debug monitor (when not halting). this is synchronous, but only active when enabled. it does not activate if lower priority than the current activation. settable 12 debug monitor reserved. - 13 - pendable request for system service. this is asynchronous and only pended by software. settable 14 pendsv system tick timer has fired. this is asynchronous. settable 15 syst ick asserted from outside the arm cortex-m3 core and fed through the nvic (prioritized). these are all asynchronous. t able 4-2 on page 47 lists the interrupts on the lm3s8962 controller . settable 16 and above interrupts a. 0 is the default priority for all the settable priorities. t able 4-2. interrupts description interrupt (bit in interrupt registers) gpio port a 0 gpio port b 1 gpio port c 2 gpio port d 3 gpio port e 4 uar t0 5 uar t1 6 ssi0 7 i2c0 8 pwm fault 9 pwm generator 0 10 pwm generator 1 1 1 pwm generator 2 12 qei0 13 adc sequence 0 14 adc sequence 1 15 adc sequence 2 16 adc sequence 3 17 w atchdog timer 18 t imer0 a 19 t imer0 b 20 t imer1 a 21 t imer1 b 22 t imer2 a 23 t imer2 b 24 analog comparator 0 25 system control 28 flash control 29 gpio port f 30 gpio port g 31 47 september 02, 2007 preliminary lm3s8962 microcontroller description interrupt (bit in interrupt registers) t imer3 a 35 t imer3 b 36 qei1 38 can0 39 ethernet controller 42 hibernation module 43 reserved 44-47 september 02, 2007 48 preliminary interrupts 5 jt ag interface the joint t est action group (jt ag) port is an ieee standard that defines a t est access port and boundary scan architecture for digital integrated circuits and provides a standardized serial interface for controlling the associated test logic. the t ap , instruction register (ir), and data registers (dr) can be used to test the interconnections of assembled printed circuit boards and obtain manufacturing information on the components. the jt ag port also provides a means of accessing and controlling design-for-test features such as i/o pin observation and control, scan testing, and debugging. the jt ag port is comprised of the standard five pins: trst , tck , tms , tdi , and tdo . data is transmitted serially into the controller on tdi and out of the controller on tdo . the interpretation of this data is dependent on the current state of the t ap controller . for detailed information on the operation of the jt ag port and t ap controller , please refer to the ieee standard 1 149.1-t est access port and boundary-scan architecture . the luminary micro jt ag controller works with the arm jt ag controller built into the cortex-m3 core. this is implemented by multiplexing the tdo outputs from both jt ag controllers. arm jt ag instructions select the arm tdo output while luminary micro jt ag instructions select the luminary micro tdo outputs. the multiplexer is controlled by the luminary micro jt ag controller , which has comprehensive programming for the arm, lmi, and unimplemented jt ag instructions. the jt ag module has the following features: ieee 1 149.1-1990 compatible t est access port (t ap) controller four-bit instruction register (ir) chain for storing jt ag instructions ieee standard instructions: C byp ass instruction C idcode instruction C sample/preload instruction C extest instruction C intest instruction arm additional instructions: C ap acc instruction C dp acc instruction C abor t instruction integrated arm serial wire debug (swd) see the arm? cortex?-m3 t echnical reference manual for more information on the arm jt ag controller . 49 september 02, 2007 preliminary lm3s8962 microcontroller 5.1 block diagram figure 5-1. jt ag module block diagram 5.2 functional description a high-level conceptual drawing of the jt ag module is shown in figure 5-1 on page 50 . the jt ag module is composed of the t est access port (t ap) controller and serial shift chains with parallel update registers. the t ap controller is a simple state machine controlled by the trst , tck and tms inputs. the current state of the t ap controller depends on the current value of trst and the sequence of values captured on tms at the rising edge of tck . the t ap controller determines when the serial shift chains capture new data, shift data from tdi towards tdo , and update the parallel load registers. the current state of the t ap controller also determines whether the instruction register (ir) chain or one of the data register (dr) chains is being accessed. the serial shift chains with parallel load registers are comprised of a single instruction register (ir) chain and multiple data register (dr) chains. the current instruction loaded in the parallel load register determines which dr chain is captured, shifted, or updated during the sequencing of the t ap controller . some instructions, like extest and intest , operate on data currently in a dr chain and do not capture, shift, or update any of the chains. instructions that are not implemented decode to the byp ass instruction to ensure that the serial path between tdi and tdo is always connected (see t able 5-2 on page 56 for a list of implemented instructions). see jt ag and boundary scan on page 587 for jt ag timing diagrams. september 02, 2007 50 preliminary jt ag interface instr uction register (ir) t ap controller byp ass data register boundar y scan data register idcode data register abor t data register dp a cc data register ap a cc data register trst tck tms tdi tdo cor te x-m3 deb ug p or t 5.2.1 jt ag interface pins the jt ag interface consists of five standard pins: trst , tck , tms , tdi , and tdo . these pins and their associated reset state are given in t able 5-1 on page 51 . detailed information on each pin follows. t able 5-1. jt ag port pins reset state drive v alue drive strength internal pull-down internal pull-up data direction pin name n/a n/a disabled enabled input trst n/a n/a disabled enabled input tck n/a n/a disabled enabled input tms n/a n/a disabled enabled input tdi high-z 2-ma driver disabled enabled output tdo 5.2.1.1 t est reset input ( trst ) the trst pin is an asynchronous active low input signal for initializing and resetting the jt ag t ap controller and associated jt ag circuitry . when trst is asserted, the t ap controller resets to the t est-logic-reset state and remains there while trst is asserted. when the t ap controller enters the t est-logic-reset state, the jt ag instruction register (ir) resets to the default instruction, idcode. by default, the internal pull-up resistor on the trst pin is enabled after reset. changes to the pull-up resistor settings on gpio port b should ensure that the internal pull-up resistor remains enabled on pb7 / trst ; otherwise jt ag communication could be lost. 5.2.1.2 t est clock input (tck) the tck pin is the clock for the jt ag module. this clock is provided so the test logic can operate independently of any other system clocks. in addition, it ensures that multiple jt ag t ap controllers that are daisy-chained together can synchronously communicate serial test data between components. during normal operation, tck is driven by a free-running clock with a nominal 50% duty cycle. when necessary , tck can be stopped at 0 or 1 for extended periods of time. while tck is stopped at 0 or 1, the state of the t ap controller does not change and data in the jt ag instruction and data registers is not lost. by default, the internal pull-up resistor on the tck pin is enabled after reset. this assures that no clocking occurs if the pin is not driven from an external source. the internal pull-up and pull-down resistors can be turned of f to save internal power as long as the tck pin is constantly being driven by an external source. 5.2.1.3 t est mode select (tms) the tms pin selects the next state of the jt ag t ap controller . tms is sampled on the rising edge of tck . depending on the current t ap state and the sampled value of tms , the next state is entered. because the tms pin is sampled on the rising edge of tck , the ieee standard 1 149.1 expects the value on tms to change on the falling edge of tck . holding tms high for five consecutive tck cycles drives the t ap controller state machine to the t est-logic-reset state. when the t ap controller enters the t est-logic-reset state, the jt ag instruction register (ir) resets to the default instruction, idcode. therefore, this sequence can be used as a reset mechanism, similar to asserting trst . the jt ag t est access port state machine can be seen in its entirety in figure 5-2 on page 53 . 51 september 02, 2007 preliminary lm3s8962 microcontroller by default, the internal pull-up resistor on the tms pin is enabled after reset. changes to the pull-up resistor settings on gpio port c should ensure that the internal pull-up resistor remains enabled on pc1/tms ; otherwise jt ag communication could be lost. 5.2.1.4 t est data input (tdi) the tdi pin provides a stream of serial information to the ir chain and the dr chains. tdi is sampled on the rising edge of tck and, depending on the current t ap state and the current instruction, presents this data to the proper shift register chain. because the tdi pin is sampled on the rising edge of tck , the ieee standard 1 149.1 expects the value on tdi to change on the falling edge of tck . by default, the internal pull-up resistor on the tdi pin is enabled after reset. changes to the pull-up resistor settings on gpio port c should ensure that the internal pull-up resistor remains enabled on pc2/tdi ; otherwise jt ag communication could be lost. 5.2.1.5 t est data output (tdo) the tdo pin provides an output stream of serial information from the ir chain or the dr chains. the value of tdo depends on the current t ap state, the current instruction, and the data in the chain being accessed. in order to save power when the jt ag port is not being used, the tdo pin is placed in an inactive drive state when not actively shifting out data. because tdo can be connected to the tdi of another controller in a daisy-chain configuration, the ieee standard 1 149.1 expects the value on tdo to change on the falling edge of tck . by default, the internal pull-up resistor on the tdo pin is enabled after reset. this assures that the pin remains at a constant logic level when the jt ag port is not being used. the internal pull-up and pull-down resistors can be turned of f to save internal power if a high-z output value is acceptable during certain t ap controller states. 5.2.2 jt ag t ap controller the jt ag t ap controller state machine is shown in figure 5-2 on page 53 . the t ap controller state machine is reset to the t est-logic-reset state on the assertion of a power-on-reset (por) or the assertion of trst . asserting the correct sequence on the tms pin allows the jt ag module to shift in new instructions, shift in data, or idle during extended testing sequences. for detailed information on the function of the t ap controller and the operations that occur in each state, please refer to ieee standard 1 149.1 . september 02, 2007 52 preliminary jt ag interface figure 5-2. t est access port state machine 5.2.3 shift registers the shift registers consist of a serial shift register chain and a parallel load register . the serial shift register chain samples specific information during the t ap controller s capture states and allows this information to be shifted out of tdo during the t ap controller s shift states. while the sampled data is being shifted out of the chain on tdo , new data is being shifted into the serial shift register on tdi . this new data is stored in the parallel load register during the t ap controller s upda te states. each of the shift registers is discussed in detail in register descriptions on page 56 . 5.2.4 operational considerations there are certain operational considerations when using the jt ag module. because the jt ag pins can be programmed to be gpios, board configuration and reset conditions on these pins must be considered. in addition, because the jt ag module has integrated arm serial wire debug, the method for switching between these two operational modes is described below . 53 september 02, 2007 preliminary lm3s8962 microcontroller t est logic reset run t est idle select dr scan select ir scan capture dr capture ir shift dr shift ir exit 1 dr exit 1 ir exit 2 dr exit 2 ir pause dr pause ir update dr update ir 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5.2.4.1 gpio functionality when the controller is reset with either a por or rst , the jt ag/swd port pins default to their jt ag/swd configurations. the default configuration includes enabling digital functionality (setting gpioden to 1), enabling the pull-up resistors (setting gpiopur to 1), and enabling the alternate hardware function (setting gpioafsel to 1) for the pb7 and pc[3:0] jt ag/swd pins. it is possible for software to configure these pins as gpios after reset by writing 0s to pb7 and pc[3:0] in the gpioafsel register . if the user does not require the jt ag/swd port for debugging or board-level testing, this provides five more gpios for use in the design. caution C if the jt ag pins ar e used as gpios in a design, pb7 and pc2 cannot have external pull-down r esistors connected to both of them at the same time. if both pins ar e pulled low during r eset, the contr oller has unpr edictable behavior . if this happens, r emove one or both of the pull-down r esistors, and apply rst or power-cycle the part. in addition, it is possible to cr eate a softwar e sequence that pr events the debugger fr om connecting to the stellaris ? micr ocontr oller . if the pr ogram code loaded into fash immediately changes the jt ag pins to their gpio functionality , the debugger may not have enough time to connect and halt the contr oller befor e the jt ag pin functionality switches. this may lock the debugger out of the part. this can be avoided with a softwar e r outine that r estor es jt ag functionality based on an external or softwar e trigger . the commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. w rites to protected bits of the gpio alternate function select (gpioafsel) register (see page 180 ) are not committed to storage unless the gpio lock (gpiolock) register (see page 190 ) has been unlocked and the appropriate bits of the gpio commit (gpiocr) register (see page 191 ) have been set to 1. recovering a "locked" device if software configures any of the jt ag/swd pins as gpio and loses the ability to communicate with the debugger , there is a debug sequence that can be used to recover the device. performing a total of ten jt ag-to-swd and swd-to-jt ag switch sequences while holding the device in reset mass erases the flash memory . the sequence to recover the device is: 1. assert and hold the rst signal. 2. perform the jt ag-to-swd switch sequence. 3. perform the swd-to-jt ag switch sequence. 4. perform the jt ag-to-swd switch sequence. 5. perform the swd-to-jt ag switch sequence. 6. perform the jt ag-to-swd switch sequence. 7. perform the swd-to-jt ag switch sequence. 8. perform the jt ag-to-swd switch sequence. 9. perform the swd-to-jt ag switch sequence. 10. perform the jt ag-to-swd switch sequence. 1 1. perform the swd-to-jt ag switch sequence. september 02, 2007 54 preliminary jt ag interface 12. release the rst signal. the jt ag-to-swd and swd-to-jt ag switch sequences are described in arm serial wire debug (swd) on page 55 . when performing switch sequences for the purpose of recovering the debug capabilities of the device, only steps 1 and 2 of the switch sequence need to be performed. 5.2.4.2 arm serial w ire debug (swd) in order to seamlessly integrate the arm serial wire debug (swd) functionality , a serial-wire debugger must be able to connect to the cortex-m3 core without having to perform, or have any knowledge of, jt ag cycles. this is accomplished with a swd preamble that is issued before the swd session begins. the preamble used to enable the swd interface of the swj-dp module starts with the t ap controller in the t est-logic-reset state. from here, the preamble sequences the t ap controller through the following states: run t est idle, select dr, select ir, t est logic reset, t est logic reset, run t est idle, run t est idle, select dr, select ir, t est logic reset, t est logic reset, run t est idle, run t est idle, select dr, select ir, and t est logic reset states. stepping through this sequences of the t ap state machine enables the swd interface and disables the jt ag interface. for more information on this operation and the swd interface, see the arm? cortex?-m3 t echnical reference manual and the arm? coresight t echnical reference manual . because this sequence is a valid series of jt ag operations that could be issued, the arm jt ag t ap controller is not fully compliant to the ieee standard 1 149.1 . this is the only instance where the arm jt ag t ap controller does not meet full compliance with the specification. due to the low probability of this sequence occurring during normal operation of the t ap controller , it should not af fect normal performance of the jt ag interface. jt ag-to-swd switching t o switch the operating mode of the debug access port (dap) from jt ag to swd mode, the external debug hardware must send a switch sequence to the device. the 16-bit switch sequence for switching to swd mode is defined as b1 1 1001 1 1 1001 1 1 10, transmitted lsb first. this can also be represented as 16'he79e when transmitted lsb first. the complete switch sequence should consist of the following transactions on the tck / swclk and tms / swdio signals: 1. send at least 50 tck / swclk cycles with tms / swdio set to 1. this ensures that both jt ag and swd are in their reset/idle states. 2. send the 16-bit jt ag-to-swd switch sequence, 16'he79e. 3. send at least 50 tck / swclk cycles with tms / swdio set to 1. this ensures that if swj-dp was already in swd mode, before sending the switch sequence, the swd goes into the line reset state. swd-to-jt ag switching t o switch the operating mode of the debug access port (dap) from swd to jt ag mode, the external debug hardware must send a switch sequence to the device. the 16-bit switch sequence for switching to jt ag mode is defined as b1 1 1001 1 1 1001 1 1 10, transmitted lsb first. this can also be represented as 16'he73c when transmitted lsb first. the complete switch sequence should consist of the following transactions on the tck / swclk and tms / swdio signals: 1. send at least 50 tck / swclk cycles with tms / swdio set to 1. this ensures that both jt ag and swd are in their reset/idle states. 55 september 02, 2007 preliminary lm3s8962 microcontroller 2. send the 16-bit swd-to-jt ag switch sequence, 16'he73c. 3. send at least 5 tck / swclk cycles with tms / swdio set to 1. this ensures that if swj-dp was already in jt ag mode, before sending the switch sequence, the jt ag goes into the t est logic reset state. 5.3 initialization and configuration after a power-on-reset or an external reset ( rst ), the jt ag pins are automatically configured for jt ag communication. no user-defined initialization or configuration is needed. however , if the user application changes these pins to their gpio function, they must be configured back to their jt ag functionality before jt ag communication can be restored. this is done by enabling the five jt ag pins ( pb7 and pc[3:0] ) for their alternate function using the gpioafsel register . 5.4 register descriptions there are no apb-accessible registers in the jt ag t ap controller or shift register chains. the registers within the jt ag controller are all accessed serially through the t ap controller . the registers can be broken down into two main categories: instruction registers and data registers. 5.4.1 instruction register (ir) the jt ag t ap instruction register (ir) is a four-bit serial scan chain with a parallel load register connected between the jt ag tdi and tdo pins. when the t ap controller is placed in the correct states, bits can be shifted into the instruction register . once these bits have been shifted into the chain and updated, they are interpreted as the current instruction. the decode of the instruction register bits is shown in t able 5-2 on page 56 . a detailed explanation of each instruction, along with its associated data register , follows. t able 5-2. jt ag instruction register commands description instruction ir[3:0] drives the values preloaded into the boundary scan chain by the sample/preload instruction onto the pads. extest 0000 drives the values preloaded into the boundary scan chain by the sample/preload instruction into the controller . intest 0001 captures the current i/o values and shifts the sampled values out of the boundary scan chain while new preload data is shifted in. sample / preload 0010 shifts data into the arm debug port abort register . abor t 1000 shifts data into and out of the arm dp access register . dp acc 1010 shifts data into and out of the arm ac access register . ap acc 101 1 loads manufacturing information defined by the ieee standard 1 149.1 into the idcode chain and shifts it out. idcode 1 1 10 connects tdi to tdo through a single shift register chain. byp ass 1 1 1 1 defaults to the byp ass instruction to ensure that tdi is always connected to tdo . reserved all others 5.4.1.1 extest instruction the extest instruction does not have an associated data register chain. the extest instruction uses the data that has been preloaded into the boundary scan data register using the sample/preload instruction. when the extest instruction is present in the instruction register , the preloaded data in the boundary scan data register associated with the outputs and output enables are used to drive the gpio pads rather than the signals coming from the core. this allows september 02, 2007 56 preliminary jt ag interface tests to be developed that drive known values out of the controller , which can be used to verify connectivity . 5.4.1.2 intest instruction the intest instruction does not have an associated data register chain. the intest instruction uses the data that has been preloaded into the boundary scan data register using the sample/preload instruction. when the intest instruction is present in the instruction register , the preloaded data in the boundary scan data register associated with the inputs are used to drive the signals going into the core rather than the signals coming from the gpio pads. this allows tests to be developed that drive known values into the controller , which can be used for testing. it is important to note that although the rst input pin is on the boundary scan data register chain, it is only observable. 5.4.1.3 sample/preload instruction the sample/preload instruction connects the boundary scan data register chain between tdi and tdo . this instruction samples the current state of the pad pins for observation and preloads new test data. each gpio pad has an associated input, output, and output enable signal. when the t ap controller enters the capture dr state during this instruction, the input, output, and output-enable signals to each of the gpio pads are captured. these samples are serially shifted out of tdo while the t ap controller is in the shift dr state and can be used for observation or comparison in various tests. while these samples of the inputs, outputs, and output enables are being shifted out of the boundary scan data register , new data is being shifted into the boundary scan data register from tdi . once the new data has been shifted into the boundary scan data register , the data is saved in the parallel load registers when the t ap controller enters the update dr state. this update of the parallel load register preloads data into the boundary scan data register that is associated with each input, output, and output enable. this preloaded data can be used with the extest and intest instructions to drive data into or out of the controller . please see boundary scan data register on page 59 for more information. 5.4.1.4 abort instruction the abor t instruction connects the associated abor t data register chain between tdi and tdo . this instruction provides read and write access to the abor t register of the arm debug access port (dap). shifting the proper data into this data register clears various error bits or initiates a dap abort of a previous request. please see the abor t data register on page 59 for more information. 5.4.1.5 dp acc instruction the dp acc instruction connects the associated dp acc data register chain between tdi and tdo . this instruction provides read and write access to the dp acc register of the arm debug access port (dap). shifting the proper data into this register and reading the data output from this register allows read and write access to the arm debug and status registers. please see dp acc data register on page 59 for more information. 5.4.1.6 ap acc instruction the ap acc instruction connects the associated ap acc data register chain between tdi and tdo . this instruction provides read and write access to the ap acc register of the arm debug access port (dap). shifting the proper data into this register and reading the data output from this register allows read and write access to internal components and buses through the debug port. please see ap acc data register on page 59 for more information. 57 september 02, 2007 preliminary lm3s8962 microcontroller 5.4.1.7 idcode instruction the idcode instruction connects the associated idcode data register chain between tdi and tdo . this instruction provides information on the manufacturer , part number , and version of the arm core. this information can be used by testing equipment and debuggers to automatically configure their input and output data streams. idcode is the default instruction that is loaded into the jt ag instruction register when a power-on-reset (por) is asserted, trst is asserted, or the t est-logic-reset state is entered. please see idcode data register on page 58 for more information. 5.4.1.8 byp ass instruction the byp ass instruction connects the associated byp ass data register chain between tdi and tdo . this instruction is used to create a minimum length serial path between the tdi and tdo ports. the byp ass data register is a single-bit shift register . this instruction improves test ef ficiency by allowing components that are not needed for a specific test to be bypassed in the jt ag scan chain by loading them with the byp ass instruction. please see byp ass data register on page 58 for more information. 5.4.2 data registers the jt ag module contains six data registers. these include: idcode, byp ass, boundary scan, ap acc, dp acc, and abor t serial data register chains. each of these data registers is discussed in the following sections. 5.4.2.1 idcode data register the format for the 32-bit idcode data register defined by the ieee standard 1 149.1 is shown in figure 5-3 on page 58 . the standard requires that every jt ag-compliant device implement either the idcode instruction or the byp ass instruction as the default instruction. the lsb of the idcode data register is defined to be a 1 to distinguish it from the byp ass instruction, which has an lsb of 0. this allows auto configuration test tools to determine which instruction is the default instruction. the major uses of the jt ag port are for manufacturer testing of component assembly , and program development and debug. t o facilitate the use of auto-configuration debug tools, the idcode instruction outputs a value of 0x3ba00477. this value indicates an arm cortex-m3, v ersion 1 processor . this allows the debuggers to automatically configure themselves to work correctly with the cortex-m3 during debug. figure 5-3. idcode register format 5.4.2.2 byp ass data register the format for the 1-bit byp ass data register defined by the ieee standard 1 149.1 is shown in figure 5-4 on page 59 . the standard requires that every jt ag-compliant device implement either the byp ass instruction or the idcode instruction as the default instruction. the lsb of the byp ass data register is defined to be a 0 to distinguish it from the idcode instruction, which has an lsb of 1. this allows auto configuration test tools to determine which instruction is the default instruction. september 02, 2007 58 preliminary jt ag interface figure 5-4. byp ass register format 5.4.2.3 boundary scan data register the format of the boundary scan data register is shown in figure 5-5 on page 59 . each gpio pin, in a counter-clockwise direction from the jt ag port pins, is included in the boundary scan data register . each gpio pin has three associated digital signals that are included in the chain. these signals are input, output, and output enable, and are arranged in that order as can be seen in the figure. in addition to the gpio pins, the controller reset pin, rst , is included in the chain. because the reset pin is always an input, only the input signal is included in the data register chain. when the boundary scan data register is accessed with the sample/preload instruction, the input, output, and output enable from each digital pad are sampled and then shifted out of the chain to be verified. the sampling of these values occurs on the rising edge of tck in the capture dr state of the t ap controller . while the sampled data is being shifted out of the boundary scan chain in the shift dr state of the t ap controller , new data can be preloaded into the chain for use with the extest and intest instructions. these instructions either force data out of the controller , with the extest instruction, or into the controller , with the intest instruction. figure 5-5. boundary scan register format for detailed information on the order of the input, output, and output enable bits for each of the gpio ports, please refer to the stellaris ? family boundary scan description language (bsdl) files, downloadable from www .luminarymicro.com. 5.4.2.4 ap acc data register the format for the 35-bit ap acc data register defined by arm is described in the arm? cortex?-m3 t echnical reference manual . 5.4.2.5 dp acc data register the format for the 35-bit dp acc data register defined by arm is described in the arm? cortex?-m3 t echnical reference manual . 5.4.2.6 abort data register the format for the 35-bit abor t data register defined by arm is described in the arm? cortex?-m3 t echnical reference manual . 59 september 02, 2007 preliminary lm3s8962 microcontroller o t d o t d i o i n e u t o o i n e u t o o i n e u t o o i n e u t i n ... ... r s t g p i o p b 6 g p i o m g p i o m + 1 g p i o n 6 system control system control determines the overall operation of the device. it provides information about the device, controls the clocking to the core and individual peripherals, and handles reset detection and reporting. 6.1 functional description the system control module provides the following capabilities: device identification, see device identification on page 60 local control, such as reset (see reset control on page 60 ), power (see power control on page 63 ) and clock control (see clock control on page 63 ) system control (run, sleep, and deep-sleep modes), see system control on page 65 6.1.1 device identification seven read-only registers provide software with information on the microcontroller , such as version, part number , sram size, flash size, and other features. see the did0 , did1 , and dc0 - dc4 registers. 6.1.2 reset control this section discusses aspects of hardware functions during reset as well as system software requirements following the reset sequence. 6.1.2.1 cmod0 and cmod1 t est-mode control pins t wo pins, cmod0 and cmod1 , are defined for use by luminary micro for testing the devices during manufacture. they have no end-user function and should not be used. the cmod pins should be connected to ground. 6.1.2.2 reset sources the controller has five sources of reset: 1. external reset input pin ( rst ) assertion, see rst pin assertion on page 60 . 2. power-on reset (por), see power-on reset (por) on page 61 . 3. internal brown-out (bor) detector , see brown-out reset (bor) on page 61 . 4. software-initiated reset (with the software reset registers), see software reset on page 62 . 5. a watchdog timer reset condition violation, see w atchdog t imer reset on page 62 . after a reset, the reset cause (resc) register is set with the reset cause. the bits in this register are sticky and maintain their state across multiple reset sequences, except when an internal por is the cause, and then all the other bits in the resc register are cleared except for the por indicator . 6.1.2.3 rst pin assertion the external reset pin ( rst ) resets the controller . this resets the core and all the peripherals except the jt ag t ap controller (see jt ag interface on page 49 ). the external reset sequence is as follows: september 02, 2007 60 preliminary system control 1. the external reset pin ( rst ) is asserted and then de-asserted. 2. the internal reset is released and the core loads from memory the initial stack pointer , the initial program counter , the first instruction designated by the program counter , and begins execution. a few clocks cycles from rst de-assertion to the start of the reset sequence is necessary for synchronization. the external reset timing is shown in figure 24-1 1 on page 589 . 6.1.2.4 power-on reset (por) the power-on reset (por) circuit monitors the power supply voltage (v dd ). the por circuit generates a reset signal to the internal logic when the power supply ramp reaches a threshold value (v th ). if the application only uses the por circuit, the rst input needs to be connected to the power supply (v dd ) through a pull-up resistor (1k to 10k ?). the device must be operating within the specified operating parameters at the point when the on-chip power-on reset pulse is complete. the 3.3-v power supply to the device must reach 3.0 v within 10 msec of it crossing 2.0 v to guarantee proper operation. for applications that require the use of an external reset to hold the device in reset longer than the internal por, the rst input may be used with the circuit as shown in figure 6-1 on page 61 . figure 6-1. external circuitry to extend reset the r 1 and c 1 components define the power-on delay . the r 2 resistor mitigates any leakage from the rst input. the diode (d 1 ) discharges c 1 rapidly when the power supply is turned of f. the power-on reset sequence is as follows: 1. the controller waits for the later of external reset ( rst ) or internal por to go inactive. 2. the internal reset is released and the core loads from memory the initial stack pointer , the initial program counter , the first instruction designated by the program counter , and begins execution. the internal por is only active on the initial power-up of the controller . the power-on reset timing is shown in figure 24-12 on page 590 . note: the power-on reset also resets the jt ag controller . an external reset does not. 6.1.2.5 brown-out reset (bor) a drop in the input voltage resulting in the assertion of the internal brown-out detector can be used to reset the controller . this is initially disabled and may be enabled by software. the system provides a brown-out detection circuit that triggers if the power supply (v dd ) drops below a brown-out threshold voltage (v bth ). if a brown-out condition is detected, the system may generate a controller interrupt or a system reset. 61 september 02, 2007 preliminary lm3s8962 microcontroller r 1 c 1 r 2 rst stellaris d 1 brown-out resets are controlled with the power-on and brown-out reset control (pborctl) register . the borior bit in the pborctl register must be set for a brown-out condition to trigger a reset. the brown-out reset is equivelent to an assertion of the external rst input and the reset is held active until the proper v dd level is restored. the resc register can be examined in the reset interrupt handler to determine if a brown-out condition was the cause of the reset, thus allowing software to determine what actions are required to recover . the internal brown-out reset timing is shown in figure 24-13 on page 590 . 6.1.2.6 software reset software can reset a specific peripheral or generate a reset to the entire system . peripherals can be individually reset by software via three registers that control reset signals to each peripheral (see the srcrn registers). if the bit position corresponding to a peripheral is set and subsequently cleared, the peripheral is reset. the encoding of the reset registers is consistent with the encoding of the clock gating control for peripherals and on-chip functions (see system control on page 65 ). note that all reset signals for all clocks of the specified unit are asserted as a result of a software-initiated reset. the entire system can be reset by software by setting the sysresetreq bit in the cortex-m3 application interrupt and reset control register resets the entire system including the core. the software-initiated system reset sequence is as follows: 1. a software system reset is initiated by writing the sysresetreq bit in the arm cortex-m3 application interrupt and reset control register . 2. an internal reset is asserted. 3. the internal reset is deasserted and the controller loads from memory the initial stack pointer , the initial program counter , and the first instruction designated by the program counter , and then begins execution. the software-initiated system reset timing is shown in figure 24-14 on page 590 . 6.1.2.7 w atchdog t imer reset the watchdog timer module's function is to prevent system hangs. the watchdog timer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. after the first time-out event, the 32-bit counter is reloaded with the value of the w atchdog t imer load (wdtload) register , and the timer resumes counting down from that value. if the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled, the watchdog timer asserts its reset signal to the system. the watchdog timer reset sequence is as follows: 1. the watchdog timer times out for the second time without being serviced. 2. an internal reset is asserted. 3. the internal reset is released and the controller loads from memory the initial stack pointer , the initial program counter , the first instruction designated by the program counter , and begins execution. september 02, 2007 62 preliminary system control the watchdog reset timing is shown in figure 24-15 on page 590 . 6.1.3 power control the stellaris ? microcontroller provides an integrated ldo regulator that may be used to provide power to the majority of the controller's internal logic. the ldo regulator provides software a mechanism to adjust the regulated value, in small increments (vstep), over the range of 2.25 v to 2.75 v (inclusive)or 2.5 v 10%. the adjustment is made by changing the value of the vadj field in the ldo power control (ldopctl) register . note: the use of the ldo is optional. the internal logic may be supplied by the on-chip ldo or by an external regulator . if the ldo is used, the ldo output pin is connected to the vdd25 pins on the printed circuit board. the ldo requires decoupling capacitors on the printed circuit board. if an external regulator is used, it is strongly recommended that the external regulator supply the controller only and not be shared with other devices on the printed circuit board. 6.1.4 clock control system control determines the control of clocks in this part. 6.1.4.1 fundamental clock sources there are four clock sources for use in the device: internal oscillator (iosc): the internal oscillator is an on-chip clock source. it does not require the use of any external components. the frequency of the internal oscillator is 12 mhz 30%. applications that do not depend on accurate clock sources may use this clock source to reduce system cost. the internal oscillator is the clock source the device uses during and following por. if the main oscillator is required, software must enable the main oscillator following reset and allow the main oscillator to stabilize before changing the clock reference. main oscillator: the main oscillator provides a frequency-accurate clock source by one of two means: an external single-ended clock source is connected to the osc0 input pin, or an external crystal is connected across the osc0 input and osc1 output pins. the crystal value allowed depends on whether the main oscillator is used as the clock reference source to the pll. if so, the crystal must be one of the supported frequencies between 3.579545 mhz through 8.192 mhz (inclusive). if the pll is not being used, the crystal may be any one of the supported frequencies between 1 mhz and 8.192 mhz. the single-ended clock source range is from dc through the specified speed of the device. the supported crystals are listed in page 76 on page ? . internal 30-khz oscillator: the internal 30-khz oscillator is similar to the internal oscillator , except that it provides an operational frequency of 30 khz 30%. it is intended for use during deep-sleep power-saving modes. this power-savings mode benefits from reduced internal switching and also allows the main oscillator to be powered down. external real-t ime oscillator: the external real-time oscillator provides a low-frequency , accurate clock reference. it is intended to provide the system with a real-time clock source. the real-time oscillator is part of the hibernation module ( hibernation module on page 121 ) and may also provide an accurate source of deep-sleep or hibernate mode power savings. the internal system clock (sysclk), is derived from any of the four sources plus two others: the output of the internal pll, and the internal oscillator divided by four (3 mhz 30%). the frequency of the pll clock reference must be in the range of 3.579545 mhz to 8.192 mhz (inclusive). 63 september 02, 2007 preliminary lm3s8962 microcontroller the run-mode clock configuration (rcc) and run-mode clock configuration 2 (rcc2) registers provide control for the system clock. the rcc2 register is provided to extend fields that of fer additional encodings over the rcc register . when used, the rcc2 register field values are used by the logic over the corresponding field in the rcc register . in particular , rcc2 provides for a larger assortment of clock configuration options. 6.1.4.2 crystal configuration for the main oscillator (mosc) the main oscillator supports the use of a select number of crystals. if the main oscillator is used by the pll as a reference clock, the supported range of crystals is 3.579545 to 8.192 mhz, otherwise, the range of supported crystals is 1 to 8.192 mhz. page 76 on page ? describes the available crystal choices and default programming values. software configures the rcc register xtal field with the crystal number . if the pll is used in the design, the xtal field value is internally translated to the pll settings. 6.1.4.3 pll frequency configuration the pll is disabled by default during power-on reset and is enabled later by software if required. software configures the pll input reference clock source, specifies the output divisor to set the system clock frequency , and enables the pll to drive the output. if the main oscillator provides the clock reference to the pll, the translation provided by hardware and used to program the pll is available for software in the xt al to pll t ranslation (pllcfg) register (see page 80 ). the internal translation provides a translation within 1% of the targeted pll vco frequency . page 76 on page ? describes the available crystal choices and default programming of the pllcfg register . the crystal number is written into the xtal field of the run-mode clock configuration (rcc) register . any time the xtal field changes, the new settings are translated and the internal pll settings are updated. 6.1.4.4 pll modes the pll has two modes of operation: normal and power-down normal: the pll multiplies the input clock reference and drives the output. power-down: most of the pll internal circuitry is disabled and the pll does not drive the output. the modes are programmed using the rcc / rcc2 register fields (see page 76 and page 81 ). 6.1.4.5 pll operation if the pll configuration is changed, the pll output frequency is unstable until it reconverges (relocks) to the new setting. the time between the configuration change and relock is t ready (see t able 24-6 on page 579 ). during this time, the pll is not usable as a clock reference. the pll is changed by one of the following: change to the xtal value in the rcc registerwrites of the same value do not cause a relock. change in the pll from power-down to normal mode. a counter is defined to measure the t ready requirement. the counter is clocked by the main oscillator . the range of the main oscillator has been taken into account and the down counter is set to 0x1200 (that is, ~600 s at an 8.192 mhz external oscillator clock). hardware is provided to keep september 02, 2007 64 preliminary system control the pll from being used as a system clock until the t ready condition is met after one of the two changes above. it is the user's responsibility to have a stable clock source (like the main oscillator) before the rcc / rcc2 register is switched to use the pll. 6.1.5 system control for power-savings purposes, the rcgcn , scgcn , and dcgcn registers control the clock gating logic for each peripheral or block in the system while the controller is in run, sleep, and deep-sleep mode, respectively . in run mode, the processor executes code. in sleep mode, the clock frequency of the active peripherals is unchanged, but the processor is not clocked and therefore no longer executes code. in deep-sleep mode, the clock frequency of the active peripherals may change (depending on the run mode clock configuration) in addition to the processor clock being stopped. an interrupt returns the device to run mode from one of the sleep modes; the sleep modes are entered on request from the code. each mode is described in more detail below . there are four levels of operation for the device defined as: run mode. run mode provides normal operation of the processor and all of the peripherals that are currently enabled by the rcgcn registers. the system clock can be any of the available clock sources including the pll. sleep mode. sleep mode is entered by the cortex-m3 core executing a wfi (wait for interrupt) instruction. any properly configured interrupt event in the system will bring the processor back into run mode. see the system control nvic section of the arm? cortex?-m3 t echnical reference manual for more details. in sleep mode, the cortex-m3 processor core and the memory subsystem are not clocked. peripherals are clocked that are enabled in the scgcn register when auto-clock gating is enabled (see the rcc register) or the rcgcn register when the auto-clock gating is disabled. the system clock has the same source and frequency as that during run mode. deep-sleep mode. deep-sleep mode is entered by first writing the deep sleep enable bit in the arm cortex-m3 nvic system control register and then executing a wfi instruction. any properly configured interrupt event in the system will bring the processor back into run mode. see the system control nvic section of the arm? cortex?-m3 t echnical reference manual for more details. the cortex-m3 processor core and the memory subsystem are not clocked. peripherals are clocked that are enabled in the dcgcn register when auto-clock gating is enabled (see the rcc register) or the rcgcn register when auto-clock gating is disabled. the system clock source is the main oscillator by default or the internal oscillator specified in the dslpclkcfg register if one is enabled. when the dslpclkcfg register is used, the internal oscillator is powered up, if necessary , and the main oscillator is powered down. if the pll is running at the time of the wfi instruction, hardware will power the pll down and override the sysdiv field of the active rcc / rcc2 register to be /16 or /64, respectively . when the deep-sleep exit event occurs, hardware brings the system clock back to the source and frequency it had at the onset of deep-sleep mode before enabling the clocks that had been stopped during the deep-sleep duration. hibernate mode. in this mode, the power supplies are turned of f to the main part of the device and only the hibernation module's circuitry is active. an external wake event or r tc event is required to bring the device back to run mode. the cortex-m3 processor and peripherals outside of the hibernation module see a normal "power on" sequence and the processor starts running 65 september 02, 2007 preliminary lm3s8962 microcontroller code. it can determine that it has been restarted from hibernate mode by inspecting the hibernation module registers. 6.2 initialization and configuration the pll is configured using direct register writes to the rcc / rcc2 register . if the rcc2 register is being used, the usercc2 bit must be set and the appropriate rcc2 bit/field is used. the steps required to successfully change the pll-based system clock are: 1. bypass the pll and system clock divider by setting the bypass bit and clearing the usesys bit in the rcc register . this configures the system to run of f a raw clock source (using the main oscillator or internal oscillator) and allows for the new pll configuration to be validated before switching the system clock to the pll. 2. select the crystal value ( xtal ) and oscillator source ( oscsrc ), and clear the pwrdn bit in rcc / rcc2 . setting the xtal field automatically pulls valid pll configuration data for the appropriate crystal, and clearing the pwrdn bit powers and enables the pll and its output. 3. select the desired system divider ( sysdiv ) in rcc / rcc2 and set the usesys bit in rcc . the sysdiv field determines the system frequency for the microcontroller . 4. w ait for the pll to lock by polling the plllris bit in the raw interrupt status (ris ) register . 5. enable use of the pll by clearing the bypass bit in rcc / rcc2 . 6.3 register map t able 6-1 on page 66 lists the system control registers, grouped by function. the of fset listed is a hexadecimal increment to the register s address, relative to the system control base address of 0x400f .e000. note: spaces in the system control register space that are not used are reserved for future or internal use by luminary micro, inc. software should not modify any reserved memory address. t able 6-1. system control register map see page description reset t ype name offset 68 device identification 0 - ro did0 0x000 84 device identification 1 - ro did1 0x004 86 device capabilities 0 0x00ff .007f ro dc0 0x008 87 device capabilities 1 0x01 1 1.32ff ro dc1 0x010 89 device capabilities 2 0x010f .1313 ro dc2 0x014 91 device capabilities 3 0x030f .81ff ro dc3 0x018 93 device capabilities 4 0x5100.007f ro dc4 0x01c 70 brown-out reset control 0x0000.7ffd r/w pborctl 0x030 71 ldo power control 0x0000.0000 r/w ldopctl 0x034 116 software reset control 0 0x00000000 r/w srcr0 0x040 september 02, 2007 66 preliminary system control see page description reset t ype name offset 117 software reset control 1 0x00000000 r/w srcr1 0x044 119 software reset control 2 0x00000000 r/w srcr2 0x048 72 raw interrupt status 0x0000.0000 ro ris 0x050 73 interrupt mask control 0x0000.0000 r/w imc 0x054 74 masked interrupt status and clear 0x0000.0000 r/w1c misc 0x058 75 reset cause - r/w resc 0x05c 76 run-mode clock configuration 0x07ae.3ad1 r/w rcc 0x060 80 xt al to pll t ranslation - ro pllcfg 0x064 81 run-mode clock configuration 2 0x0780.2800 r/w rcc2 0x070 95 run mode clock gating control register 0 0x00000040 r/w rcgc0 0x100 101 run mode clock gating control register 1 0x00000000 r/w rcgc1 0x104 110 run mode clock gating control register 2 0x00000000 r/w rcgc2 0x108 97 sleep mode clock gating control register 0 0x00000040 r/w scgc0 0x1 10 104 sleep mode clock gating control register 1 0x00000000 r/w scgc1 0x1 14 112 sleep mode clock gating control register 2 0x00000000 r/w scgc2 0x1 18 99 deep sleep mode clock gating control register 0 0x00000040 r/w dcgc0 0x120 107 deep sleep mode clock gating control register 1 0x00000000 r/w dcgc1 0x124 114 deep sleep mode clock gating control register 2 0x00000000 r/w dcgc2 0x128 83 deep sleep clock configuration 0x0780.0000 r/w dslpclkcfg 0x144 6.4 register descriptions all addresses given are relative to the system control base address of 0x400f .e000. 67 september 02, 2007 preliminary lm3s8962 microcontroller register 1: device identification 0 (did0), offset 0x000 this register identifies the version of the device. device identification 0 (did0) base 0x400f .e000 of fset 0x000 t ype ro, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 class reserved ver reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 minor major ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype - - - - - - - - - - - - - - - - reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31 did0 v ersion this field defines the did0 register format version. the version number is numeric. the value of the ver field is encoded as follows: description v alue first revision of the did0 register format, for stellaris? fury-class devices. 0x1 0x1 ro ver 30:28 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 27:24 device class the class field value identifies the internal design from which all mask sets are generated for all devices in a particular product line. the class field value is changed for new product lines, for changes in fab process (for example, a remap or shrink), or any case where the major or minor fields require dif ferentiation from prior devices. the value of the class field is encoded as follows (all other encodings are reserved): description v alue stellaris? sandstorm-class devices. 0x0 stellaris? fury-class devices. 0x1 0x1 ro class 23:16 september 02, 2007 68 preliminary system control description reset t ype name bit/field major revision this field specifies the major revision number of the device. the major revision reflects changes to base layers of the design. the major revision number is indicated in the part number as a letter (a for first revision, b for second, and so on). this field is encoded as follows: description v alue revision a (initial device) 0x0 revision b (first base layer revision) 0x1 revision c (second base layer revision) 0x2 and so on. - ro major 15:8 minor revision this field specifies the minor revision number of the device. the minor revision reflects changes to the metal layers of the design. the minor field value is reset when the major field is changed. this field is numeric and is encoded as follows: description v alue initial device, or a major revision update. 0x0 first metal layer change. 0x1 second metal layer change. 0x2 and so on. - ro minor 7:0 69 september 02, 2007 preliminary lm3s8962 microcontroller register 2: brown-out reset control (pborctl), offset 0x030 this register is responsible for controlling reset conditions after initial power-on reset. brown-out reset control (pborctl) base 0x400f .e000 of fset 0x030 t ype r/w , reset 0x0000.7ffd 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved borior reserved ro r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:2 bor interrupt or reset this bit controls how a bor event is signaled to the controller . if set, a reset is signaled. otherwise, an interrupt is signaled. 0 r/w borior 1 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 september 02, 2007 70 preliminary system control register 3: ldo power control (ldopctl), offset 0x034 the vadj field in this register adjusts the on-chip output voltage (v out ). ldo power control (ldopctl) base 0x400f .e000 of fset 0x034 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 v adj reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:6 ldo output v oltage this field sets the on-chip output voltage. the programming values for the vadj field are provided below . v out (v) v alue 2.50 0x00 2.45 0x01 2.40 0x02 2.35 0x03 2.30 0x04 2.25 0x05 reserved 0x06-0x3f 2.75 0x1b 2.70 0x1c 2.65 0x1d 2.60 0x1e 2.55 0x1f 0x0 r/w v adj 5:0 71 september 02, 2007 preliminary lm3s8962 microcontroller register 4: raw interrupt status (ris), offset 0x050 central location for system control raw interrupts. these are set and cleared by hardware. raw interrupt status (ris) base 0x400f .e000 of fset 0x050 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved borris reserved plllris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:7 pll lock raw interrupt status this bit is set when the pll t ready t imer asserts. 0 ro plllris 6 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 5:2 brown-out reset raw interrupt status this bit is the raw interrupt status for any brown-out conditions. if set, a brown-out condition is currently active. this is an unregistered signal from the brown-out detection circuit. an interrupt is reported if the borim bit in the imc register is set and the borior bit in the pborctl register is cleared. 0 ro borris 1 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 september 02, 2007 72 preliminary system control register 5: interrupt mask control (imc), offset 0x054 central location for system control interrupt masks. interrupt mask control (imc) base 0x400f .e000 of fset 0x054 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved borim reserved plllim reserved ro r/w ro ro ro ro r/w ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:7 pll lock interrupt mask this bit specifies whether a current limit detection is promoted to a controller interrupt. if set, an interrupt is generated if plllris in ris is set; otherwise, an interrupt is not generated. 0 r/w plllim 6 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 5:2 brown-out reset interrupt mask this bit specifies whether a brown-out condition is promoted to a controller interrupt. if set, an interrupt is generated if borris is set; otherwise, an interrupt is not generated. 0 r/w borim 1 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 73 september 02, 2007 preliminary lm3s8962 microcontroller register 6: masked interrupt status and clear (misc), offset 0x058 central location for system control result of ris and imc to generate an interrupt to the controller . all of the bits are r/w1c and this action also clears the corresponding raw interrupt bit in the ris register (see page 72 ). shrm says: it is more than the contents of the ris register anded with the the contents of the imc register . this register latches a positive and result and holds it until cleared by software. a straight combinatoric and is insuf ficient. cr: what do we want to say in para? masked interrupt status and clear (misc) base 0x400f .e000 of fset 0x058 t ype r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved bormis reserved plllmis reserved ro r/w1c ro ro ro ro r/w1c ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:7 pll lock masked interrupt status this bit is set when the pll t ready timer asserts. the interrupt is cleared by writing a 1 to this bit. 0 r/w1c plllmis 6 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 5:2 bor masked interrupt status the bormis is simply the borris anded with the mask value, borim . 0 r/w1c bormis 1 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 september 02, 2007 74 preliminary system control register 7: reset cause (resc), offset 0x05c this register is set with the reset cause after reset. the bits in this register are sticky and maintain their state across multiple reset sequences, except when an external reset is the cause, and then all the other bits in the resc register are cleared. reset cause (resc) base 0x400f .e000 of fset 0x05c t ype r/w , reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ext por bor wdt sw ldo reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro t ype - - - - - - 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:6 ldo reset when set, indicates the ldo circuit has lost regulation and has generated a reset event. - r/w ldo 5 software reset when set, indicates a software reset is the cause of the reset event. - r/w sw 4 w atchdog t imer reset when set, indicates a watchdog reset is the cause of the reset event. - r/w wdt 3 brown-out reset when set, indicates a brown-out reset is the cause of the reset event. - r/w bor 2 power-on reset when set, indicates a power-on reset is the cause of the reset event. - r/w por 1 external reset when set, indicates an external reset ( rst assertion) is the cause of the reset event. - r/w ext 0 75 september 02, 2007 preliminary lm3s8962 microcontroller register 8: run-mode clock configuration (rcc), offset 0x060 this register is defined to provide source control and frequency speed. run-mode clock configuration (rcc) base 0x400f .e000 of fset 0x060 t ype r/w , reset 0x07ae.3ad1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved pwmdiv usepwmdiv reserved usesysdiv sysdiv acg reserved ro r/w r/w r/w r/w ro r/w r/w r/w r/w r/w r/w ro ro ro ro t ype 0 1 1 1 0 0 0 1 1 1 1 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 moscdis ioscdis reserved oscsrc xt al reserved byp ass reserved pwrdn reserved r/w r/w ro ro r/w r/w r/w r/w r/w r/w ro r/w ro r/w ro ro t ype 1 0 0 0 1 0 1 1 0 1 0 1 1 1 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:28 auto clock gating this bit specifies whether the system uses the sleep-mode clock gating control (scgcn) registers and deep-sleep-mode clock gating control (dcgcn) registers if the controller enters a sleep or deep-sleep mode (respectively). if set, the scgcn or dcgcn registers are used to control the clocks distributed to the peripherals when the controller is in a sleep mode. otherwise, the run-mode clock gating control (rcgcn) registers are used when the controller enters a sleep mode. the rcgcn registers are always used to control the clocks in run mode. this allows peripherals to consume less power when the controller is in a sleep mode and the peripheral is unused. 0 r/w acg 27 september 02, 2007 76 preliminary system control description reset t ype name bit/field system clock divisor specifies which divisor is used to generate the system clock from the pll output. the pll vco frequency is 400 mhz. frequency (byp ass=0) divisor (byp ass=1) v alue reserved reserved 0x0 reserved /2 0x1 reserved /3 0x2 50 mhz /4 0x3 40 mhz /5 0x4 33.33 mhz /6 0x5 28.57 mhz /7 0x6 25 mhz /8 0x7 22.22 mhz /9 0x8 20 mhz /10 0x9 18.18 mhz /1 1 0xa 16.67 mhz /12 0xb 15.38 mhz /13 0xc 14.29 mhz /14 0xd 13.33 mhz /15 0xe 12.5 mhz (default) /16 0xf when reading the run-mode clock configuration (rcc) register (see page 76 ), the sysdiv value is minsysdiv if a lower divider was requested and the pll is being used. this lower value is allowed to divide a non-pll source. 0xf r/w sysdiv 26:23 enable system clock divider use the system clock divider as the source for the system clock. the system clock divider is forced to be used when the pll is selected as the source. 0 r/w usesysdiv 22 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 21 enable pwm clock divisor use the pwm clock divider as the source for the pwm clock. 0 r/w usepwmdiv 20 77 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field pwm unit clock divisor this field specifies the binary divisor used to predivide the system clock down for use as the timing reference for the pwm module. this clock is only power 2 divide and rising edge is synchronous without phase shift from the system clock. divisor v alue /2 0x0 /4 0x1 /8 0x2 /16 0x3 /32 0x4 /64 0x5 /64 0x6 /64 (default) 0x7 0x7 r/w pwmdiv 19:17 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 16:14 pll power down this bit connects to the pll pwrdn input. the reset value of 1 powers down the pll. 1 r/w pwrdn 13 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 1 ro reserved 12 pll bypass chooses whether the system clock is derived from the pll output or the osc source. if set, the clock that drives the system is the osc source. otherwise, the clock that drives the system is the pll output clock divided by the system divider . note: the adc must be clocked from the pll or directly from a 14-mhz to 18-mhz clock source to operate properly . while the adc works in a 14-18 mhz range, to maintain a 1 m sample/second rate, the adc must be provided a 16-mhz clock source. 1 r/w byp ass 1 1 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 10 september 02, 2007 78 preliminary system control description reset t ype name bit/field crystal v alue this field specifies the crystal value attached to the main oscillator . the encoding for this field is provided below . crystal frequency (mhz) using the pll crystal frequency (mhz) not using the pll v alue reserved 1.000 0x0 reserved 1.8432 0x1 reserved 2.000 0x2 reserved 2.4576 0x3 3.579545 mhz 0x4 3.6864 mhz 0x5 4 mhz 0x6 4.096 mhz 0x7 4.9152 mhz 0x8 5 mhz 0x9 5.12 mhz 0xa 6 mhz (reset value) 0xb 6.144 mhz 0xc 7.3728 mhz 0xd 8 mhz 0xe 8.192 mhz 0xf 0xb r/w xt al 9:6 oscillator source picks among the four input sources for the osc. the values are: input source v alue main oscillator (default) 0x0 internal oscillator (default) 0x1 internal oscillator / 4 (this is necessary if used as input to pll) 0x2 reserved 0x3 0x1 r/w oscsrc 5:4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:2 internal oscillator disable 0: internal oscillator (iosc) is enabled. 1: internal oscillator is disabled. 0 r/w ioscdis 1 main oscillator disable 0: main oscillator is enabled. 1: main oscillator is disabled (default). 1 r/w moscdis 0 79 september 02, 2007 preliminary lm3s8962 microcontroller register 9: xt al to pll t ranslation (pllcfg), offset 0x064 this register provides a means of translating external crystal frequencies into the appropriate pll settings. this register is initialized during the reset sequence and updated anytime that the xtal field changes in the run-mode clock configuration (rcc) register (see page 76 ). the pll frequency is calculated using the pllcfg field values, as follows: pllfreq = oscfreq * f / (r + 1) xt al to pll t ranslation (pllcfg) base 0x400f .e000 of fset 0x064 t ype ro, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 r f od ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype - - - - - - - - - - - - - - - - reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:16 pll od v alue this field specifies the value supplied to the pll s od input. description v alue divide by 1 0x0 divide by 2 0x1 divide by 4 0x2 reserved 0x3 - ro od 15:14 pll f v alue this field specifies the value supplied to the pll s f input. - ro f 13:5 pll r v alue this field specifies the value supplied to the pll s r input. - ro r 4:0 september 02, 2007 80 preliminary system control register 10: run-mode clock configuration 2 (rcc2), offset 0x070 this register overrides the rcc equivalent register fields when the usercc2 bit is set. this allows rcc2 to be used to extend the capabilities, while also providing a means to be backward-compatible to previous parts. the fields within the rcc2 register occupy the same bit positions as they do within the rcc register as lsb-justified. the sysdiv2 field is wider so that additional larger divisors are possible. this allows a lower system clock frequency for improved deep sleep power consumption. run-mode clock configuration 2 (rcc2) base 0x400f .e000 of fset 0x070 t ype r/w , reset 0x0780.2800 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved sysdiv2 reserved usercc2 ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w ro ro r/w t ype 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved oscsrc2 reserved byp ass2 reserved pwrdn2 reserved ro ro ro ro r/w r/w r/w ro ro ro ro r/w ro r/w ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 reset description reset t ype name bit/field use rcc2 when set, overrides the rcc register fields. 0 r/w usercc2 31 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 30:29 system clock divisor specifies which divisor is used to generate the system clock from the pll output. the pll vco frequency is 400 mhz. this field is wider than the rcc register sysdiv field in order to provide additional divisor values. this permits the system clock to be run at much lower frequencies during deep sleep mode. for example, where the rcc register sysdiv encoding of 1 1 1 provides /16, the rcc2 register sysdiv2 encoding of 1 1 1 1 1 1 provides /64. 0x0f r/w sysdiv2 28:23 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 22:14 power-down pll when set, powers down the pll. 1 r/w pwrdn2 13 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12 bypass pll when set, bypasses the pll for the clock source. 1 r/w byp ass2 1 1 81 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 10:7 system clock source description v alue main oscillator (mosc) 0x0 internal oscillator (iosc) 0x1 internal oscillator / 4 0x2 30 khz internal oscillator 0x3 32 khz external oscillator 0x7 0x0 r/w oscsrc2 6:4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3:0 september 02, 2007 82 preliminary system control register 1 1: deep sleep clock configuration (dslpclkcfg), offset 0x144 this register provides configuration information for the hardware control of deep sleep mode. deep sleep clock configuration (dslpclkcfg) base 0x400f .e000 of fset 0x144 t ype r/w , reset 0x0780.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved dsdivoride reserved ro ro ro ro ro ro ro r/w r/w r/w r/w r/w r/w ro ro ro t ype 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved dsoscsrc reserved ro ro ro ro r/w r/w r/w ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:29 divider field override 6-bit system divider field to override when deep-sleep occurs with pll running. 0x0f r/w dsdivoride 28:23 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 22:7 clock source when set, forces iosc to be clock source during deep sleep mode. description name v alue no override to the oscillator clock source is done nooride 0x0 use internal 12 mhz oscillator as source iosc 0x1 use 30 khz internal oscillator 30khz 0x3 use 32 khz external oscillator 32khz 0x7 0x0 r/w dsoscsrc 6:4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:0 83 september 02, 2007 preliminary lm3s8962 microcontroller register 12: device identification 1 (did1), offset 0x004 this register identifies the device family , part number , temperature range, pin count, and package type. device identification 1 (did1) base 0x400f .e000 of fset 0x004 t ype ro, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 p ar tno f am ver ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 1 1 0 0 1 0 1 0 0 0 0 1 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 qual rohs pkg temp reserved pincount ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype - - 1 1 0 1 0 0 0 0 0 0 0 0 1 0 reset description reset t ype name bit/field did1 v ersion this field defines the did1 register format version. the version number is numeric. the value of the ver field is encoded as follows (all other encodings are reserved): description v alue first revision of the did1 register format, indicating a stellaris fury-class device. 0x1 0x1 ro ver 31:28 family this field provides the family identification of the device within the luminary micro product portfolio. the value is encoded as follows (all other encodings are reserved): description v alue stellaris family of microcontollers, that is, all devices with external part numbers starting with lm3s. 0x0 0x0 ro f am 27:24 part number this field provides the part number of the device within the family . the value is encoded as follows (all other encodings are reserved): description v alue lm3s8962 0xa6 0xa6 ro p ar tno 23:16 package pin count this field specifies the number of pins on the device package. the value is encoded as follows (all other encodings are reserved): description v alue 100-pin package 0x2 0x2 ro pincount 15:13 september 02, 2007 84 preliminary system control description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12:8 t emperature range this field specifies the temperature rating of the device. the value is encoded as follows (all other encodings are reserved): description v alue industrial temperature range (-40c to 85c) 0x1 0x1 ro temp 7:5 package t ype this field specifies the package type. the value is encoded as follows (all other encodings are reserved): description v alue lqfp package 0x1 0x1 ro pkg 4:3 rohs-compliance this bit specifies whether the device is rohs-compliant. a 1 indicates the part is rohs-compliant. 1 ro rohs 2 qualification status this field specifies the qualification status of the device. the value is encoded as follows (all other encodings are reserved): description v alue engineering sample (unqualified) 0x0 pilot production (unqualified) 0x1 fully qualified 0x2 - ro qual 1:0 85 september 02, 2007 preliminary lm3s8962 microcontroller register 13: device capabilities 0 (dc0), offset 0x008 this register is predefined by the part and can be used to verify features. device capabilities 0 (dc0) base 0x400f .e000 of fset 0x008 t ype ro, reset 0x00ff .007f 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 sramsz ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 flashsz ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field sram size indicates the size of the on-chip sram memory . description v alue 64 kb of sram 0x00ff 0x00ff ro sramsz 31:16 flash size indicates the size of the on-chip flash memory . description v alue 256 kb of flash 0x007f 0x007f ro flashsz 15:0 september 02, 2007 86 preliminary system control register 14: device capabilities 1 (dc1), offset 0x010 this register provides a list of features available in the system. the stellaris family uses this register format to indicate the availability of the following family features in the specific device: cans, pwm, adc, w atchdog timer , hibernation module, and debug capabilities. this register also indicates the maximum clock frequency and maximum adc sample rate. the format of this register is consistent with the rcgc0 , scgc0 , and dcgc0 clock control registers and the srcr0 software reset control register . device capabilities 1 (dc1) base 0x400f .e000 of fset 0x010 t ype ro, reset 0x01 1 1.32ff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc reserved pwm reserved can0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 jt ag swd swo wdt pll tempsns hib mpu maxadcspd minsysdiv ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 1 1 1 0 1 0 0 1 1 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:25 can module 0 present when set, indicates that can unit 0 is present. 1 ro can0 24 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:21 pwm module present when set, indicates that the pwm module is present. 1 ro pwm 20 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 19:17 adc module present when set, indicates that the adc module is present. 1 ro adc 16 system clock divider minimum 4-bit divider value for system clock. the reset value is hardware-dependent. see the rcc register for how to change the system clock divisor using the sysdiv bit. description v alue specifies a 50-mhz cpu clock with a pll divider of 4. 0x3 0x3 ro minsysdiv 15:12 87 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field max adc speed indicates the maximum rate at which the adc samples data. description v alue 500k samples/second 0x2 0x2 ro maxadcspd 1 1:8 mpu present when set, indicates that the cortex-m3 memory protection unit (mpu) module is present. see the arm cortex-m3 t echnical reference manual for details on the mpu. 1 ro mpu 7 hibernation module present when set, indicates that the hibernation module is present. 1 ro hib 6 t emp sensor present when set, indicates that the on-chip temperature sensor is present. 1 ro tempsns 5 pll present when set, indicates that the on-chip phase locked loop (pll) is present. 1 ro pll 4 w atchdog t imer present when set, indicates that a watchdog timer is present. 1 ro wdt 3 swo t race port present when set, indicates that the serial wire output (swo) trace port is present. 1 ro swo 2 swd present when set, indicates that the serial wire debugger (swd) is present. 1 ro swd 1 jt ag present when set, indicates that the jt ag debugger interface is present. 1 ro jt ag 0 september 02, 2007 88 preliminary system control register 15: device capabilities 2 (dc2), offset 0x014 this register provides a list of features available in the system. the stellaris family uses this register format to indicate the availability of the following family features in the specific device: analog comparators, general-purpose t imers, i2cs, qeis, ssis, and uar t s. the format of this register is consistent with the rcgc1 , scgc1 , and dcgc1 clock control registers and the srcr1 software reset control register . device capabilities 2 (dc2) base 0x400f .e000 of fset 0x014 t ype ro, reset 0x010f .1313 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 timer0 timer1 timer2 timer3 reserved comp0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 0 0 0 0 1 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 uar t0 uar t1 reserved ssi0 reserved qei0 qei1 reserved i2c0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 0 0 1 0 0 0 1 1 0 0 1 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:25 analog comparator 0 present when set, indicates that analog comparator 0 is present. 1 ro comp0 24 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:20 t imer 3 present when set, indicates that general-purpose t imer module 3 is present. 1 ro timer3 19 t imer 2 present when set, indicates that general-purpose t imer module 2 is present. 1 ro timer2 18 t imer 1 present when set, indicates that general-purpose t imer module 1 is present. 1 ro timer1 17 t imer 0 present when set, indicates that general-purpose t imer module 0 is present. 1 ro timer0 16 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:13 i2c module 0 present when set, indicates that i2c module 0 is present. 1 ro i2c0 12 89 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 1 1:10 qei1 present when set, indicates that qei module 1 is present. 1 ro qei1 9 qei0 present when set, indicates that qei module 0 is present. 1 ro qei0 8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:5 ssi0 present when set, indicates that ssi module 0 is present. 1 ro ssi0 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3:2 uar t1 present when set, indicates that uar t module 1 is present. 1 ro uar t1 1 uar t0 present when set, indicates that uar t module 0 is present. 1 ro uar t0 0 september 02, 2007 90 preliminary system control register 16: device capabilities 3 (dc3), offset 0x018 this register provides a list of features available in the system. the stellaris family uses this register format to indicate the availability of the following family features in the specific device: analog comparator i/os, ccp i/os, adc i/os, and pwm i/os. device capabilities 3 (dc3) base 0x400f .e000 of fset 0x018 t ype ro, reset 0x030f .81ff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc0 adc1 adc2 adc3 reserved ccp0 ccp1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 0 0 0 0 1 1 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 c0minus c0plus c0o reserved pwmf aul t ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:26 ccp1 pin present when set, indicates that capture/compare/pwm pin 1 is present. 1 ro ccp1 25 ccp0 pin present when set, indicates that capture/compare/pwm pin 0 is present. 1 ro ccp0 24 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:20 adc3 pin present when set, indicates that adc pin 3 is present. 1 ro adc3 19 adc2 pin present when set, indicates that adc pin 2 is present. 1 ro adc2 18 adc1 pin present when set, indicates that adc pin 1 is present. 1 ro adc1 17 adc0 pin present when set, indicates that adc pin 0 is present. 1 ro adc0 16 pwm fault pin present when set, indicates that the pwm fault pin is present. 1 ro pwmf aul t 15 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 14:9 91 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field c0o pin present when set, indicates that the analog comparator 0 output pin is present. 1 ro c0o 8 c0+ pin present when set, indicates that the analog comparator 0 (+) input pin is present. 1 ro c0plus 7 c0- pin present when set, indicates that the analog comparator 0 (-) input pin is present. 1 ro c0minus 6 pwm5 pin present when set, indicates that the pwm pin 5 is present. 1 ro pwm5 5 pwm4 pin present when set, indicates that the pwm pin 4 is present. 1 ro pwm4 4 pwm3 pin present when set, indicates that the pwm pin 3 is present. 1 ro pwm3 3 pwm2 pin present when set, indicates that the pwm pin 2 is present. 1 ro pwm2 2 pwm1 pin present when set, indicates that the pwm pin 1 is present. 1 ro pwm1 1 pwm0 pin present when set, indicates that the pwm pin 0 is present. 1 ro pwm0 0 september 02, 2007 92 preliminary system control register 17: device capabilities 4 (dc4), offset 0x01c this register provides a list of features available in the system. the stellaris family uses this register format to indicate the availability of the following family features in the specific device: ethernet mac and phy , gpios, and ccp i/os. the format of this register is consistent with the rcgc2 , scgc2 , and dcgc2 clock control registers and the srcr2 software reset control register . device capabilities 4 (dc4) base 0x400f .e000 of fset 0x01c t ype ro, reset 0x5100.007f 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved e1588 reserved emac0 reserved ephy0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 gpioa gpiob gpioc gpiod gpioe gpiof gpiog reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31 ethernet phy0 present when set, indicates that ethernet phy module 0 is present. 1 ro ephy0 30 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 29 ethernet mac0 present when set, indicates that ethernet mac module 0 is present. 1 ro emac0 28 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:25 1588 capable when set, indicates that that emac0 is 1588-capable. 1 ro e1588 24 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:7 gpio port g present when set, indicates that gpio port g is present. 1 ro gpiog 6 gpio port f present when set, indicates that gpio port f is present. 1 ro gpiof 5 gpio port e present when set, indicates that gpio port e is present. 1 ro gpioe 4 93 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field gpio port d present when set, indicates that gpio port d is present. 1 ro gpiod 3 gpio port c present when set, indicates that gpio port c is present. 1 ro gpioc 2 gpio port b present when set, indicates that gpio port b is present. 1 ro gpiob 1 gpio port a present when set, indicates that gpio port a is present. 1 ro gpioa 0 september 02, 2007 94 preliminary system control register 18: run mode clock gating control register 0 (rcgc0), offset 0x100 this register controls the clock gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). if the unit is unclocked, reads or writes to the unit will generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc0 is the clock configuration register for running operation, scgc0 for sleep operation, and dcgc0 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. run mode clock gating control register 0 (rcgc0) base 0x400f .e000 of fset 0x100 t ype r/w , reset 0x00000040 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc reserved pwm reserved can0 reserved r/w ro ro ro r/w ro ro ro r/w ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved wdt reserved hib reserved maxadcspd reserved ro ro ro r/w ro ro r/w ro r/w r/w r/w r/w ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:25 can0 clock gating control this bit controls the clock gating for can unit 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. 0 r/w can0 24 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:21 pwm clock gating control this bit controls the clock gating for the pwm module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, a read or write to the unit generates a bus fault. 0 r/w pwm 20 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 19:17 adc0 clock gating control this bit controls the clock gating for sar adc module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, a read or write to the unit generates a bus fault. 0 r/w adc 16 95 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:12 adc sample speed this field sets the rate at which the adc samples data. y ou cannot set the rate higher than the maximum rate. y ou can set the sample rate by setting the maxadcspd bit as follows: description v alue 500k samples/second 0x2 250k samples/second 0x1 125k samples/second 0x0 0 r/w maxadcspd 1 1:8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 hib clock gating control this bit controls the clock gating for the hibernation module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. 0 r/w hib 6 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 5:4 wdt clock gating control this bit controls the clock gating for the wdt module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, a read or write to the unit generates a bus fault. 0 r/w wdt 3 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2:0 september 02, 2007 96 preliminary system control register 19: sleep mode clock gating control register 0 (scgc0), offset 0x1 10 this register controls the clock gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). if the unit is unclocked, reads or writes to the unit will generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc0 is the clock configuration register for running operation, scgc0 for sleep operation, and dcgc0 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. sleep mode clock gating control register 0 (scgc0) base 0x400f .e000 of fset 0x1 10 t ype r/w , reset 0x00000040 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc reserved pwm reserved can0 reserved r/w ro ro ro r/w ro ro ro r/w ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved wdt reserved hib reserved maxadcspd reserved ro ro ro r/w ro ro r/w ro r/w r/w r/w r/w ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:25 can0 clock gating control this bit controls the clock gating for can unit 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. 0 r/w can0 24 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:21 pwm clock gating control this bit controls the clock gating for the pwm module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, a read or write to the unit generates a bus fault. 0 r/w pwm 20 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 19:17 adc0 clock gating control this bit controls the clock gating for sar adc module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, a read or write to the unit generates a bus fault. 0 r/w adc 16 97 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:12 adc sample speed this field sets the rate at which the adc samples data. y ou cannot set the rate higher than the maximum rate. y ou can set the sample rate by setting the maxadcspd bit as follows: description v alue 500k samples/second 0x2 250k samples/second 0x1 125k samples/second 0x0 0 r/w maxadcspd 1 1:8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 hib clock gating control this bit controls the clock gating for the hibernation module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. 0 r/w hib 6 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 5:4 wdt clock gating control this bit controls the clock gating for the wdt module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, a read or write to the unit generates a bus fault. 0 r/w wdt 3 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2:0 september 02, 2007 98 preliminary system control register 20: deep sleep mode clock gating control register 0 (dcgc0), offset 0x120 this register controls the clock gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). if the unit is unclocked, reads or writes to the unit will generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc0 is the clock configuration register for running operation, scgc0 for sleep operation, and dcgc0 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. deep sleep mode clock gating control register 0 (dcgc0) base 0x400f .e000 of fset 0x120 t ype r/w , reset 0x00000040 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc reserved pwm reserved can0 reserved r/w ro ro ro r/w ro ro ro r/w ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved wdt reserved hib reserved maxadcspd reserved ro ro ro r/w ro ro r/w ro r/w r/w r/w r/w ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:25 can0 clock gating control this bit controls the clock gating for can unit 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. 0 r/w can0 24 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:21 pwm clock gating control this bit controls the clock gating for the pwm module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, a read or write to the unit generates a bus fault. 0 r/w pwm 20 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 19:17 adc0 clock gating control this bit controls the clock gating for sar adc module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, a read or write to the unit generates a bus fault. 0 r/w adc 16 99 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:12 adc sample speed this field sets the rate at which the adc samples data. y ou cannot set the rate higher than the maximum rate. y ou can set the sample rate by setting the maxadcspd bit as follows: description v alue 500k samples/second 0x2 250k samples/second 0x1 125k samples/second 0x0 0 r/w maxadcspd 1 1:8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 hib clock gating control this bit controls the clock gating for the hibernation module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. 0 r/w hib 6 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 5:4 wdt clock gating control this bit controls the clock gating for the wdt module. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, a read or write to the unit generates a bus fault. 0 r/w wdt 3 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2:0 september 02, 2007 100 preliminary system control register 21: run mode clock gating control register 1 (rcgc1), offset 0x104 this register controls the clock gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). if the unit is unclocked, reads or writes to the unit will generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc1 is the clock configuration register for running operation, scgc1 for sleep operation, and dcgc1 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. run mode clock gating control register 1 (rcgc1) base 0x400f .e000 of fset 0x104 t ype r/w , reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 timer0 timer1 timer2 timer3 reserved comp0 reserved r/w r/w r/w r/w ro ro ro ro r/w ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 uar t0 uar t1 reserved ssi0 reserved qei0 qei1 reserved i2c0 reserved r/w r/w ro ro r/w ro ro ro r/w r/w ro ro r/w ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:25 analog comparator 0 clock gating this bit controls the clock gating for analog comparator 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w comp0 24 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:20 t imer 3 clock gating control this bit controls the clock gating for general-purpose t imer module 3. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w timer3 19 t imer 2 clock gating control this bit controls the clock gating for general-purpose t imer module 2. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w timer2 18 101 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field t imer 1 clock gating control this bit controls the clock gating for general-purpose t imer module 1. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w timer1 17 t imer 0 clock gating control this bit controls the clock gating for general-purpose t imer module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w timer0 16 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:13 i2c0 clock gating control this bit controls the clock gating for i2c module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w i2c0 12 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 1 1:10 qei1 clock gating control this bit controls the clock gating for qei module 1. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w qei1 9 qei0 clock gating control this bit controls the clock gating for qei module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w qei0 8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:5 ssi0 clock gating control this bit controls the clock gating for ssi module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w ssi0 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3:2 uar t1 clock gating control this bit controls the clock gating for uar t module 1. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w uar t1 1 september 02, 2007 102 preliminary system control description reset t ype name bit/field uar t0 clock gating control this bit controls the clock gating for uar t module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w uar t0 0 103 september 02, 2007 preliminary lm3s8962 microcontroller register 22: sleep mode clock gating control register 1 (scgc1), offset 0x1 14 this register controls the clock gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). if the unit is unclocked, reads or writes to the unit will generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc1 is the clock configuration register for running operation, scgc1 for sleep operation, and dcgc1 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. sleep mode clock gating control register 1 (scgc1) base 0x400f .e000 of fset 0x1 14 t ype r/w , reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 timer0 timer1 timer2 timer3 reserved comp0 reserved r/w r/w r/w r/w ro ro ro ro r/w ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 uar t0 uar t1 reserved ssi0 reserved qei0 qei1 reserved i2c0 reserved r/w r/w ro ro r/w ro ro ro r/w r/w ro ro r/w ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:25 analog comparator 0 clock gating this bit controls the clock gating for analog comparator 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w comp0 24 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:20 t imer 3 clock gating control this bit controls the clock gating for general-purpose t imer module 3. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w timer3 19 t imer 2 clock gating control this bit controls the clock gating for general-purpose t imer module 2. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w timer2 18 september 02, 2007 104 preliminary system control description reset t ype name bit/field t imer 1 clock gating control this bit controls the clock gating for general-purpose t imer module 1. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w timer1 17 t imer 0 clock gating control this bit controls the clock gating for general-purpose t imer module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w timer0 16 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:13 i2c0 clock gating control this bit controls the clock gating for i2c module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w i2c0 12 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 1 1:10 qei1 clock gating control this bit controls the clock gating for qei module 1. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w qei1 9 qei0 clock gating control this bit controls the clock gating for qei module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w qei0 8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:5 ssi0 clock gating control this bit controls the clock gating for ssi module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w ssi0 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3:2 uar t1 clock gating control this bit controls the clock gating for uar t module 1. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w uar t1 1 105 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field uar t0 clock gating control this bit controls the clock gating for uar t module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w uar t0 0 september 02, 2007 106 preliminary system control register 23: deep sleep mode clock gating control register 1 (dcgc1), offset 0x124 this register controls the clock gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). if the unit is unclocked, reads or writes to the unit will generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc1 is the clock configuration register for running operation, scgc1 for sleep operation, and dcgc1 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. deep sleep mode clock gating control register 1 (dcgc1) base 0x400f .e000 of fset 0x124 t ype r/w , reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 timer0 timer1 timer2 timer3 reserved comp0 reserved r/w r/w r/w r/w ro ro ro ro r/w ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 uar t0 uar t1 reserved ssi0 reserved qei0 qei1 reserved i2c0 reserved r/w r/w ro ro r/w ro ro ro r/w r/w ro ro r/w ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:25 analog comparator 0 clock gating this bit controls the clock gating for analog comparator 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w comp0 24 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:20 t imer 3 clock gating control this bit controls the clock gating for general-purpose t imer module 3. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w timer3 19 t imer 2 clock gating control this bit controls the clock gating for general-purpose t imer module 2. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w timer2 18 107 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field t imer 1 clock gating control this bit controls the clock gating for general-purpose t imer module 1. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w timer1 17 t imer 0 clock gating control this bit controls the clock gating for general-purpose t imer module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w timer0 16 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:13 i2c0 clock gating control this bit controls the clock gating for i2c module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w i2c0 12 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 1 1:10 qei1 clock gating control this bit controls the clock gating for qei module 1. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w qei1 9 qei0 clock gating control this bit controls the clock gating for qei module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w qei0 8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:5 ssi0 clock gating control this bit controls the clock gating for ssi module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w ssi0 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3:2 uar t1 clock gating control this bit controls the clock gating for uar t module 1. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w uar t1 1 september 02, 2007 108 preliminary system control description reset t ype name bit/field uar t0 clock gating control this bit controls the clock gating for uar t module 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w uar t0 0 109 september 02, 2007 preliminary lm3s8962 microcontroller register 24: run mode clock gating control register 2 (rcgc2), offset 0x108 this register controls the clock gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). if the unit is unclocked, reads or writes to the unit will generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc2 is the clock configuration register for running operation, scgc2 for sleep operation, and dcgc2 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. run mode clock gating control register 2 (rcgc2) base 0x400f .e000 of fset 0x108 t ype r/w , reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved emac0 reserved ephy0 reserved ro ro ro ro ro ro ro ro ro ro ro ro r/w ro r/w ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 gpioa gpiob gpioc gpiod gpioe gpiof gpiog reserved r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31 phy0 clock gating control this bit controls the clock gating for ethernet phy unit 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w ephy0 30 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 29 mac0 clock gating control this bit controls the clock gating for ethernet mac unit 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w emac0 28 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:7 port g clock gating control this bit controls the clock gating for port g. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpiog 6 september 02, 2007 1 10 preliminary system control description reset t ype name bit/field port f clock gating control this bit controls the clock gating for port f . if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpiof 5 port e clock gating control this bit controls the clock gating for port e. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpioe 4 port d clock gating control this bit controls the clock gating for port d. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpiod 3 port c clock gating control this bit controls the clock gating for port c. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpioc 2 port b clock gating control this bit controls the clock gating for port b. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpiob 1 port a clock gating control this bit controls the clock gating for port a. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpioa 0 1 1 1 september 02, 2007 preliminary lm3s8962 microcontroller register 25: sleep mode clock gating control register 2 (scgc2), offset 0x1 18 this register controls the clock gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). if the unit is unclocked, reads or writes to the unit will generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc2 is the clock configuration register for running operation, scgc2 for sleep operation, and dcgc2 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. sleep mode clock gating control register 2 (scgc2) base 0x400f .e000 of fset 0x1 18 t ype r/w , reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved emac0 reserved ephy0 reserved ro ro ro ro ro ro ro ro ro ro ro ro r/w ro r/w ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 gpioa gpiob gpioc gpiod gpioe gpiof gpiog reserved r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31 phy0 clock gating control this bit controls the clock gating for ethernet phy unit 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w ephy0 30 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 29 mac0 clock gating control this bit controls the clock gating for ethernet mac unit 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w emac0 28 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:7 september 02, 2007 1 12 preliminary system control description reset t ype name bit/field port g clock gating control this bit controls the clock gating for port g. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpiog 6 port f clock gating control this bit controls the clock gating for port f . if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpiof 5 port e clock gating control this bit controls the clock gating for port e. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpioe 4 port d clock gating control this bit controls the clock gating for port d. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpiod 3 port c clock gating control this bit controls the clock gating for port c. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpioc 2 port b clock gating control this bit controls the clock gating for port b. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpiob 1 port a clock gating control this bit controls the clock gating for port a. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpioa 0 1 13 september 02, 2007 preliminary lm3s8962 microcontroller register 26: deep sleep mode clock gating control register 2 (dcgc2), offset 0x128 this register controls the clock gating logic. each bit controls a clock enable for a given interface, function, or unit. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled (saving power). if the unit is unclocked, reads or writes to the unit will generate a bus fault. the reset state of these bits is 0 (unclocked) unless otherwise noted, so that all functional units are disabled. it is the responsibility of software to enable the ports necessary for the application. note that these registers may contain more bits than there are interfaces, functions, or units to control. this is to assure reasonable code compatibility with other family and future parts. rcgc2 is the clock configuration register for running operation, scgc2 for sleep operation, and dcgc2 for deep-sleep operation. setting the acg bit in the run-mode clock configuration (rcc) register specifies that the system uses sleep modes. deep sleep mode clock gating control register 2 (dcgc2) base 0x400f .e000 of fset 0x128 t ype r/w , reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved emac0 reserved ephy0 reserved ro ro ro ro ro ro ro ro ro ro ro ro r/w ro r/w ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 gpioa gpiob gpioc gpiod gpioe gpiof gpiog reserved r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31 phy0 clock gating control this bit controls the clock gating for ethernet phy unit 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w ephy0 30 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 29 mac0 clock gating control this bit controls the clock gating for ethernet mac unit 0. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w emac0 28 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:7 september 02, 2007 1 14 preliminary system control description reset t ype name bit/field port g clock gating control this bit controls the clock gating for port g. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpiog 6 port f clock gating control this bit controls the clock gating for port f . if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpiof 5 port e clock gating control this bit controls the clock gating for port e. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpioe 4 port d clock gating control this bit controls the clock gating for port d. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpiod 3 port c clock gating control this bit controls the clock gating for port c. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpioc 2 port b clock gating control this bit controls the clock gating for port b. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpiob 1 port a clock gating control this bit controls the clock gating for port a. if set, the unit receives a clock and functions. otherwise, the unit is unclocked and disabled. if the unit is unclocked, reads or writes to the unit will generate a bus fault. 0 r/w gpioa 0 1 15 september 02, 2007 preliminary lm3s8962 microcontroller register 27: software reset control 0 (srcr0), offset 0x040 w rites to this register are masked by the bits in the device capabilities 1 (dc1) register . software reset control 0 (srcr0) base 0x400f .e000 of fset 0x040 t ype r/w , reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 adc reserved pwm reserved can0 reserved r/w ro ro ro r/w ro ro ro r/w ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved wdt reserved hib reserved ro ro ro r/w ro ro r/w ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:25 can0 reset control reset control for can unit 0. 0 r/w can0 24 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:21 pwm reset control reset control for pwm module. 0 r/w pwm 20 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 19:17 adc0 reset control reset control for sar adc module 0. 0 r/w adc 16 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:7 hib reset control reset control for the hibernation module. 0 r/w hib 6 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 5:4 wdt reset control reset control for w atchdog unit. 0 r/w wdt 3 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2:0 september 02, 2007 1 16 preliminary system control register 28: software reset control 1 (srcr1), offset 0x044 w rites to this register are masked by the bits in the device capabilities 2 (dc2) register . software reset control 1 (srcr1) base 0x400f .e000 of fset 0x044 t ype r/w , reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 timer0 timer1 timer2 timer3 reserved comp0 reserved r/w r/w r/w r/w ro ro ro ro r/w ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 uar t0 uar t1 reserved ssi0 reserved qei0 qei1 reserved i2c0 reserved r/w r/w ro ro r/w ro ro ro r/w r/w ro ro r/w ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:25 analog comp 0 reset control reset control for analog comparator 0. 0 r/w comp0 24 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:20 t imer 3 reset control reset control for general-purpose t imer module 3. 0 r/w timer3 19 t imer 2 reset control reset control for general-purpose t imer module 2. 0 r/w timer2 18 t imer 1 reset control reset control for general-purpose t imer module 1. 0 r/w timer1 17 t imer 0 reset control reset control for general-purpose t imer module 0. 0 r/w timer0 16 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:13 i2c0 reset control reset control for i2c unit 0. 0 r/w i2c0 12 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 1 1:10 qei1 reset control reset control for qei unit 1. 0 r/w qei1 9 1 17 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field qei0 reset control reset control for qei unit 0. 0 r/w qei0 8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:5 ssi0 reset control reset control for ssi unit 0. 0 r/w ssi0 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3:2 uar t1 reset control reset control for uar t unit 1. 0 r/w uar t1 1 uar t0 reset control reset control for uar t unit 0. 0 r/w uar t0 0 september 02, 2007 1 18 preliminary system control register 29: software reset control 2 (srcr2), offset 0x048 w rites to this register are masked by the bits in the device capabilities 4 (dc4) register . software reset control 2 (srcr2) base 0x400f .e000 of fset 0x048 t ype r/w , reset 0x00000000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved emac0 reserved ephy0 reserved ro ro ro ro ro ro ro ro ro ro ro ro r/w ro r/w ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 gpioa gpiob gpioc gpiod gpioe gpiof gpiog reserved r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31 phy0 reset control reset control for ethernet phy unit 0. 0 r/w ephy0 30 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 29 mac0 reset control reset control for ethernet mac unit 0. 0 r/w emac0 28 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:7 port g reset control reset control for gpio port g. 0 r/w gpiog 6 port f reset control reset control for gpio port f . 0 r/w gpiof 5 port e reset control reset control for gpio port e. 0 r/w gpioe 4 port d reset control reset control for gpio port d. 0 r/w gpiod 3 port c reset control reset control for gpio port c. 0 r/w gpioc 2 port b reset control reset control for gpio port b. 0 r/w gpiob 1 1 19 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field port a reset control reset control for gpio port a. 0 r/w gpioa 0 september 02, 2007 120 preliminary system control 7 hibernation module the hibernation module manages removal and restoration of power to the rest of the microcontroller to provide a means for reducing power consumption. when the processor and peripherals are idle, power can be completely removed with only the hibernation module remaining powered. power can be restored based on an external signal, or at a certain time using the built-in real-time clock (r tc). the hibernation module can be independently supplied from a battery or an auxillary power supply . the hibernation module has the following features: power-switching logic to discrete external regulator dedicated pin for waking from an external signal low-battery detection, signalling, and interrupt generation 32-bit real-time counter (r tc) t wo 32-bit r tc match registers for timed wake-up and interrupt generation clock source from a 32.768-khz external oscillator or a 4.194304-mhz crystal r tc predivider trim for making fine adjustments to the clock rate 64 32-bit words of non-volatile memory programmable interrupts for r tc match, external wake, and low battery events 121 september 02, 2007 preliminary lm3s8962 microcontroller 7.1 block diagram figure 7-1. hibernation module block diagram 7.2 functional description the hibernation module controls the power to the processor with an enable signal ( hib ) that signals an external voltage regulator to turn of f. the hibernation module power is determined dynamically . the supply voltage of the hibernation module is the larger of the main voltage source (vdd) or the battery/auxilliary voltage source (vba t). a voting circuit indicates the larger and an internal power switch selects the appropriate voltage source. the hibernation module also has a separate clock source to maintain a real-time clock (r tc). once in hibernation, the module signals an external voltage regulator to turn back on the power when an external pin ( wake ) is asserted, or when the internal r tc reaches a certain value. the hibernation module can also detect when the battery voltage is low , and optionally prevent hibernation when this occurs. power-up from a power cut to code execution is defined as the regulator turn-on time (specifed at t hib_t o_vdd maximum) plus the normal chip por (see hibernation module on page 585 ). 7.2.1 register access t iming because the hibernation module has an independent clocking domain, certain registers must be written only with a timing gap between accesses. the delay time is t hib_reg_write , therefore software must guarantee that a delay of t hib_reg_write is inserted between back-to-back writes to certain hibernation registers, or between a write followed by a read to those same registers. there is no september 02, 2007 122 preliminary hibernation module hibim hibris hibmis hibic hibr tct pre-divider /128 xosc0 xosc1 hibctl.clk32en hibctl.clksel hibr tcc hibr tcld hibr tcm0 hibr tcm1 r tc interrupts power sequence logic ma tch0/1 w ake interrupts to cpu low battery detect lowba t vdd vba t hib hibctl.lowba ten hibctl.pwrcut hibctl.extwen hibctl.r tcwen hibctl.v abor t non-v olatile memory hibda t a restriction on timing for back-to-back reads from the hibernation module. refer to register descriptions on page 127 for details about which registers are subject to this timing restriction. 7.2.2 clock source the hibernation module must be clocked by an external source, even if the r tc feature will not be used. an external oscillator or crystal can be used for this purpose. t o use a crystal, a 4.194304-mhz crystal is connected to the xosc0 and xosc1 pins. this clock signal is divided by 128 internally to produce the 32.768-khz clock reference. t o use a more precise clock source, a 32.768-khz oscillator can be connected to the xosc0 pin. the clock source is enabled by setting the clk32en bit of the hibctl register . the type of clock source is selected by setting the clksel bit to 0 for a 4.194304-mhz clock source, and to 1 for a 32.768-khz clock source. if the bit is set to 0, the input clock is divided by 128, resulting in a 32.768-khz clock source. if a crystal is used for the clock source, the software must leave a delay of t xosc_settle after setting the clk32en bit and before any other accesses to the hibernation module registers. the delay allows the crystal to power up and stabilize. if an oscillator is used for the clock source, no delay is needed. 7.2.3 battery management the hibernation module can be independently powered by a battery or an auxiliary power source. the module can monitor the voltage level of the battery and detect when the voltage becomes too low . when this happens, an interrupt can be generated. the module can also be configured so that it will not go into hibernate mode if the battery voltage is too low . note that the hibernation module draws power from whichever source ( vbat or vdd ) has the higher voltage. therefore, it is important to design the circuit to ensure that vdd is higher that vbat under nominal conditions or else the hibernation module draws power from the battery even when vdd is available. the hibernation module can be configured to detect a low battery condition by setting the lowbaten bit of the hibctl register . in this configuration, the lowbat bit of the hibris register will be set when the battery level is low . if the vabort bit is also set, then the module is prevented from entering hibernation mode when a low battery is detected. the module can also be configured to generate an interrupt for the low-battery condition (see interrupts and status on page 124 ). 7.2.4 real-t ime clock the hibernation module includes a 32-bit counter that increments once per second with a proper clock source and configuration (see clock source on page 123 ). the 32.768-khz clock signal is fed into a predivider register which counts down the 32.768-khz clock ticks to achieve a once per second clock rate for the r tc. the rate can be adjusted to compensate for inaccuracies in the clock source by using the predivider trim register . this register has a nominal value of 0x7fff , and is used for one second out of every 64 seconds to divide the input clock. this allows the software to make fine corrections to the clock rate by adjusting the predivider trim register up or down from 0x7fff . the predivider trim should be adjusted up from 0x7fff in order to slow down the r tc rate, and down from 0x7fff in order to speed up the r tc rate. the hibernation module includes two 32-bit match registers that are compared to the value of the r tc counter . the match registers can be used to wake the processor from hibernation mode, or to generate an interrupt to the processor if it is not in hibernation. the r tc must be enabled with the rtcen bit of the hibctl register . the value of the r tc can be set at any time by writing to the hibrtcld register . the predivider trim can be adjusted by reading and writing the hibrtct register . the predivider uses this register once every 64 seconds to adjust 123 september 02, 2007 preliminary lm3s8962 microcontroller the clock rate. the two match registers can be set by writing to the hibrtcm0 and hibrtcm1 registers. the r tc can be configured to generate interrupts by using the interrupt registers (see interrupts and status on page 124 ). 7.2.5 non-v olatile memory the hibernation module contains 64 32-bit words of memory which are retained during hibernation. this memory is powered from the battery or auxillary power supply during hibernation. the processor software can save state information in this memory prior to hibernation, and can then recover the state upon waking. the non-volatile memory can be accessed through the hibda t a registers. 7.2.6 power control the hibernation module controls power to the processor through the use of the hib pin, which is intended to be connected to the enable signal of the external regulator(s) providing 3.3 v and/or 2.5 v to the microcontroller . when the hib signal is asserted by the hibernation module, the external regulator is turned of f and no longer powers the microcontroller . the hibernation module remains powered from the vbat supply , which could be a battery or an auxillary power source. hibernation mode is initiated by the microcontroller setting the hibreq bit of the hibctl register . prior to doing this, a wake-up condition must be configured, either from the external wake pin, or by using an r tc match. the hibernation module is configured to wake from the external wake pin by setting the pinwen bit of the hibctl register . it is configured to wake from r tc match by setting the rtcwen bit. either one or both of these bits can be set prior to going into hibernation. the wake pin includes a weak internal pull-up. note that both the hib and wake pins use the hibernation module's internal power supply as the logic 1 reference. when the hibernation module wakes, the microcontroller will see a normal power-on reset. it can detect that the power-on was due to a wake from hibernation by examining the raw interrupt status register (see interrupts and status on page 124 ) and by looking for state data in the non-volatile memory (see non-v olatile memory on page 124 ). when the hib signal deasserts, enabling the external regulator , the external regulator must reach the operating voltage within t hib_t o_vdd . 7.2.7 interrupts and status the hibernation module can generate interrupts when the following conditions occur: assertion of wake pin r tc match low battery detected all of the interrupts are ored together before being sent to the interrupt controller , so the hibernate module can only generate a single interrupt request to the controller at any given time. the software interrupt handler can service multiple interrupt events by reading the hibmis register . software can also read the status of the hibernation module at any time by reading the hibris register which shows all of the pending events. this register can be used at power-on to see if a wake condition is pending, which indicates to the software that a hibernation wake occurred. the events that can trigger an interrupt are configured by setting the appropriate bits in the hibim register . pending interrupts can be cleared by writing the corresponding bit in the hibic register . september 02, 2007 124 preliminary hibernation module 7.3 initialization and configuration the hibernation module can be configured in several dif ferent combinations. the following sections show the recommended programming sequence for various scenarios. the examples below assume that a 32.768-khz oscillator is used, and thus always show bit 2 ( clksel ) of the hibctl register set to 1. if a 4.194304-mhz crystal is used instead, then the clksel bit remains cleared. because the hibernation module runs at 32 khz and is asynchronous to the rest of the system, software must allow a delay of t hib_reg_write after writes to certain registers (see register access t iming on page 122 ). the registers that require a delay are denoted with a footnote in t able 7-1 on page 126 . 7.3.1 initialization the clock source must be enabled first, even if the r tc will not be used. if a 4.194304-mhz crystal is used, perform the following steps: 1. w rite 0x40 to the hibctl register at of fset 0x10 to enable the crystal and select the divide-by-128 input path. 2. w ait for a time of t xosc_settle for the crystal to power up and stabilize before performing any other operations with the hibernation module. if a 32.678-khz oscillator is used, then perform the following steps: 1. w rite 0x44 to the hibctl register at of fset 0x10 to enable the oscillator input. 2. no delay is necessary . the above is only necessary when the entire system is initialized for the first time. if the processor is powered due to a wake from hibernation, then the hibernation module has already been powered up and the above steps are not necessary . the software can detect that the hibernation module and clock are already powered by examining the clk32en bit of the hibctl register . 7.3.2 rtc match functionality (no hibernation) the following steps are needed to use the r tc match functionality of the hibernation module: 1. w rite the required r tc match value to one of the hibrtcmn registers at of fset 0x004 or 0x008. 2. w rite the required r tc load value to the hibrtcld register at of fset 0x00c. 3. set the required r tc match interrupt mask in the rtcalt0 and rtcalt1 bits (bits 1:0) in the hibim register at of fset 0x014. 4. w rite 0x0000.0041 to the hibctl register at of fset 0x010 to enable the r tc to begin counting. 7.3.3 rtc match/w ake-up from hibernation the following steps are needed to use the r tc match and wake-up functionality of the hibernation module: 1. w rite the required r tc match value to the hibrtcmn registers at of fset 0x004 or 0x008. 2. w rite the required r tc load value to the hibrtcld register at of fset 0x00c. 3. w rite any data to be retained during power cut to the hibda t a register at of fsets 0x030-0x12c. 125 september 02, 2007 preliminary lm3s8962 microcontroller 4. set the r tc match w ake-up and start the hibernation sequence by writing 0x0000.004f to the hibctl register at of fset 0x010. 7.3.4 external w ake-up from hibernation the following steps are needed to use the hibernation module with the external wake pin as the wake-up source for the microcontroller: 1. w rite any data to be retained during power cut to the hibda t a register at of fsets 0x030-0x12c. 2. enable the external wake and start the hibernation sequence by writing 0x0000.0056 to the hibctl register at of fset 0x010. 7.3.5 rtc/external w ake-up from hibernation 1. w rite the required r tc match value to the hibrtcmn registers at of fset 0x004 or 0x008. 2. w rite the required r tc load value to the hibrtcld register at of fset 0x00c. 3. w rite any data to be retained during power cut to the hibda t a register at of fsets 0x030-0x12c. 4. set the r tc match/external w ake-up and start the hibernation sequence by writing 0x0000.005f to the hibctl register at of fset 0x010. 7.4 register map t able 7-1 on page 126 lists the hibernation registers. all addresses given are relative to the hibernation module base address at 0x400f .c000. note: hibrtcc , hibrtcm0 , hibrtcm1 , hibrtcld , hibrtct , and hibda t a are on the hibernation module clock domain and require a delay of t hib_reg_write between write accesses. see register access t iming on page 122 . t able 7-1. hibernation module register map see page description reset t ype name offset 128 hibernation r tc counter 0x0000.0000 ro hibr tcc 0x000 129 hibernation r tc match 0 0xffff .ffff r/w hibr tcm0 0x004 130 hibernation r tc match 1 0xffff .ffff r/w hibr tcm1 0x008 131 hibernation r tc load 0xffff .ffff r/w hibr tcld 0x00c 132 hibernation control 0x0000.0000 r/w hibctl 0x010 134 hibernation interrupt mask 0x0000.0000 r/w hibim 0x014 135 hibernation raw interrupt status 0x0000.0000 ro hibris 0x018 136 hibernation masked interrupt status 0x0000.0000 ro hibmis 0x01c 137 hibernation interrupt clear 0x0000.0000 r/w1c hibic 0x020 138 hibernation r tc t rim 0x0000.7fff r/w hibr tct 0x024 139 hibernation data 0x0000.0000 r/w hibda t a 0x030- 0x12c september 02, 2007 126 preliminary hibernation module 7.5 register descriptions the remainder of this section lists and describes the hibernation module registers, in numerical order by address of fset. 127 september 02, 2007 preliminary lm3s8962 microcontroller register 1: hibernation rtc counter (hibrtcc), offset 0x000 this register is the current 32-bit value of the r tc counter . hibernation r tc counter (hibr tcc) base 0x400f .c000 of fset 0x000 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tcc ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 r tcc ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field r tc counter a read returns the 32-bit counter value. this register is read-only . t o change the value, use the hibrtcld register . 0x0000.0000 ro r tcc 31:0 september 02, 2007 128 preliminary hibernation module register 2: hibernation rtc match 0 (hibrtcm0), offset 0x004 this register is the 32-bit match 0 register for the r tc counter . hibernation r tc match 0 (hibr tcm0) base 0x400f .c000 of fset 0x004 t ype r/w , reset 0xffff .ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tcm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 r tcm0 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field r tc match 0 a write loads the value into the r tc match register . a read returns the current match value. 0xffff .ffff r/w r tcm0 31:0 129 september 02, 2007 preliminary lm3s8962 microcontroller register 3: hibernation rtc match 1 (hibrtcm1), offset 0x008 this register is the 32-bit match 1 register for the r tc counter . hibernation r tc match 1 (hibr tcm1) base 0x400f .c000 of fset 0x008 t ype r/w , reset 0xffff .ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tcm1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 r tcm1 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field r tc match 1 a write loads the value into the r tc match register . a read returns the current match value. 0xffff .ffff r/w r tcm1 31:0 september 02, 2007 130 preliminary hibernation module register 4: hibernation rtc load (hibrtcld), offset 0x00c this register is the 32-bit value loaded into the r tc counter . hibernation r tc load (hibr tcld) base 0x400f .c000 of fset 0x00c t ype r/w , reset 0xffff .ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r tcld r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 r tcld r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field r tc load a write loads the current value into the r tc counter ( rtcc ). a read returns the 32-bit load value. 0xffff .ffff r/w r tcld 31:0 131 september 02, 2007 preliminary lm3s8962 microcontroller register 5: hibernation control (hibctl), offset 0x010 this register is the control register for the hibernation module. hibernation control (hibctl) base 0x400f .c000 of fset 0x010 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 r tcen hibreq clksel r tcwen pinwen lowba ten clk32en v abor t reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 power cut abort enable 0: power cut occurs during a low-battery alert 1: power cut is aborted 0 r/w v abor t 7 32-khz oscillator enable 0: disabled 1: enabled this bit must be enabled to use the hibernation module. if a crystal is used, then software should wait 20 ms after setting this bit to allow the crystal to power up and stabilize. 0 r/w clk32en 6 low battery monitoring enable 0: disabled 1: enabled when set, low battery voltage detection is enabled. 0 r/w lowba ten 5 external wake pin enable 0: disabled 1: enabled when set, an external event on the wake pin will re-power the device. 0 r/w pinwen 4 r tc w ake-up enable 0: disabled 1: enabled when set, an r tc match event ( rtcm0 or rtcm1 ) will re-power the device based on the r tc counter value matching the corresponding match register 0 or 1. 0 r/w r tcwen 3 september 02, 2007 132 preliminary hibernation module description reset t ype name bit/field hibernation module clock select 0: use divide by 128 output. use this value for a 4-mhz crystal. 1: use raw output. use this value for a 32-khz oscillator . 0 r/w clksel 2 hibernation request 0: disabled 1: hibernation initiated after a wake-up event, this bit is cleared by hardware. 0 r/w hibreq 1 r tc t imer enable 0: disabled 1: enabled 0 r/w r tcen 0 133 september 02, 2007 preliminary lm3s8962 microcontroller register 6: hibernation interrupt mask (hibim), offset 0x014 this register is the interrupt mask register for the hibernation module interrupt sources. hibernation interrupt mask (hibim) base 0x400f .c000 of fset 0x014 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 r tcal t0 r tcal t1 lowba t extw reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000.0000 ro reserved 31:4 external w ake-up interrupt mask 0: masked 1: unmasked 0 r/w extw 3 low battery v oltage interrupt mask 0: masked 1: unmasked 0 r/w lowba t 2 r tc alert1 interrupt mask 0: masked 1: unmasked 0 r/w r tcal t1 1 r tc alert0 interrupt mask 0: masked 1: unmasked 0 r/w r tcal t0 0 september 02, 2007 134 preliminary hibernation module register 7: hibernation raw interrupt status (hibris), offset 0x018 this register is the raw interrupt status for the hibernation module interrupt sources. hibernation raw interrupt status (hibris) base 0x400f .c000 of fset 0x018 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 r tcal t0 r tcal t1 lowba t extw reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000.0000 ro reserved 31:4 external w ake-up raw interrupt status 0 ro extw 3 low battery v oltage raw interrupt status 0 ro lowba t 2 r tc alert1 raw interrupt status 0 ro r tcal t1 1 r tc alert0 raw interrupt status 0 ro r tcal t0 0 135 september 02, 2007 preliminary lm3s8962 microcontroller register 8: hibernation masked interrupt status (hibmis), offset 0x01c this register is the masked interrupt status for the hibernation module interrupt sources. hibernation masked interrupt status (hibmis) base 0x400f .c000 of fset 0x01c t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 r tcal t0 r tcal t1 lowba t extw reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000.0000 ro reserved 31:4 external w ake-up masked interrupt status 0 ro extw 3 low battery v oltage masked interrupt status 0 ro lowba t 2 r tc alert1 masked interrupt status 0 ro r tcal t1 1 r tc alert0 masked interrupt status 0 ro r tcal t0 0 september 02, 2007 136 preliminary hibernation module register 9: hibernation interrupt clear (hibic), offset 0x020 this register is the interrupt write-one-to-clear register for the hibernation module interrupt sources. hibernation interrupt clear (hibic) base 0x400f .c000 of fset 0x020 t ype r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 r tcal t0 r tcal t1 lowba t extw reserved r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000.0000 ro reserved 31:4 external w ake-up masked interrupt clear reads return an indeterminate value. 0 r/w1c extw 3 low battery v oltage masked interrupt clear reads return an indeterminate value. 0 r/w1c lowba t 2 r tc alert1 masked interrupt clear reads return an indeterminate value. 0 r/w1c r tcal t1 1 r tc alert0 masked interrupt clear reads return an indeterminate value. 0 r/w1c r tcal t0 0 137 september 02, 2007 preliminary lm3s8962 microcontroller register 10: hibernation rtc t rim (hibrtct), offset 0x024 this register contains the value that is used to trim the r tc clock predivider . it represents the computed underflow value that is used during the trim cycle. it is represented as 0x7fff n clock cycles. hibernation r tc t rim (hibr tct) base 0x400f .c000 of fset 0x024 t ype r/w , reset 0x0000.7fff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 trim r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 r tc t rim v alue this value is loaded into the r tc predivider every 64 seconds. it is used to adjust the r tc rate to account for drift and inaccuracy in the clock source. the compensation is made by software by adjusting the default value of 0x7fff up or down. 0x7fff r/w trim 15:0 september 02, 2007 138 preliminary hibernation module register 1 1: hibernation data (hibda t a), offset 0x030-0x12c this address space is implemented as a 64x32-bit memory (256 bytes). it can be loaded by the system processor in order to store any non-volatile state data and will not lose power during a power cut operation. hibernation data (hibda t a) base 0x400f .c000 of fset 0x030-0x12c t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 r td r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 r td r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field hibernation module nv registers[63:0] 0x0000.0000 r/w r td 31:0 139 september 02, 2007 preliminary lm3s8962 microcontroller 8 internal memory the lm3s8962 microcontroller comes with 64 kb of bit-banded sram and 256 kb of flash memory . the flash controller provides a user-friendly interface, making flash programming a simple task. flash protection can be applied to the flash memory on a 2-kb block basis. 8.1 block diagram figure 8-1. flash block diagram 8.2 functional description this section describes the functionality of both the flash and sram memories. 8.2.1 sram memory the internal sram of the stellaris ? devices is located at address 0x2000.0000 of the device memory map. t o reduce the number of time consuming read-modify-write (rmw) operations, arm has introduced bit-banding technology in the cortex-m3 processor . with a bit-band-enabled processor , certain regions in the memory map (sram and peripheral space) can use address aliases to access individual bits in a single, atomic operation. the bit-band alias is calculated by using the formula: september 02, 2007 140 preliminary internal memory flash control fma fcmisc fcim fcris fmc fmd flash t iming usecrl flash protection fmpren fmppen flash array sram array bridge cortex-m3 icode dcode system bus apb user registers user_reg0 user_reg1 user_dbg bit-band alias = bit-band base + (byte offset * 32) + (bit number * 4) for example, if bit 3 at address 0x2000.1000 is to be modified, the bit-band alias is calculated as: 0x2200.0000 + (0x1000 * 32) + (3 * 4) = 0x2202.000c with the alias address calculated, an instruction performing a read/write to address 0x2202.000c allows direct access to only bit 3 of the byte at address 0x2000.1000. for details about bit-banding, please refer to chapter 4, memory map in the arm? cortex?-m3 t echnical reference manual . 8.2.2 flash memory the flash is organized as a set of 1-kb blocks that can be individually erased. erasing a block causes the entire contents of the block to be reset to all 1s. an individual 32-bit word can be programmed to change bits that are currently 1 to a 0. these blocks are paired into a set of 2-kb blocks that can be individually protected. the protection allows blocks to be marked as read-only or execute-only , providing dif ferent levels of code protection. read-only blocks cannot be erased or programmed, protecting the contents of those blocks from being modified. execute-only blocks cannot be erased or programmed, and can only be read by the controller instruction fetch mechanism, protecting the contents of those blocks from being read by either the controller or by a debugger . see also serial flash loader on page 593 for a preprogrammed flash-resident utility used to download code to the flash memory of a device without the use of a debug interface. 8.2.2.1 flash memory t iming the timing for the flash is automatically handled by the flash controller . however , in order to do so, it must know the clock rate of the system in order to time its internal signals properly . the number of clock cycles per microsecond must be provided to the flash controller for it to accomplish this timing. it is software's responsibility to keep the flash controller updated with this information via the usec reload (usecrl) register . on reset, the usecrl register is loaded with a value that configures the flash timing so that it works with the maximum clock rate of the part. if software changes the system operating frequency , the new operating frequency minus 1 (in mhz) must be loaded into usecrl before any flash modifications are attempted. for example, if the device is operating at a speed of 20 mhz, a value of 0x13 (20-1) must be written to the usecrl register . 8.2.2.2 flash memory protection the user is provided two forms of flash protection per 2-kb flash blocks in four pairs of 32-bit wide registers. the protection policy for each form is controlled by individual bits (per policy per block) in the fmppen and fmpren registers. flash memory protection program enable (fmppen) : if set, the block may be programmed (written) or erased. if cleared, the block may not be changed. flash memory protection read enable (fmpren) : if set, the block may be executed or read by software or debuggers. if cleared, the block may only be executed. the contents of the memory block are prohibited from being accessed as data and traversing the dcode bus. the policies may be combined as shown in t able 8-1 on page 142 . 141 september 02, 2007 preliminary lm3s8962 microcontroller t able 8-1. flash protection policy combinations protection fmpren fmppen execute-only protection. the block may only be executed and may not be written or erased. this mode is used to protect code. 0 0 the block may be written, erased or executed, but not read. this combination is unlikely to be used. 0 1 read-only protection. the block may be read or executed but may not be written or erased. this mode is used to lock the block from further modification while allowing any read or execute access. 1 0 no protection. the block may be written, erased, executed or read. 1 1 an access that attempts to program or erase a pe-protected block is prohibited. a controller interrupt may be optionally generated (by setting the amask bit in the fim register) to alert software developers of poorly behaving software during the development and debug phases. an access that attempts to read an re-protected block is prohibited. such accesses return data filled with all 0s. a controller interrupt may be optionally generated to alert software developers of poorly behaving software during the development and debug phases. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this implements a policy of open access and programmability . the register bits may be changed by writing the specific register bit. the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. details on programming these bits are discussed in nonvolatile register programming on page 143 . 8.3 flash memory initialization and configuration 8.3.1 flash programming the stellaris ? devices provide a user-friendly interface for flash programming. all erase/program operations are handled via three registers: fma , fmd , and fmc . 8.3.1.1 t o program a 32-bit word 1. w rite source data to the fmd register . 2. w rite the target address to the fma register . 3. w rite the flash write key and the write bit (a value of 0xa442.0001) to the fmc register . 4. poll the fmc register until the write bit is cleared. 8.3.1.2 t o perform an erase of a 1-kb page 1. w rite the page address to the fma register . 2. w rite the flash write key and the erase bit (a value of 0xa442.0002) to the fmc register . 3. poll the fmc register until the erase bit is cleared. 8.3.1.3 t o perform a mass erase of the flash 1. w rite the flash write key and the merase bit (a value of 0xa442.0004) to the fmc register . 2. poll the fmc register until the merase bit is cleared. september 02, 2007 142 preliminary internal memory 8.3.2 nonvolatile register programming this section discusses how to update registers that are resident within the flash memory itself. these registers exist in a separate space from the main flash array and are not af fected by an erase or mass erase operation. these nonvolatile registers are updated by using the comt bit in the fmc register to activate a write operation. for the user_dbg register , the data to be written must be loaded into the fmd register before it is "committed". all other registers are r/w and can have their operation tried before committing them to nonvolatile memory . important: these registers can only have bits changed from 1 to 0 by the user and there is no mechanism for the user to erase them back to a 1 value. in addition, the user_reg0 , user_reg1 , and user_dbg use bit 31 ( nw ) of their respective registers to indicate that they are available for user write. these three registers can only be written once whereas the flash protection registers may be written multiple times. t able 8-2 on page 143 provides the fma address required for commitment of each of the registers and the source of the data to be written when the comt bit of the fmc register is written with a value of 0xa442.0008. after writing the comt bit, the user may poll the fmc register to wait for the commit operation to complete. t able 8-2. flash resident registers a data source fma v alue register to be committed fmpre0 0x0000.0000 fmpre0 fmpre1 0x0000.0002 fmpre1 fmpre2 0x0000.0004 fmpre2 fmpre3 0x0000.0008 fmpre3 fmppe0 0x0000.0001 fmppe0 fmppe1 0x0000.0003 fmppe1 fmppe2 0x0000.0005 fmppe2 fmppe3 0x0000.0007 fmppe3 user_reg0 0x8000.0000 user_reg0 user_reg1 0x8000.0001 user_reg1 fmd 0x7510.0000 user_dbg a. which fmpren and fmppen registers are available depend on the flash size of your particular stellaris ? device. 8.4 register map t able 8-3 on page 143 lists the flash memory and control registers. the of fset listed is a hexadecimal increment to the register's address. the fma , fmd , fmc , fcris , fcim , and fcmisc registers are relative to the flash control base address of 0x400f .d000. the fmpren , fmppen , usecrl , user_dbg , and user_regn registers are relative to the system control base address of 0x400f .e000. t able 8-3. flash register map see page description reset t ype name offset flash control offset 145 flash memory address 0x0000.0000 r/w fma 0x000 143 september 02, 2007 preliminary lm3s8962 microcontroller see page description reset t ype name offset 146 flash memory data 0x0000.0000 r/w fmd 0x004 147 flash memory control 0x0000.0000 r/w fmc 0x008 149 flash controller raw interrupt status 0x0000.0000 ro fcris 0x00c 150 flash controller interrupt mask 0x0000.0000 r/w fcim 0x010 151 flash controller masked interrupt status and clear 0x0000.0000 r/w1c fcmisc 0x014 system control offset 153 flash memory protection read enable 0 0xffff .ffff r/w fmpre0 0x130 153 flash memory protection read enable 0 0xffff .ffff r/w fmpre0 0x200 154 flash memory protection program enable 0 0xffff .ffff r/w fmppe0 0x134 154 flash memory protection program enable 0 0xffff .ffff r/w fmppe0 0x400 152 usec reload 0x31 r/w usecrl 0x140 155 user debug 0xffff .fffe r/w user_dbg 0x1d0 156 user register 0 0xffff .ffff r/w user_reg0 0x1e0 157 user register 1 0xffff .ffff r/w user_reg1 0x1e4 158 flash memory protection read enable 1 0xffff .ffff r/w fmpre1 0x204 159 flash memory protection read enable 2 0xffff .ffff r/w fmpre2 0x208 160 flash memory protection read enable 3 0xffff .ffff r/w fmpre3 0x20c 161 flash memory protection program enable 1 0xffff .ffff r/w fmppe1 0x404 162 flash memory protection program enable 2 0xffff .ffff r/w fmppe2 0x408 163 flash memory protection program enable 3 0xffff .ffff r/w fmppe3 0x40c 8.5 flash register descriptions (flash control offset) the remainder of this section lists and describes the flash memory registers, in numerical order by address of fset. registers in this section are relative to the flash control base address of 0x400f .d000. september 02, 2007 144 preliminary internal memory register 1: flash memory address (fma), offset 0x000 during a write operation, this register contains a 4-byte-aligned address and specifies where the data is written. during erase operations, this register contains a 1 kb-aligned address and specifies which page is erased. note that the alignment requirements must be met by software or the results of the operation are unpredictable. flash memory address (fma) base 0x400f .d000 of fset 0x000 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 offset reserved r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 offset r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:18 address of fset address of fset in flash where operation is performed, except for nonvolatile registers (see nonvolatile register programming on page 143 for details on values for this field). 0x0 r/w offset 17:0 145 september 02, 2007 preliminary lm3s8962 microcontroller register 2: flash memory data (fmd), offset 0x004 this register contains the data to be written during the programming cycle or read during the read cycle. note that the contents of this register are undefined for a read access of an execute-only block. this register is not used during the erase cycles. flash memory data (fmd) base 0x400f .d000 of fset 0x004 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 da t a r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 da t a r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field data v alue data value for write operation. 0x0 r/w da t a 31:0 september 02, 2007 146 preliminary internal memory register 3: flash memory control (fmc), offset 0x008 when this register is written, the flash controller initiates the appropriate access cycle for the location specified by the flash memory address (fma) register (see page 145 ). if the access is a write access, the data contained in the flash memory data (fmd) register (see page 146 ) is written. this is the final register written and initiates the memory operation. there are four control bits in the lower byte of this register that, when set, initiate the memory operation. the most used of these register bits are the erase and write bits. it is a programming error to write multiple control bits and the results of such an operation are unpredictable. flash memory control (fmc) base 0x400f .d000 of fset 0x008 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wrkey wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 write erase merase comt reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field flash w rite key this field contains a write key , which is used to minimize the incidence of accidental flash writes. the value 0xa442 must be written into this field for a write to occur . w rites to the fmc register without this wrkey value are ignored. a read of this field returns the value 0. 0x0 wo wrkey 31:16 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 15:4 commit register v alue commit (write) of register value to nonvolatile storage. a write of 0 has no ef fect on the state of this bit. if read, the state of the previous commit access is provided. if the previous commit access is complete, a 0 is returned; otherwise, if the commit access is not complete, a 1 is returned. this can take up to 50 s. 0 r/w comt 3 mass erase flash memory if this bit is set, the flash main memory of the device is all erased. a write of 0 has no ef fect on the state of this bit. if read, the state of the previous mass erase access is provided. if the previous mass erase access is complete, a 0 is returned; otherwise, if the previous mass erase access is not complete, a 1 is returned. this can take up to 250 ms. 0 r/w merase 2 147 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field erase a page of flash memory if this bit is set, the page of flash main memory as specified by the contents of fma is erased. a write of 0 has no ef fect on the state of this bit. if read, the state of the previous erase access is provided. if the previous erase access is complete, a 0 is returned; otherwise, if the previous erase access is not complete, a 1 is returned. this can take up to 25 ms. 0 r/w erase 1 w rite a w ord into flash memory if this bit is set, the data stored in fmd is written into the location as specified by the contents of fma . a write of 0 has no ef fect on the state of this bit. if read, the state of the previous write update is provided. if the previous write access is complete, a 0 is returned; otherwise, if the write access is not complete, a 1 is returned. this can take up to 50 s. 0 r/w write 0 september 02, 2007 148 preliminary internal memory register 4: flash controller raw interrupt status (fcris), offset 0x00c this register indicates that the flash controller has an interrupt condition. an interrupt is only signaled if the corresponding fcim register bit is set. flash controller raw interrupt status (fcris) base 0x400f .d000 of fset 0x00c t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 aris pris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:2 programming raw interrupt status this bit indicates the current state of the programming cycle. if set, the programming cycle completed; if cleared, the programming cycle has not completed. programming cycles are either write or erase actions generated through the flash memory control (fmc) register bits (see page 147 ). 0 ro pris 1 access raw interrupt status this bit indicates if the flash was improperly accessed. if set, the program tried to access the flash counter to the policy as set in the flash memory protection read enable (fmpren) and flash memory protection program enable (fmppen) registers. otherwise, no access has tried to improperly access the flash. 0 ro aris 0 149 september 02, 2007 preliminary lm3s8962 microcontroller register 5: flash controller interrupt mask (fcim), offset 0x010 this register controls whether the flash controller generates interrupts to the controller . flash controller interrupt mask (fcim) base 0x400f .d000 of fset 0x010 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 amask pmask reserved r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:2 programming interrupt mask this bit controls the reporting of the programming raw interrupt status to the controller . if set, a programming-generated interrupt is promoted to the controller . otherwise, interrupts are recorded but suppressed from the controller . 0 r/w pmask 1 access interrupt mask this bit controls the reporting of the access raw interrupt status to the controller . if set, an access-generated interrupt is promoted to the controller . otherwise, interrupts are recorded but suppressed from the controller . 0 r/w amask 0 september 02, 2007 150 preliminary internal memory register 6: flash controller masked interrupt status and clear (fcmisc), offset 0x014 this register provides two functions. first, it reports the cause of an interrupt by indicating which interrupt source or sources are signalling the interrupt. second, it serves as the method to clear the interrupt reporting. flash controller masked interrupt status and clear (fcmisc) base 0x400f .d000 of fset 0x014 t ype r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 amisc pmisc reserved r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:2 programming masked interrupt status and clear this bit indicates whether an interrupt was signaled because a programming cycle completed and was not masked. this bit is cleared by writing a 1. the pris bit in the fcris register (see page 149 ) is also cleared when the pmisc bit is cleared. 0 r/w1c pmisc 1 access masked interrupt status and clear this bit indicates whether an interrupt was signaled because an improper access was attempted and was not masked. this bit is cleared by writing a 1. the aris bit in the fcris register is also cleared when the amisc bit is cleared. 0 r/w1c amisc 0 8.6 flash register descriptions (system control offset) the remainder of this section lists and describes the flash memory registers, in numerical order by address of fset. registers in this section are relative to the system control base address of 0x400f .e000. 151 september 02, 2007 preliminary lm3s8962 microcontroller register 7: usec reload (usecrl), offset 0x140 note: of fset is relative to system control base address of 0x400f .e000 this register is provided as a means of creating a 1-s tick divider reload value for the flash controller . the internal flash has specific minimum and maximum requirements on the length of time the high voltage write pulse can be applied. it is required that this register contain the operating frequency (in mhz -1) whenever the flash is being erased or programmed. the user is required to change this value if the clocking conditions are changed for a flash erase/program operation. usec reload (usecrl) base 0x400f .e000 of fset 0x140 t ype r/w , reset 0x31 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 usec reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 microsecond reload v alue mhz -1 of the controller clock when the flash is being erased or programmed. usec should be set to 0x31 (50 mhz) whenever the flash is being erased or programmed. 0x31 r/w usec 7:0 september 02, 2007 152 preliminary internal memory register 8: flash memory protection read enable 0 (fmpre0), offset 0x130 and 0x200 note: this register is aliased for backwards compatability . note: of fset is relative to system control base address of 0x400fe000. this register stores the read-only protection bits for each 2-kb flash block ( fmppen stores the execute-only bits). this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability . the register bits may be changed by writing the specific register bit. however , this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. for additional information, see the "flash memory protection" section. flash memory protection read enable 0 (fmpre0) base 0x400f .d000 of fset 0x130 and 0x200 t ype r/w , reset 0xffff .ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field flash read enable enables 2-kb flash blocks to be executed or read. the policies may be combined as shown in the table flash protection policy combinations. description v alue enables 256 kb of flash. 0xffffffff 0xffffffff r/w read_enable 31:0 153 september 02, 2007 preliminary lm3s8962 microcontroller register 9: flash memory protection program enable 0 (fmppe0), offset 0x134 and 0x400 note: this register is aliased for backwards compatability . note: of fset is relative to system control base address of 0x400fe000. this register stores the execute-only protection bits for each 2-kb flash block ( fmpren stores the execute-only bits). this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability . the register bits may be changed by writing the specific register bit. however , this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. for additional information, see the "flash memory protection" section. flash memory protection program enable 0 (fmppe0) base 0x400f .d000 of fset 0x134 and 0x400 t ype r/w , reset 0xffff .ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field flash programming enable configures 2-kb flash blocks to be execute only . the policies may be combined as shown in the table flash protection policy combinations. description v alue enables 256 kb of flash. 0xffffffff 0xffffffff r/w prog_enable 31:0 september 02, 2007 154 preliminary internal memory register 10: user debug (user_dbg), offset 0x1d0 note: of fset is relative to system control base address of 0x400fe000. this register provides a write-once mechanism to disable external debugger access to the device in addition to 27 additional bits of user-defined data. the dbg0 bit (bit 0) is set to 0 from the factory and the dbg1 bit (bit 1) is set to 1, which enables external debuggers. changing the dbg1 bit to 0 disables any external debugger access to the device permanently , starting with the next power-up cycle of the device. the notwritten bit (bit 31) indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. user debug (user_dbg) base 0x400f .e000 of fset 0x1d0 t ype r/w , reset 0xffff .fffe 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 da t a nw r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 dbg0 dbg1 da t a r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field user debug not w ritten specifies that this 32-bit dword has not been written. 1 r/w nw 31 user data contains the user data value. this field is initialized to all 1s and can only be written once. 0x1fffffff r/w da t a 30:2 debug control 1 the dbg1 bit must be 1 and dbg0 must be 0 for debug to be available. 1 r/w dbg1 1 debug control 0 the dbg1 bit must be 1 and dbg0 must be 0 for debug to be available. 0 r/w dbg0 0 155 september 02, 2007 preliminary lm3s8962 microcontroller register 1 1: user register 0 (user_reg0), offset 0x1e0 note: of fset is relative to system control base address of 0x400fe000. this register provides 31 bits of user-defined data that is non-volatile and can only be written once. bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. the write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external eeprom or other non-volatile device. user register 0 (user_reg0) base 0x400f .e000 of fset 0x1e0 t ype r/w , reset 0xffff .ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 da t a nw r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 da t a r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field not w ritten specifies that this 32-bit dword has not been written. 1 r/w nw 31 user data contains the user data value. this field is initialized to all 1s and can only be written once. 0x7fffffff r/w da t a 30:0 september 02, 2007 156 preliminary internal memory register 12: user register 1 (user_reg1), offset 0x1e4 note: of fset is relative to system control base address of 0x400fe000. this register provides 31 bits of user-defined data that is non-volatile and can only be written once. bit 31 indicates that the register is available to be written and is controlled through hardware to ensure that the register is only written once. the write-once characteristics of this register are useful for keeping static information like communication addresses that need to be unique per part and would otherwise require an external eeprom or other non-volatile device. user register 1 (user_reg1) base 0x400f .e000 of fset 0x1e4 t ype r/w , reset 0xffff .ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 da t a nw r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 da t a r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field not w ritten specifies that this 32-bit dword has not been written. 1 r/w nw 31 user data contains the user data value. this field is initialized to all 1s and can only be written once. 0x7fffffff r/w da t a 30:0 157 september 02, 2007 preliminary lm3s8962 microcontroller register 13: flash memory protection read enable 1 (fmpre1), offset 0x204 note: of fset is relative to system control base address of 0x400fe000. this register stores the read-only protection bits for each 2-kb flash block ( fmppen stores the execute-only bits). this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability . the register bits may be changed by writing the specific register bit. however , this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. for additional information, see the "flash memory protection" section. flash memory protection read enable 1 (fmpre1) base 0x400f .e000 of fset 0x204 t ype r/w , reset 0xffff .ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field flash read enable enables 2-kb flash blocks to be executed or read. the policies may be combined as shown in the table flash protection policy combinations. description v alue enables 256 kb of flash. 0xffffffff 0xffffffff r/w read_enable 31:0 september 02, 2007 158 preliminary internal memory register 14: flash memory protection read enable 2 (fmpre2), offset 0x208 note: of fset is relative to system control base address of 0x400fe000. this register stores the read-only protection bits for each 2-kb flash block ( fmppen stores the execute-only bits). this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability . the register bits may be changed by writing the specific register bit. however , this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. for additional information, see the "flash memory protection" section. flash memory protection read enable 2 (fmpre2) base 0x400f .e000 of fset 0x208 t ype r/w , reset 0xffff .ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field flash read enable enables 2-kb flash blocks to be executed or read. the policies may be combined as shown in the table flash protection policy combinations. description v alue enables 256 kb of flash. 0xffffffff 0xffffffff r/w read_enable 31:0 159 september 02, 2007 preliminary lm3s8962 microcontroller register 15: flash memory protection read enable 3 (fmpre3), offset 0x20c note: of fset is relative to system control base address of 0x400fe000. this register stores the read-only protection bits for each 2-kb flash block ( fmppen stores the execute-only bits). this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability . the register bits may be changed by writing the specific register bit. however , this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. for additional information, see the "flash memory protection" section. flash memory protection read enable 3 (fmpre3) base 0x400f .e000 of fset 0x20c t ype r/w , reset 0xffff .ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 read_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field flash read enable enables 2-kb flash blocks to be executed or read. the policies may be combined as shown in the table flash protection policy combinations. description v alue enables 256 kb of flash. 0xffffffff 0xffffffff r/w read_enable 31:0 september 02, 2007 160 preliminary internal memory register 16: flash memory protection program enable 1 (fmppe1), offset 0x404 note: of fset is relative to system control base address of 0x400fe000. this register stores the execute-only protection bits for each 2-kb flash block ( fmpren stores the execute-only bits). this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability . the register bits may be changed by writing the specific register bit. however , this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. for additional information, see the "flash memory protection" section. flash memory protection program enable 1 (fmppe1) base 0x400f .e000 of fset 0x404 t ype r/w , reset 0xffff .ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field flash programming enable configures 2-kb flash blocks to be execute only . the policies may be combined as shown in the table flash protection policy combinations. description v alue enables 256 kb of flash. 0xffffffff 0xffffffff r/w prog_enable 31:0 161 september 02, 2007 preliminary lm3s8962 microcontroller register 17: flash memory protection program enable 2 (fmppe2), offset 0x408 note: of fset is relative to system control base address of 0x400fe000. this register stores the execute-only protection bits for each 2-kb flash block ( fmpren stores the execute-only bits). this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability . the register bits may be changed by writing the specific register bit. however , this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. for additional information, see the "flash memory protection" section. flash memory protection program enable 2 (fmppe2) base 0x400f .e000 of fset 0x408 t ype r/w , reset 0xffff .ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field flash programming enable configures 2-kb flash blocks to be execute only . the policies may be combined as shown in the table flash protection policy combinations. description v alue enables 256 kb of flash. 0xffffffff 0xffffffff r/w prog_enable 31:0 september 02, 2007 162 preliminary internal memory register 18: flash memory protection program enable 3 (fmppe3), offset 0x40c note: of fset is relative to system control base address of 0x400fe000. this register stores the execute-only protection bits for each 2-kb flash block ( fmpren stores the execute-only bits). this register is loaded during the power-on reset sequence. the factory settings for the fmpren and fmppen registers are a value of 1 for all implemented banks. this achieves a policy of open access and programmability . the register bits may be changed by writing the specific register bit. however , this register is r/w0; the user can only change the protection bit from a 1 to a 0 (and may not change a 0 to a 1). the changes are not permanent until the register is committed (saved), at which point the bit change is permanent. if a bit is changed from a 1 to a 0 and not committed, it may be restored by executing a power-on reset sequence. for additional information, see the "flash memory protection" section. flash memory protection program enable 3 (fmppe3) base 0x400f .e000 of fset 0x40c t ype r/w , reset 0xffff .ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 prog_enable r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field flash programming enable configures 2-kb flash blocks to be execute only . the policies may be combined as shown in the table flash protection policy combinations. description v alue enables 256 kb of flash. 0xffffffff 0xffffffff r/w prog_enable 31:0 163 september 02, 2007 preliminary lm3s8962 microcontroller 9 general-purpose input/outputs (gpios) the gpio module is composed of seven physical gpio blocks, each corresponding to an individual gpio port (port a, port b, port c, port d, port e, port f , and port g, ). the gpio module is firm-compliant and supports 5-42 programmable input/output pins, depending on the peripherals being used. the gpio module has the following features: programmable control for gpio interrupts C interrupt generation masking C edge-triggered on rising, falling, or both C level-sensitive on high or low values 5-v-tolerant input/outputs bit masking in both read and write operations through address lines programmable control for gpio pad configuration C w eak pull-up or pull-down resistors C 2-ma, 4-ma, and 8-ma pad drive C slew rate control for the 8-ma drive C open drain enables C digital input enables 9.1 functional description important: all gpio pins are tri-stated by default ( gpioafsel =0, gpioden =0, gpiopdr =0, and gpiopur =0), with the exception of the five jt ag/swd pins ( pb7 and pc[3:0] ). the jt ag/swd pins default to their jt ag/swd functionality ( gpioafsel =1, gpioden=1 and gpiopur =1). a power-on-reset ( por ) or asserting rst puts both groups of pins back to their default state. each gpio port is a separate hardware instantiation of the same physical block. the lm3s8962 microcontroller contains seven ports and thus seven of these physical gpio blocks. 9.1.1 data control the data control registers allow software to configure the operational modes of the gpios. the data direction register configures the gpio as an input or an output while the data register either captures incoming data or drives it out to the pads. 9.1.1.1 data direction operation the gpio direction (gpiodir) register (see page 172 ) is used to configure each individual pin as an input or output. when the data direction bit is set to 0, the gpio is configured as an input and the corresponding data register bit will capture and store the value on the gpio port. when the data september 02, 2007 164 preliminary general-purpose input/outputs (gpios) direction bit is set to 1, the gpio is configured as an output and the corresponding data register bit will be driven out on the gpio port. 9.1.1.2 data register operation t o aid in the ef ficiency of software, the gpio ports allow for the modification of individual bits in the gpio data (gpioda t a) register (see page 171 ) by using bits [9:2] of the address bus as a mask. this allows software drivers to modify individual gpio pins in a single instruction, without af fecting the state of the other pins. this is in contrast to the "typical" method of doing a read-modify-write operation to set or clear an individual gpio pin. t o accommodate this feature, the gpioda t a register covers 256 locations in the memory map. during a write, if the address bit associated with that data bit is set to 1, the value of the gpioda t a register is altered. if it is cleared to 0, it is left unchanged. for example, writing a value of 0xeb to the address gpioda t a + 0x098 would yield as shown in figure 9-1 on page 165 , where u is data unchanged by the write. figure 9-1. gpioda t a w rite example during a read, if the address bit associated with the data bit is set to 1, the value is read. if the address bit associated with the data bit is set to 0, it is read as a zero, regardless of its actual value. for example, reading address gpioda t a + 0x0c4 yields as shown in figure 9-2 on page 165 . figure 9-2. gpioda t a read example 9.1.2 interrupt control the interrupt capabilities of each gpio port are controlled by a set of seven registers. with these registers, it is possible to select the source of the interrupt, its polarity , and the edge properties. when one or more gpio inputs cause an interrupt, a single interrupt output is sent to the interrupt controller for the entire gpio port. for edge-triggered interrupts, software must clear the interrupt to enable any further interrupts. for a level-sensitive interrupt, it is assumed that the external source holds the level constant for the interrupt to be recognized by the controller . three registers are required to define the edge or sense that causes interrupts: 165 september 02, 2007 preliminary lm3s8962 microcontroller 0 1 0 0 1 1 0 0 1 0 u 1 u u 0 1 u u 9 8 7 6 5 4 3 2 1 0 1 1 1 0 0 1 1 1 7 6 5 4 3 2 1 0 gpioda t a 0xeb 0x098 addr[9:2] 0 1 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 9 8 7 6 5 4 3 2 1 0 0 1 1 1 1 1 1 0 7 6 5 4 3 2 1 0 returned v alue gpioda t a 0x0c4 addr[9:2] gpio interrupt sense (gpiois) register (see page 173 ) gpio interrupt both edges (gpioibe) register (see page 174 ) gpio interrupt event (gpioiev) register (see page 175 ) interrupts are enabled/disabled via the gpio interrupt mask (gpioim) register (see page 176 ). when an interrupt condition occurs, the state of the interrupt signal can be viewed in two locations: the gpio raw interrupt status (gpioris) and gpio masked interrupt status (gpiomis) registers (see page 177 and page 178 ). as the name implies, the gpiomis register only shows interrupt conditions that are allowed to be passed to the controller . the gpioris register indicates that a gpio pin meets the conditions for an interrupt, but has not necessarily been sent to the controller . in addition to providing gpio functionality , pb4 can also be used as an external trigger for the adc. if pb4 is configured as a non-masked interrupt pin ( gpioim is set to 1), not only is an interrupt for portb generated, but an external trigger signal is sent to the adc. if the adc event multiplexer select (adcemux) register is configured to use the external trigger , an adc conversion is initiated. if no other portb pins are being used to generate interrupts, the arm integrated nested v ectored interrupt controller (nvic) interrupt set enable (setna) register can disable the portb interrupts and the adc interrupt can be used to read back the converted data. otherwise, the portb interrupt handler needs to ignore and clear interrupts on b4, and wait for the adc interrupt or the adc interrupt needs to be disabled in the setna register and the portb interrupt handler polls the adc registers until the conversion is completed. interrupts are cleared by writing a 1 to the gpio interrupt clear (gpioicr) register (see page 179 ). when programming the following interrupt control registers, the interrupts should be masked ( gpioim set to 0). w riting any value to an interrupt control register ( gpiois , gpioibe , or gpioiev ) can generate a spurious interrupt if the corresponding bits are enabled. 9.1.3 mode control the gpio pins can be controlled by either hardware or software. when hardware control is enabled via the gpio alternate function select (gpioafsel) register (see page 180 ), the pin state is controlled by its alternate function (that is, the peripheral). software control corresponds to gpio mode, where the gpioda t a register is used to read/write the corresponding pins. 9.1.4 commit control the commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. w rites to protected bits of the gpio alternate function select (gpioafsel) register (see page 180 ) are not committed to storage unless the gpio lock (gpiolock) register (see page 190 ) has been unlocked and the appropriate bits of the gpio commit (gpiocr) register (see page 191 ) have been set to 1. 9.1.5 pad control the pad control registers allow for gpio pad configuration by software based on the application requirements. the pad control registers include the gpiodr2r , gpiodr4r , gpiodr8r , gpioodr , gpiopur , gpiopdr , gpioslr , and gpioden registers. september 02, 2007 166 preliminary general-purpose input/outputs (gpios) 9.1.6 identification the identification registers configured at reset allow software to detect and identify the module as a gpio block. the identification registers include the gpioperiphid0 - gpioperiphid7 registers as well as the gpiopcellid0 - gpiopcellid3 registers. 9.2 initialization and configuration t o use the gpio, the peripheral clock must be enabled by setting the appropriate gpio port bit field ( gpion ) in the rcgc2 register . on reset, all gpio pins (except for the five jt ag pins) are configured out of reset to be undriven (tristate): gpioafsel =0, gpioden =0, gpiopdr =0, and gpiopur =0. t able 9-1 on page 167 shows all possible configurations of the gpio pads and the control register settings required to achieve them. t able 9-2 on page 168 shows how a rising edge interrupt would be configured for pin 2 of a gpio port. t able 9-1. gpio pad configuration examples gpio register bit v alue a configuration slr dr8r dr4r dr2r pdr pur den odr dir afsel x x x x ? ? 1 0 0 0 digital input (gpio) ? ? ? ? ? ? 1 0 1 0 digital output (gpio) x x x x x x 1 1 0 0 open drain input (gpio) ? ? ? ? x x 1 1 1 0 open drain output (gpio) ? ? ? ? x x 1 1 x 1 open drain input/output (i 2 c) x x x x ? ? 1 0 x 1 digital input (t imer ccp) x x x x ? ? 1 0 x 1 digital input (qei) ? ? ? ? ? ? 1 0 x 1 digital output (pwm) ? ? ? ? ? ? 1 0 x 1 digital output (t imer pwm) ? ? ? ? ? ? 1 0 x 1 digital input/output (ssi) ? ? ? ? ? ? 1 0 x 1 digital input/output (uar t) x x x x 0 0 0 0 0 0 analog input (comparator) ? ? ? ? ? ? 1 0 x 1 digital output (comparator) a. x=ignored (dont care bit) ?=can be either 0 or 1, depending on the configuration 167 september 02, 2007 preliminary lm3s8962 microcontroller t able 9-2. gpio interrupt configuration example pin 2 bit v alue a desired interrupt event t rigger register 0 1 2 3 4 5 6 7 x x 0 x x x x x 0=edge 1=level gpiois x x 0 x x x x x 0=single edge 1=both edges gpioibe x x 1 x x x x x 0=low level, or negative edge 1=high level, or positive edge gpioiev 0 0 1 0 0 0 0 0 0=masked 1=not masked gpioim a. x=ignored (dont care bit) 9.3 register map t able 9-3 on page 169 lists the gpio registers. the of fset listed is a hexadecimal increment to the register s address, relative to that gpio port s base address: gpio port a: 0x4000.4000 gpio port b: 0x4000.5000 gpio port c: 0x4000.6000 gpio port d: 0x4000.7000 gpio port e: 0x4002.4000 gpio port f: 0x4002.5000 gpio port g: 0x4002.6000 important: the gpio registers in this chapter are duplicated in each gpio block, however , depending on the block, all eight bits may not be connected to a gpio pad. in those cases, writing to those unconnected bits has no ef fect and reading those unconnected bits returns no meaningful data. note: the default reset value for the gpioafsel , gpiopur , and gpioden registers are 0x0000.0000 for all gpio pins, with the exception of the five jt ag/swd pins ( pb7 and pc[3:0] ). these five pins default to jt ag/swd functionality . because of this, the default reset value of these registers for gpio port b is 0x0000.0080 while the default reset value for port c is 0x0000.000f . september 02, 2007 168 preliminary general-purpose input/outputs (gpios) the default register type for the gpiocr register is ro for all gpio pins, with the exception of the five jt ag/swd pins ( pb7 and pc[3:0] ). these five pins are currently the only gpios that are protected by the gpiocr register . because of this, the register type for gpio port b7 and gpio port c[3:0] is r/w . the default reset value for the gpiocr register is 0x0000.00ff for all gpio pins, with the exception of the five jt ag/swd pins ( pb7 and pc[3:0] ). t o ensure that the jt ag port is not accidentally programmed as a gpio, these five pins default to non-commitable. because of this, the default reset value of gpiocr for gpio port b is 0x0000.007f while the default reset value of gpiocr for port c is 0x0000.00f0. t able 9-3. gpio register map see page description reset t ype name offset 171 gpio data 0x0000.0000 r/w gpioda t a 0x000 172 gpio direction 0x0000.0000 r/w gpiodir 0x400 173 gpio interrupt sense 0x0000.0000 r/w gpiois 0x404 174 gpio interrupt both edges 0x0000.0000 r/w gpioibe 0x408 175 gpio interrupt event 0x0000.0000 r/w gpioiev 0x40c 176 gpio interrupt mask 0x0000.0000 r/w gpioim 0x410 177 gpio raw interrupt status 0x0000.0000 ro gpioris 0x414 178 gpio masked interrupt status 0x0000.0000 ro gpiomis 0x418 179 gpio interrupt clear 0x0000.0000 w1c gpioicr 0x41c 180 gpio alternate function select - r/w gpioafsel 0x420 182 gpio 2-ma drive select 0x0000.00ff r/w gpiodr2r 0x500 183 gpio 4-ma drive select 0x0000.0000 r/w gpiodr4r 0x504 184 gpio 8-ma drive select 0x0000.0000 r/w gpiodr8r 0x508 185 gpio open drain select 0x0000.0000 r/w gpioodr 0x50c 186 gpio pull-up select - r/w gpiopur 0x510 187 gpio pull-down select 0x0000.0000 r/w gpiopdr 0x514 188 gpio slew rate control select 0x0000.0000 r/w gpioslr 0x518 189 gpio digital enable - r/w gpioden 0x51c 190 gpio lock 0x0000.0001 r/w gpiolock 0x520 191 gpio commit - - gpiocr 0x524 193 gpio peripheral identification 4 0x0000.0000 ro gpioperiphid4 0xfd0 194 gpio peripheral identification 5 0x0000.0000 ro gpioperiphid5 0xfd4 195 gpio peripheral identification 6 0x0000.0000 ro gpioperiphid6 0xfd8 196 gpio peripheral identification 7 0x0000.0000 ro gpioperiphid7 0xfdc 197 gpio peripheral identification 0 0x0000.0061 ro gpioperiphid0 0xfe0 169 september 02, 2007 preliminary lm3s8962 microcontroller see page description reset t ype name offset 198 gpio peripheral identification 1 0x0000.0000 ro gpioperiphid1 0xfe4 199 gpio peripheral identification 2 0x0000.0018 ro gpioperiphid2 0xfe8 200 gpio peripheral identification 3 0x0000.0001 ro gpioperiphid3 0xfec 201 gpio primecell identification 0 0x0000.000d ro gpiopcellid0 0xff0 202 gpio primecell identification 1 0x0000.00f0 ro gpiopcellid1 0xff4 203 gpio primecell identification 2 0x0000.0005 ro gpiopcellid2 0xff8 204 gpio primecell identification 3 0x0000.00b1 ro gpiopcellid3 0xffc 9.4 register descriptions the remainder of this section lists and describes the gpio registers, in numerical order by address of fset. september 02, 2007 170 preliminary general-purpose input/outputs (gpios) register 1: gpio data (gpioda t a), offset 0x000 the gpioda t a register is the data register . in software control mode, values written in the gpioda t a register are transferred onto the gpio port pins if the respective pins have been configured as outputs through the gpio direction (gpiodir) register (see page 172 ). in order to write to gpioda t a , the corresponding bits in the mask, resulting from the address bus bits [9:2], must be high. otherwise, the bit values remain unchanged by the write. similarly , the values read from this register are determined for each bit by the mask bit derived from the address used to access the data register , bits [9:2]. bits that are 1 in the address mask cause the corresponding bits in gpioda t a to be read, and bits that are 0 in the address mask cause the corresponding bits in gpioda t a to be read as 0, regardless of their value. a read from gpioda t a returns the last bit value written if the respective pins are configured as outputs, or it returns the value on the corresponding input pin when these are configured as inputs. all bits are cleared by a reset. gpio data (gpioda t a) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0x000 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 da t a reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio data this register is virtually mapped to 256 locations in the address space. t o facilitate the reading and writing of data to these registers by independent drivers, the data read from and the data written to the registers are masked by the eight address lines ipaddr[9:2] . reads from this register return its current state. w rites to this register only af fect bits that are not masked by ipaddr[9:2] and are configured as outputs. see data register operation on page 165 for examples of reads and writes. 0x00 r/w da t a 7:0 171 september 02, 2007 preliminary lm3s8962 microcontroller register 2: gpio direction (gpiodir), offset 0x400 the gpiodir register is the data direction register . bits set to 1 in the gpiodir register configure the corresponding pin to be an output, while bits set to 0 configure the pins to be inputs. all bits are cleared by a reset, meaning all gpio pins are inputs by default. gpio direction (gpiodir) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0x400 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 dir reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio data direction the dir values are defined as follows: description v alue pins are inputs. 0 pins are outputs. 1 0x00 r/w dir 7:0 september 02, 2007 172 preliminary general-purpose input/outputs (gpios) register 3: gpio interrupt sense (gpiois), offset 0x404 the gpiois register is the interrupt sense register . bits set to 1 in gpiois configure the corresponding pins to detect levels, while bits set to 0 configure the pins to detect edges. all bits are cleared by a reset. gpio interrupt sense (gpiois) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0x404 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 is reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio interrupt sense the is values are defined as follows: description v alue edge on corresponding pin is detected (edge-sensitive). 0 level on corresponding pin is detected (level-sensitive). 1 0x00 r/w is 7:0 173 september 02, 2007 preliminary lm3s8962 microcontroller register 4: gpio interrupt both edges (gpioibe), offset 0x408 the gpioibe register is the interrupt both-edges register . when the corresponding bit in the gpio interrupt sense (gpiois) register (see page 173 ) is set to detect edges, bits set to high in gpioibe configure the corresponding pin to detect both rising and falling edges, regardless of the corresponding bit in the gpio interrupt event (gpioiev) register (see page 175 ). clearing a bit configures the pin to be controlled by gpioiev . all bits are cleared by a reset. gpio interrupt both edges (gpioibe) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0x408 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ibe reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio interrupt both edges the ibe values are defined as follows: description v alue interrupt generation is controlled by the gpio interrupt event (gpioiev) register (see page 175 ). 0 both edges on the corresponding pin trigger an interrupt. 1 note: single edge is determined by the corresponding bit in gpioiev . 0x00 r/w ibe 7:0 september 02, 2007 174 preliminary general-purpose input/outputs (gpios) register 5: gpio interrupt event (gpioiev), offset 0x40c the gpioiev register is the interrupt event register . bits set to high in gpioiev configure the corresponding pin to detect rising edges or high levels, depending on the corresponding bit value in the gpio interrupt sense (gpiois) register (see page 173 ). clearing a bit configures the pin to detect falling edges or low levels, depending on the corresponding bit value in gpiois . all bits are cleared by a reset. gpio interrupt event (gpioiev) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0x40c t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 iev reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio interrupt event the iev values are defined as follows: description v alue falling edge or low levels on corresponding pins trigger interrupts. 0 rising edge or high levels on corresponding pins trigger interrupts. 1 0x00 r/w iev 7:0 175 september 02, 2007 preliminary lm3s8962 microcontroller register 6: gpio interrupt mask (gpioim), offset 0x410 the gpioim register is the interrupt mask register . bits set to high in gpioim allow the corresponding pins to trigger their individual interrupts and the combined gpiointr line. clearing a bit disables interrupt triggering on that pin. all bits are cleared by a reset. gpio interrupt mask (gpioim) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0x410 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ime reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio interrupt mask enable the ime values are defined as follows: description v alue corresponding pin interrupt is masked. 0 corresponding pin interrupt is not masked. 1 0x00 r/w ime 7:0 september 02, 2007 176 preliminary general-purpose input/outputs (gpios) register 7: gpio raw interrupt status (gpioris), offset 0x414 the gpioris register is the raw interrupt status register . bits read high in gpioris reflect the status of interrupt trigger conditions detected (raw , prior to masking), indicating that all the requirements have been met, before they are finally allowed to trigger by the gpio interrupt mask (gpioim) register (see page 176 ). bits read as zero indicate that corresponding input pins have not initiated an interrupt. all bits are cleared by a reset. gpio raw interrupt status (gpioris) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0x414 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio interrupt raw status reflects the status of interrupt trigger condition detection on pins (raw , prior to masking). the ris values are defined as follows: description v alue corresponding pin interrupt requirements not met. 0 corresponding pin interrupt has met requirements. 1 0x00 ro ris 7:0 177 september 02, 2007 preliminary lm3s8962 microcontroller register 8: gpio masked interrupt status (gpiomis), offset 0x418 the gpiomis register is the masked interrupt status register . bits read high in gpiomis reflect the status of input lines triggering an interrupt. bits read as low indicate that either no interrupt has been generated, or the interrupt is masked. in addition to providing gpio functionality , pb4 can also be used as an external trigger for the adc. if pb4 is configured as a non-masked interrupt pin ( gpioim is set to 1), not only is an interrupt for portb generated, but an external trigger signal is sent to the adc. if the adc event multiplexer select (adcemux) register is configured to use the external trigger , an adc conversion is initiated. if no other portb pins are being used to generate interrupts, the arm integrated nested v ectored interrupt controller (nvic) interrupt set enable (setna) register can disable the portb interrupts and the adc interrupt can be used to read back the converted data. otherwise, the portb interrupt handler needs to ignore and clear interrupts on b4, and wait for the adc interrupt or the adc interrupt needs to be disabled in the setna register and the portb interrupt handler polls the adc registers until the conversion is completed. gpiomis is the state of the interrupt after masking. gpio masked interrupt status (gpiomis) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0x418 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 mis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio masked interrupt status masked value of interrupt due to corresponding pin. the mis values are defined as follows: description v alue corresponding gpio line interrupt not active. 0 corresponding gpio line asserting interrupt. 1 0x00 ro mis 7:0 september 02, 2007 178 preliminary general-purpose input/outputs (gpios) register 9: gpio interrupt clear (gpioicr), offset 0x41c the gpioicr register is the interrupt clear register . w riting a 1 to a bit in this register clears the corresponding interrupt edge detection logic register . w riting a 0 has no ef fect. gpio interrupt clear (gpioicr) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0x41c t ype w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ic reserved w1c w1c w1c w1c w1c w1c w1c w1c ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio interrupt clear the ic values are defined as follows: description v alue corresponding interrupt is unaf fected. 0 corresponding interrupt is cleared. 1 0x00 w1c ic 7:0 179 september 02, 2007 preliminary lm3s8962 microcontroller register 10: gpio alternate function select (gpioafsel), offset 0x420 the gpioafsel register is the mode control select register . w riting a 1 to any bit in this register selects the hardware control for the corresponding gpio line. all bits are cleared by a reset, therefore no gpio line is set to hardware control by default. the commit control registers provide a layer of protection against accidental programming of critical hardware peripherals. w rites to protected bits of the gpio alternate function select (gpioafsel) register (see page 180 ) are not committed to storage unless the gpio lock (gpiolock) register (see page 190 ) has been unlocked and the appropriate bits of the gpio commit (gpiocr) register (see page 191 ) have been set to 1. important: all gpio pins are tri-stated by default ( gpioafsel =0, gpioden =0, gpiopdr =0, and gpiopur =0), with the exception of the five jt ag/swd pins ( pb7 and pc[3:0] ). the jt ag/swd pins default to their jt ag/swd functionality ( gpioafsel =1, gpioden=1 and gpiopur =1). a power-on-reset ( por ) or asserting rst puts both groups of pins back to their default state. caution C if the jt ag pins ar e used as gpios in a design, pb7 and pc2 cannot have external pull-down r esistors connected to both of them at the same time. if both pins ar e pulled low during r eset, the contr oller has unpr edictable behavior . if this happens, r emove one or both of the pull-down r esistors, and apply rst or power-cycle the part. in addition, it is possible to cr eate a softwar e sequence that pr events the debugger fr om connecting to the stellaris ? micr ocontr oller . if the pr ogram code loaded into fash immediately changes the jt ag pins to their gpio functionality , the debugger may not have enough time to connect and halt the contr oller befor e the jt ag pin functionality switches. this may lock the debugger out of the part. this can be avoided with a softwar e r outine that r estor es jt ag functionality based on an external or softwar e trigger . gpio alternate function select (gpioafsel) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0x420 t ype r/w , reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 afsel reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype - - - - - - - - 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 september 02, 2007 180 preliminary general-purpose input/outputs (gpios) description reset t ype name bit/field gpio alternate function select the afsel values are defined as follows: description v alue software control of corresponding gpio line (gpio mode). 0 hardware control of corresponding gpio line (alternate hardware function). 1 note: the default reset value for the gpioafsel , gpiopur , and gpioden registers are 0x0000.0000 for all gpio pins, with the exception of the five jt ag/swd pins ( pb7 and pc[3:0] ). these five pins default to jt ag/swd functionality . because of this, the default reset value of these registers for gpio port b is 0x0000.0080 while the default reset value for port c is 0x0000.000f . - r/w afsel 7:0 181 september 02, 2007 preliminary lm3s8962 microcontroller register 1 1: gpio 2-ma drive select (gpiodr2r), offset 0x500 the gpiodr2r register is the 2-ma drive control register . it allows for each gpio signal in the port to be individually configured without af fecting the other pads. when writing a drv2 bit for a gpio signal, the corresponding drv4 bit in the gpiodr4r register and the drv8 bit in the gpiodr8r register are automatically cleared by hardware. gpio 2-ma drive select (gpiodr2r) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0x500 t ype r/w , reset 0x0000.00ff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 dr v2 reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 output pad 2-ma drive enable a write of 1 to either gpiodr4[n] or gpiodr8[n] clears the corresponding 2-ma enable bit. the change is ef fective on the second clock cycle after the write. 0xff r/w dr v2 7:0 september 02, 2007 182 preliminary general-purpose input/outputs (gpios) register 12: gpio 4-ma drive select (gpiodr4r), offset 0x504 the gpiodr4r register is the 4-ma drive control register . it allows for each gpio signal in the port to be individually configured without af fecting the other pads. when writing the drv4 bit for a gpio signal, the corresponding drv2 bit in the gpiodr2r register and the drv8 bit in the gpiodr8r register are automatically cleared by hardware. gpio 4-ma drive select (gpiodr4r) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0x504 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 dr v4 reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 output pad 4-ma drive enable a write of 1 to either gpiodr2[n] or gpiodr8[n] clears the corresponding 4-ma enable bit. the change is ef fective on the second clock cycle after the write. 0x00 r/w dr v4 7:0 183 september 02, 2007 preliminary lm3s8962 microcontroller register 13: gpio 8-ma drive select (gpiodr8r), offset 0x508 the gpiodr8r register is the 8-ma drive control register . it allows for each gpio signal in the port to be individually configured without af fecting the other pads. when writing the drv8 bit for a gpio signal, the corresponding drv2 bit in the gpiodr2r register and the drv4 bit in the gpiodr4r register are automatically cleared by hardware. gpio 8-ma drive select (gpiodr8r) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0x508 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 dr v8 reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 output pad 8-ma drive enable a write of 1 to either gpiodr2[n] or gpiodr4[n] clears the corresponding 8-ma enable bit. the change is ef fective on the second clock cycle after the write. 0x00 r/w dr v8 7:0 september 02, 2007 184 preliminary general-purpose input/outputs (gpios) register 14: gpio open drain select (gpioodr), offset 0x50c the gpioodr register is the open drain control register . setting a bit in this register enables the open drain configuration of the corresponding gpio pad. when open drain mode is enabled, the corresponding bit should also be set in the gpio digital input enable (gpioden) register (see page 189 ). corresponding bits in the drive strength registers ( gpiodr2r , gpiodr4r , gpiodr8r , and gpioslr ) can be set to achieve the desired rise and fall times. the gpio acts as an open drain input if the corresponding bit in the gpiodir register is set to 0; and as an open drain output when set to 1. when using the i 2 c module, the gpio alternate function select (gpioafsel) register bit for pb2 and pb3 should be set to 1 (see examples in initialization and configuration on page 167 ). gpio open drain select (gpioodr) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0x50c t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ode reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 output pad open drain enable the ode values are defined as follows: description v alue open drain configuration is disabled. 0 open drain configuration is enabled. 1 0x00 r/w ode 7:0 185 september 02, 2007 preliminary lm3s8962 microcontroller register 15: gpio pull-up select (gpiopur), offset 0x510 the gpiopur register is the pull-up control register . when a bit is set to 1, it enables a weak pull-up resistor on the corresponding gpio signal. setting a bit in gpiopur automatically clears the corresponding bit in the gpio pull-down select (gpiopdr) register (see page 187 ). gpio pull-up select (gpiopur) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0x510 t ype r/w , reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pue reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype - - - - - - - - 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 pad w eak pull-up enable a write of 1 to gpiopdr[n] clears the corresponding gpiopur[n] enables. the change is ef fective on the second clock cycle after the write. note: the default reset value for the gpioafsel , gpiopur , and gpioden registers are 0x0000.0000 for all gpio pins, with the exception of the five jt ag/swd pins ( pb7 and pc[3:0] ). these five pins default to jt ag/swd functionality . because of this, the default reset value of these registers for gpio port b is 0x0000.0080 while the default reset value for port c is 0x0000.000f . - r/w pue 7:0 september 02, 2007 186 preliminary general-purpose input/outputs (gpios) register 16: gpio pull-down select (gpiopdr), offset 0x514 the gpiopdr register is the pull-down control register . when a bit is set to 1, it enables a weak pull-down resistor on the corresponding gpio signal. setting a bit in gpiopdr automatically clears the corresponding bit in the gpio pull-up select (gpiopur) register (see page 186 ). gpio pull-down select (gpiopdr) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0x514 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pde reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 pad w eak pull-down enable a write of 1 to gpiopur[n] clears the corresponding gpiopdr[n] enables. the change is ef fective on the second clock cycle after the write. 0x00 r/w pde 7:0 187 september 02, 2007 preliminary lm3s8962 microcontroller register 17: gpio slew rate control select (gpioslr), offset 0x518 the gpioslr register is the slew rate control register . slew rate control is only available when using the 8-ma drive strength option via the gpio 8-ma drive select (gpiodr8r) register (see page 184 ). gpio slew rate control select (gpioslr) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0x518 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 srl reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 slew rate limit enable (8-ma drive only) the srl values are defined as follows: description v alue slew rate control disabled. 0 slew rate control enabled. 1 0x00 r/w srl 7:0 september 02, 2007 188 preliminary general-purpose input/outputs (gpios) register 18: gpio digital enable (gpioden), offset 0x51c the gpioden register is the digital enable register . by default, with the exception of the gpio signals used for jt ag/swd function, all other gpio signals are configured out of reset to be undriven (tristate). their digital function is disabled; they do not drive a logic value on the pin and they do not allow the pin voltage into the gpio receiver . t o use the pin in a digital function (either gpio or alternate function), the corresponding gpioden bit must be set. gpio digital enable (gpioden) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0x51c t ype r/w , reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 den reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype - - - - - - - - 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 digital enable the den values are defined as follows: description v alue digital functions disabled. 0 digital functions enabled. 1 note: the default reset value for the gpioafsel , gpiopur , and gpioden registers are 0x0000.0000 for all gpio pins, with the exception of the five jt ag/swd pins ( pb7 and pc[3:0] ). these five pins default to jt ag/swd functionality . because of this, the default reset value of these registers for gpio port b is 0x0000.0080 while the default reset value for port c is 0x0000.000f . - r/w den 7:0 189 september 02, 2007 preliminary lm3s8962 microcontroller register 19: gpio lock (gpiolock), offset 0x520 the gpiolock register enables write access to the gpiocr register (see page 191 ). w riting 0x1acce551 to the gpiolock register will unlock the gpiocr register . w riting any other value to the gpiolock register re-enables the locked state. reading the gpiolock register returns the lock status rather than the 32-bit value that was previously written. therefore, when write accesses are disabled, or locked, reading the gpiolock register returns 0x00000001. when write accesses are enabled, or unlocked, reading the gpiolock register returns 0x00000000. gpio lock (gpiolock) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0x520 t ype r/w , reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 lock r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 lock r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field gpio lock a write of the value 0x1acce551 unlocks the gpio commit (gpiocr) register for write access. a write of any other value reapplies the lock, preventing any register updates. a read of this register returns the following values: description v alue locked 0x0000.0001 unlocked 0x0000.0000 0x0000.0001 r/w lock 31:0 september 02, 2007 190 preliminary general-purpose input/outputs (gpios) register 20: gpio commit (gpiocr), offset 0x524 the gpiocr register is the commit register . the value of the gpiocr register determines which bits of the gpioafsel register will be committed when a write to the gpioafsel register is performed. if a bit in the gpiocr register is a zero, the data being written to the corresponding bit in the gpioafsel register will not be committed and will retain its previous value. if a bit in the gpiocr register is a one, the data being written to the corresponding bit of the gpioafsel register will be committed to the register and will reflect the new value. the contents of the gpiocr register can only be modified if the gpiolock register is unlocked. w rites to the gpiocr register will be ignored if the gpiolock register is locked. important: this register is designed to prevent accidental programming of the gpioafsel registers that control connectivity to the jt ag/swd debug hardware. by initializing the bits of the gpiocr register to 0 for pb7 and pc[3:0] , the jt ag/swd debug port can only be converted to gpios through a deliberate set of writes to the gpiolock , gpiocr , and gpioafsel registers. because this protection is currently only implemented on the jt ag/swd pins on pb7 and pc[3:0] , all of the other bits in the gpiocr registers cannot be written with 0x0. these bits are hardwired to 0x1, ensuring that it is always possible to commit new values to the gpioafsel register bits of these other pins. gpio commit (gpiocr) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0x524 t ype -, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cr reserved - - - - - - - - ro ro ro ro ro ro ro ro t ype - - - - - - - - 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 191 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field gpio commit on a bit-wise basis, any bit set allows the corresponding gpioafsel bit to be set to its alternate function. note: the default register type for the gpiocr register is ro for all gpio pins, with the exception of the five jt ag/swd pins ( pb7 and pc[3:0] ). these five pins are currently the only gpios that are protected by the gpiocr register . because of this, the register type for gpio port b7 and gpio port c[3:0] is r/w . the default reset value for the gpiocr register is 0x0000.00ff for all gpio pins, with the exception of the five jt ag/swd pins ( pb7 and pc[3:0] ). t o ensure that the jt ag port is not accidentally programmed as a gpio, these five pins default to non-commitable. because of this, the default reset value of gpiocr for gpio port b is 0x0000.007f while the default reset value of gpiocr for port c is 0x0000.00f0. - - cr 7:0 september 02, 2007 192 preliminary general-purpose input/outputs (gpios) register 21: gpio peripheral identification 4 (gpioperiphid4), offset 0xfd0 the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register , used by software to identify the peripheral. gpio peripheral identification 4 (gpioperiphid4) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0xfd0 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid4 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio peripheral id register[7:0] 0x00 ro pid4 7:0 193 september 02, 2007 preliminary lm3s8962 microcontroller register 22: gpio peripheral identification 5 (gpioperiphid5), offset 0xfd4 the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register , used by software to identify the peripheral. gpio peripheral identification 5 (gpioperiphid5) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0xfd4 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid5 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio peripheral id register[15:8] 0x00 ro pid5 7:0 september 02, 2007 194 preliminary general-purpose input/outputs (gpios) register 23: gpio peripheral identification 6 (gpioperiphid6), offset 0xfd8 the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register , used by software to identify the peripheral. gpio peripheral identification 6 (gpioperiphid6) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0xfd8 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid6 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio peripheral id register[23:16] 0x00 ro pid6 7:0 195 september 02, 2007 preliminary lm3s8962 microcontroller register 24: gpio peripheral identification 7 (gpioperiphid7), offset 0xfdc the gpioperiphid4 , gpioperiphid5 , gpioperiphid6 , and gpioperiphid7 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register , used by software to identify the peripheral. gpio peripheral identification 7 (gpioperiphid7) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0xfdc t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid7 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio peripheral id register[31:24] 0x00 ro pid7 7:0 september 02, 2007 196 preliminary general-purpose input/outputs (gpios) register 25: gpio peripheral identification 0 (gpioperiphid0), offset 0xfe0 the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register , used by software to identify the peripheral. gpio peripheral identification 0 (gpioperiphid0) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0xfe0 t ype ro, reset 0x0000.0061 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio peripheral id register[7:0] can be used by software to identify the presence of this peripheral. 0x61 ro pid0 7:0 197 september 02, 2007 preliminary lm3s8962 microcontroller register 26: gpio peripheral identification 1 (gpioperiphid1), offset 0xfe4 the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register , used by software to identify the peripheral. gpio peripheral identification 1 (gpioperiphid1) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0xfe4 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio peripheral id register[15:8] can be used by software to identify the presence of this peripheral. 0x00 ro pid1 7:0 september 02, 2007 198 preliminary general-purpose input/outputs (gpios) register 27: gpio peripheral identification 2 (gpioperiphid2), offset 0xfe8 the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register , used by software to identify the peripheral. gpio peripheral identification 2 (gpioperiphid2) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0xfe8 t ype ro, reset 0x0000.0018 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio peripheral id register[23:16] can be used by software to identify the presence of this peripheral. 0x18 ro pid2 7:0 199 september 02, 2007 preliminary lm3s8962 microcontroller register 28: gpio peripheral identification 3 (gpioperiphid3), offset 0xfec the gpioperiphid0 , gpioperiphid1 , gpioperiphid2 , and gpioperiphid3 registers can conceptually be treated as one 32-bit register; each register contains eight bits of the 32-bit register , used by software to identify the peripheral. gpio peripheral identification 3 (gpioperiphid3) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0xfec t ype ro, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio peripheral id register[31:24] can be used by software to identify the presence of this peripheral. 0x01 ro pid3 7:0 september 02, 2007 200 preliminary general-purpose input/outputs (gpios) register 29: gpio primecell identification 0 (gpiopcellid0), offset 0xff0 the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register . the register is used as a standard cross-peripheral identification system. gpio primecell identification 0 (gpiopcellid0) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0xff0 t ype ro, reset 0x0000.000d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio primecell id register[7:0] provides software a standard cross-peripheral identification system. 0x0d ro cid0 7:0 201 september 02, 2007 preliminary lm3s8962 microcontroller register 30: gpio primecell identification 1 (gpiopcellid1), offset 0xff4 the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register . the register is used as a standard cross-peripheral identification system. gpio primecell identification 1 (gpiopcellid1) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0xff4 t ype ro, reset 0x0000.00f0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio primecell id register[15:8] provides software a standard cross-peripheral identification system. 0xf0 ro cid1 7:0 september 02, 2007 202 preliminary general-purpose input/outputs (gpios) register 31: gpio primecell identification 2 (gpiopcellid2), offset 0xff8 the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register . the register is used as a standard cross-peripheral identification system. gpio primecell identification 2 (gpiopcellid2) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0xff8 t ype ro, reset 0x0000.0005 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio primecell id register[23:16] provides software a standard cross-peripheral identification system. 0x05 ro cid2 7:0 203 september 02, 2007 preliminary lm3s8962 microcontroller register 32: gpio primecell identification 3 (gpiopcellid3), offset 0xffc the gpiopcellid0 , gpiopcellid1 , gpiopcellid2 , and gpiopcellid3 registers are four 8-bit wide registers, that can conceptually be treated as one 32-bit register . the register is used as a standard cross-peripheral identification system. gpio primecell identification 3 (gpiopcellid3) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 of fset 0xffc t ype ro, reset 0x0000.00b1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gpio primecell id register[31:24] provides software a standard cross-peripheral identification system. 0xb1 ro cid3 7:0 september 02, 2007 204 preliminary general-purpose input/outputs (gpios) 10 general-purpose t imers programmable timers can be used to count or time external events that drive the t imer input pins. the stellaris ? general-purpose t imer module (gptm) contains four gptm blocks (t imer0, t imer1, t imer 2, and t imer 3). each gptm block provides two 16-bit timer/counters (referred to as t imera and t imerb) that can be configured to operate independently as timers or event counters, or configured to operate as one 32-bit timer or one 32-bit real-t ime clock (r tc). t imers can also be used to trigger analog-to-digital (adc) conversions. the trigger signals from all of the general-purpose timers are ored together before reaching the adc module, so only one timer should be used to trigger adc events. note: t imer2 is an internal timer and can only be used to generate internal interrupts or trigger adc events. the general-purpose t imer module is one timing resource available on the stellaris ? microcontrollers. other timer resources include the system t imer (syst ick) (see system t imer (syst ick) on page 41 ) and the pwm timer in the pwm module (see pwm t imer on page 507 ). the following modes are supported: 32-bit t imer modes C programmable one-shot timer C programmable periodic timer C real-t ime clock using 32.768-khz input clock C software-controlled event stalling (excluding r tc mode) 16-bit t imer modes C general-purpose timer function with an 8-bit prescaler (for one-shot and periodic modes only) C programmable one-shot timer C programmable periodic timer C software-controlled event stalling 16-bit input capture modes C input edge count capture C input edge time capture 16-bit pwm mode C simple pwm mode with software-programmable output inversion of the pwm signal 205 september 02, 2007 preliminary lm3s8962 microcontroller 10.1 block diagram figure 10-1. gptm module block diagram 10.2 functional description the main components of each gptm block are two free-running 16-bit up/down counters (referred to as t imera and t imerb), two 16-bit match registers, two prescaler match registers, and two 16-bit load/initialization registers and their associated control functions. the exact functionality of each gptm is controlled by software and configured through the register interface. software configures the gptm using the gptm configuration (gptmcfg) register (see page 217 ), the gptm t imera mode (gptmt amr) register (see page 218 ), and the gptm t imerb mode (gptmtbmr) register (see page 220 ). when in one of the 32-bit modes, the timer can only act as a 32-bit timer . however , when configured in 16-bit mode, the gptm can have its two 16-bit timers configured in any combination of the 16-bit modes. 10.2.1 gptm reset conditions after reset has been applied to the gptm module, the module is in an inactive state, and all control registers are cleared and in their default states. counters t imera and t imerb are initialized to 0xffff , along with their corresponding load registers: the gptm t imera interval load (gptmt ailr) register (see page 231 ) and the gptm t imerb interval load (gptmtbilr) register (see page 232 ). the prescale counters are initialized to 0x00: the gptm t imera prescale (gptmt apr) register (see page 235 ) and the gptm t imerb prescale (gptmtbpr) register (see page 236 ). 10.2.2 32-bit t imer operating modes note: both the odd- and even-numbered ccp pins are used for 16-bit mode. only the even-numbered ccp pins are used for 32-bit mode. september 02, 2007 206 preliminary general-purpose t imers t a comparator tb comparator gptmtbr gptmar clock / edge detect r tc divider clock / edge detect t imera interrupt t imerb interrupt system clock 0x0000 (down counter modes) 0x0000 (down counter modes) ccp (even) ccp (odd) en en t imera control gptmt apmr gptmt ailr gptmt ama tchr gptmt apr gptmt amr t imerb control gptmtbpmr gptmtbilr gptmtbma tchr gptmtbpr gptmtbmr interrupt / config gptmcfg gptmris gptmicr gptmmis gptmimr gptmctl this section describes the three gptm 32-bit timer modes (one-shot, periodic, and r tc) and their configuration. the gptm is placed into 32-bit mode by writing a 0 (one-shot/periodic 32-bit timer mode) or a 1 (r tc mode) to the gptm configuration (gptmcfg) register . in both configurations, certain gptm registers are concatenated to form pseudo 32-bit registers. these registers include: gptm t imera interval load (gptmt ailr) register [15:0], see page 231 gptm t imerb interval load (gptmtbilr) register [15:0], see page 232 gptm t imera (gptmt ar) register [15:0], see page 239 gptm t imerb (gptmtbr) register [15:0], see page 240 in the 32-bit modes, the gptm translates a 32-bit write access to gptmt ailr into a write access to both gptmt ailr and gptmtbilr . the resulting word ordering for such a write operation is: gptmtbilr[15:0]:gptmtailr[15:0] likewise, a read access to gptmt ar returns the value: gptmtbr[15:0]:gptmtar[15:0] 10.2.2.1 32-bit one-shot/periodic t imer mode in 32-bit one-shot and periodic timer modes, the concatenated versions of the t imera and t imerb registers are configured as a 32-bit down-counter . the selection of one-shot or periodic mode is determined by the value written to the tamr field of the gptm t imera mode (gptmt amr) register (see page 218 ), and there is no need to write to the gptm t imerb mode (gptmtbmr) register . when software writes the taen bit in the gptm control (gptmctl) register (see page 222 ), the timer begins counting down from its preloaded value. once the 0x0000.0000 state is reached, the timer reloads its start value from the concatenated gptmt ailr on the next cycle. if configured to be a one-shot timer , the timer stops counting and clears the taen bit in the gptmctl register . if configured as a periodic timer , it continues counting. in addition to reloading the count value, the gptm generates interrupts and output triggers when it reaches the 0x0000000 state. the gptm sets the tatoris bit in the gptm raw interrupt status (gptmris) register (see page 227 ), and holds it until it is cleared by writing the gptm interrupt clear (gptmicr) register (see page 229 ). if the time-out interrupt is enabled in the gptm interrupt mask (gptimr) register (see page 225 ), the gptm also sets the tatomis bit in the gptm masked interrupt status (gptmmis) register (see page 228 ). the output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000.0000 state, and deasserted on the following clock cycle. it is enabled by setting the taote bit in gptmctl , and can trigger soc-level events such as adc conversions. if software reloads the gptmt ailr register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. if the tastall bit in the gptmctl register is asserted, the timer freezes counting until the signal is deasserted. 10.2.2.2 32-bit real-t ime clock t imer mode in real-t ime clock (r tc) mode, the concatenated versions of the t imera and t imerb registers are configured as a 32-bit up-counter . when r tc mode is selected for the first time, the counter is 207 september 02, 2007 preliminary lm3s8962 microcontroller loaded with a value of 0x0000.0001. all subsequent load values must be written to the gptm t imera match (gptmt ama tchr) register (see page 233 ) by the controller . the input clock on the ccp0 , ccp2 , or ccp4 pins is required to be 32.768 khz in r tc mode. the clock signal is then divided down to a 1 hz rate and is passed along to the input of the 32-bit counter . when software writes the taen bit inthe gptmctl register , the counter starts counting up from its preloaded value of 0x0000.0001. when the current count value matches the preloaded value in the gptmt ama tchr register , it rolls over to a value of 0x0000.0000 and continues counting until either a hardware reset, or it is disabled by software (clearing the taen bit). when a match occurs, the gptm asserts the rtcris bit in gptmris . if the r tc interrupt is enabled in gptimr , the gptm also sets the rtcmis bit in gptmisr and generates a controller interrupt. the status flags are cleared by writing the rtccint bit in gptmicr . if the tastall and/or tbstall bits in the gptmctl register are set, the timer does not freeze if the rtcen bit is set in gptmctl . 10.2.3 16-bit t imer operating modes the gptm is placed into global 16-bit mode by writing a value of 0x4 to the gptm configuration (gptmcfg) register (see page 217 ). this section describes each of the gptm 16-bit modes of operation. t imera and t imerb have identical modes, so a single description is given using an n to reference both. 10.2.3.1 16-bit one-shot/periodic t imer mode in 16-bit one-shot and periodic timer modes, the timer is configured as a 16-bit down-counter with an optional 8-bit prescaler that ef fectively extends the counting range of the timer to 24 bits. the selection of one-shot or periodic mode is determined by the value written to the tnmr field of the gptmtnmr register . the optional prescaler is loaded into the gptm t imern prescale (gptmtnpr) register . when software writes the tnen bit in the gptmctl register , the timer begins counting down from its preloaded value. once the 0x0000 state is reached, the timer reloads its start value from gptmtnilr and gptmtnpr on the next cycle. if configured to be a one-shot timer , the timer stops counting and clears the tnen bit in the gptmctl register . if configured as a periodic timer , it continues counting. in addition to reloading the count value, the timer generates interrupts and output triggers when it reaches the 0x0000 state. the gptm sets the tntoris bit in the gptmris register , and holds it until it is cleared by writing the gptmicr register . if the time-out interrupt is enabled in gptimr , the gptm also sets the tntomis bit in gptmisr and generates a controller interrupt. the output trigger is a one-clock-cycle pulse that is asserted when the counter hits the 0x0000 state, and deasserted on the following clock cycle. it is enabled by setting the tnote bit in the gptmctl register , and can trigger soc-level events such as adc conversions. if software reloads the gptmt ailr register while the counter is running, the counter loads the new value on the next clock cycle and continues counting from the new value. if the tnstall bit in the gptmctl register is enabled, the timer freezes counting until the signal is deasserted. the following example shows a variety of configurations for a 16-bit free running timer while using the prescaler . all values assume a 50-mhz clock with t c=20 ns (clock period). september 02, 2007 208 preliminary general-purpose t imers t able 10-1. 16-bit t imer w ith prescaler configurations units max t ime #clock (t c) a prescale ms 1.3107 1 00000000 ms 2.6214 2 00000001 ms 3.9321 3 00000010 -- -- -- ------------ ms 332.9229 254 1 1 1 1 1 100 ms 334.2336 255 1 1 1 1 1 1 10 ms 335.5443 256 1 1 1 1 1 1 1 1 a. t c is the clock period. 10.2.3.2 16-bit input edge count mode in edge count mode, the timer is configured as a down-counter capable of capturing three types of events: rising edge, falling edge, or both. t o place the timer in edge count mode, the tncmr bit of the gptmtnmr register must be set to 0. the type of edge that the timer counts is determined by the tnevent fields of the gptmctl register . during initialization, the gptm t imern match (gptmtnma tchr) register is configured so that the dif ference between the value in the gptmtnilr register and the gptmtnma tchr register equals the number of edge events that must be counted. when software writes the tnen bit in the gptm control (gptmctl) register , the timer is enabled for event capture. each input event on the ccp pin decrements the counter by 1 until the event count matches gptmtnma tchr . when the counts match, the gptm asserts the cnmris bit in the gptmris register (and the cnmmis bit, if the interrupt is not masked). the counter is then reloaded using the value in gptmtnilr , and stopped since the gptm automatically clears the tnen bit in the gptmctl register . once the event count has been reached, all further events are ignored until tnen is re-enabled by software. figure 10-2 on page 210 shows how input edge count mode works. in this case, the timer start value is set to gptmnilr =0x000a and the match value is set to gptmnma tchr =0x0006 so that four edge events are counted. the counter is configured to detect both edges of the input signal. note that the last two edges are not counted since the timer automatically clears the tnen bit after the current count matches the value in the gptmnmr register . 209 september 02, 2007 preliminary lm3s8962 microcontroller figure 10-2. 16-bit input edge count mode example 10.2.3.3 16-bit input edge t ime mode note: the prescaler is not available in 16-bit input edge t ime mode. in edge t ime mode, the timer is configured as a free-running down-counter initialized to the value loaded in the gptmtnilr register (or 0xffff at reset). this mode allows for event capture of both rising and falling edges. the timer is placed into edge t ime mode by setting the tncmr bit in the gptmtnmr register , and the type of event that the timer captures is determined by the tnevent fields of the gptmcntl register . when software writes the tnen bit in the gptmctl register , the timer is enabled for event capture. when the selected input event is detected, the current tn counter value is captured in the gptmtnr register and is available to be read by the controller . the gptm then asserts the cneris bit (and the cnemis bit, if the interrupt is not masked). after an event has been captured, the timer does not stop counting. it continues to count until the tnen bit is cleared. when the timer reaches the 0x0000 state, it is reloaded with the value from the gptmnilr register . figure 10-3 on page 211 shows how input edge timing mode works. in the diagram, it is assumed that the start value of the timer is the default value of 0xffff , and the timer is configured to capture rising edge events. each time a rising edge event is detected, the current count value is loaded into the gptmtnr register , and is held there until another rising edge is detected (at which point the new count value is loaded into gptmtnr ). september 02, 2007 210 preliminary general-purpose t imers 0x000a 0x0006 0x0007 0x0008 0x0009 input signal t imer stops, flags asserted t imer reload on next cycle ignored ignored count figure 10-3. 16-bit input edge t ime mode example 10.2.3.4 16-bit pwm mode the gptm supports a simple pwm generation mode. in pwm mode, the timer is configured as a down-counter with a start value (and thus period) defined by gptmtnilr . pwm mode is enabled with the gptmtnmr register by setting the tnams bit to 0x1, the tncmr bit to 0x0, and the tnmr field to 0x2. when software writes the tnen bit in the gptmctl register , the counter begins counting down until it reaches the 0x0000 state. on the next counter cycle, the counter reloads its start value from gptmtnilr (and gptmtnpr if using a prescaler) and continues counting until disabled by software clearing the tnen bit in the gptmctl register . no interrupts or status bits are asserted in pwm mode. the output pwm signal asserts when the counter is at the value of the gptmtnilr register (its start state), and is deasserted when the counter value equals the value in the gptm t imern match register (gptmnma tchr) . software has the capability of inverting the output pwm signal by setting the tnpwml bit in the gptmctl register . figure 10-4 on page 212 shows how to generate an output pwm with a 1-ms period and a 66% duty cycle assuming a 50-mhz input clock and tnpwml =0 (duty cycle would be 33% for the tnpwml =1 configuration). for this example, the start value is gptmnirl =0xc350 and the match value is gptmnmr =0x41 1a. 21 1 september 02, 2007 preliminary lm3s8962 microcontroller gptmtnr=y input signal t ime count gptmtnr=x gptmtnr=z z x y 0xffff figure 10-4. 16-bit pwm mode example 10.3 initialization and configuration t o use the general-purpose timers, the peripheral clock must be enabled by setting the timer0 , timer1 , timer2 , and timer3 bits in the rcgc1 register . this section shows module initialization and configuration examples for each of the supported timer modes. 10.3.1 32-bit one-shot/periodic t imer mode the gptm is configured for 32-bit one-shot and periodic modes by the following sequence: 1. ensure the timer is disabled (the taen bit in the gptmctl register is cleared) before making any changes. 2. w rite the gptm configuration register (gptmcfg) with a value of 0x0. 3. set the tamr field in the gptm t imera mode register (gptmt amr) : a. w rite a value of 0x1 for one-shot mode. b. w rite a value of 0x2 for periodic mode. 4. load the start value into the gptm t imera interval load register (gptmt ailr) . 5. if interrupts are required, set the tatoim bit in the gptm interrupt mask register (gptmimr) . 6. set the taen bit in the gptmctl register to enable the timer and start counting. september 02, 2007 212 preliminary general-purpose t imers output signal t ime count gptmtnr=gptmnmr gptmtnr=gptmnmr 0xc350 0x41 1a tnpwml = 0 tnpwml = 1 tnen set 7. poll the tatoris bit in the gptmris register or wait for the interrupt to be generated (if enabled). in both cases, the status flags are cleared by writing a 1 to the tatocint bit of the gptm interrupt clear register (gptmicr) . in one-shot mode, the timer stops counting after step 7 on page 213 . t o re-enable the timer , repeat the sequence. a timer configured in periodic mode does not stop counting after it times out. 10.3.2 32-bit real-t ime clock (rtc) mode t o use the r tc mode, the timer must have a 32.768-khz input signal on its ccp0 , ccp2 , or ccp4 pins. t o enable the r tc feature, follow these steps: 1. ensure the timer is disabled (the taen bit is cleared) before making any changes. 2. w rite the gptm configuration register (gptmcfg) with a value of 0x1. 3. w rite the desired match value to the gptm t imera match register (gptmt ama tchr) . 4. set/clear the rtcen bit in the gptm control register (gptmctl) as desired. 5. if interrupts are required, set the rtcim bit in the gptm interrupt mask register (gptmimr) . 6. set the taen bit in the gptmctl register to enable the timer and start counting. when the timer count equals the value in the gptmt ama tchr register , the counter is re-loaded with 0x0000.0000 and begins counting. if an interrupt is enabled, it does not have to be cleared. 10.3.3 16-bit one-shot/periodic t imer mode a timer is configured for 16-bit one-shot and periodic modes by the following sequence: 1. ensure the timer is disabled (the tnen bit is cleared) before making any changes. 2. w rite the gptm configuration register (gptmcfg) with a value of 0x4. 3. set the tnmr field in the gptm t imer mode (gptmtnmr) register: a. w rite a value of 0x1 for one-shot mode. b. w rite a value of 0x2 for periodic mode. 4. if a prescaler is to be used, write the prescale value to the gptm t imern prescale register (gptmtnpr) . 5. load the start value into the gptm t imer interval load register (gptmtnilr) . 6. if interrupts are required, set the tntoim bit in the gptm interrupt mask register (gptmimr) . 7. set the tnen bit in the gptm control register (gptmctl) to enable the timer and start counting. 8. poll the tntoris bit in the gptmris register or wait for the interrupt to be generated (if enabled). in both cases, the status flags are cleared by writing a 1 to the tntocint bit of the gptm interrupt clear register (gptmicr) . 213 september 02, 2007 preliminary lm3s8962 microcontroller in one-shot mode, the timer stops counting after step 8 on page 213 . t o re-enable the timer , repeat the sequence. a timer configured in periodic mode does not stop counting after it times out. 10.3.4 16-bit input edge count mode a timer is configured to input edge count mode by the following sequence: 1. ensure the timer is disabled (the tnen bit is cleared) before making any changes. 2. w rite the gptm configuration (gptmcfg) register with a value of 0x4. 3. in the gptm t imer mode (gptmtnmr) register , write the tncmr field to 0x0 and the tnmr field to 0x3. 4. configure the type of event(s) that the timer captures by writing the tnevent field of the gptm control (gptmctl) register . 5. load the timer start value into the gptm t imern interval load (gptmtnilr) register . 6. load the desired event count into the gptm t imern match (gptmtnma tchr) register . 7. if interrupts are required, set the cnmim bit in the gptm interrupt mask (gptmimr) register . 8. set the tnen bit in the gptmctl register to enable the timer and begin waiting for edge events. 9. poll the cnmris bit in the gptmris register or wait for the interrupt to be generated (if enabled). in both cases, the status flags are cleared by writing a 1 to the cnmcint bit of the gptm interrupt clear (gptmicr) register . in input edge count mode, the timer stops after the desired number of edge events has been detected. t o re-enable the timer , ensure that the tnen bit is cleared and repeat step 4 on page 214 - step 9 on page 214 . 10.3.5 16-bit input edge t iming mode a timer is configured to input edge t iming mode by the following sequence: 1. ensure the timer is disabled (the tnen bit is cleared) before making any changes. 2. w rite the gptm configuration (gptmcfg) register with a value of 0x4. 3. in the gptm t imer mode (gptmtnmr) register , write the tncmr field to 0x1 and the tnmr field to 0x3. 4. configure the type of event that the timer captures by writing the tnevent field of the gptm control (gptmctl) register . 5. load the timer start value into the gptm t imern interval load (gptmtnilr) register . 6. if interrupts are required, set the cneim bit in the gptm interrupt mask (gptmimr) register . 7. set the tnen bit in the gptm control (gptmctl) register to enable the timer and start counting. 8. poll the cneris bit in the gptmris register or wait for the interrupt to be generated (if enabled). in both cases, the status flags are cleared by writing a 1 to the cnecint bit of the gptm september 02, 2007 214 preliminary general-purpose t imers interrupt clear (gptmicr) register . the time at which the event happened can be obtained by reading the gptm t imern (gptmtnr) register . in input edge t iming mode, the timer continues running after an edge event has been detected, but the timer interval can be changed at any time by writing the gptmtnilr register . the change takes ef fect at the next cycle after the write. 10.3.6 16-bit pwm mode a timer is configured to pwm mode using the following sequence: 1. ensure the timer is disabled (the tnen bit is cleared) before making any changes. 2. w rite the gptm configuration (gptmcfg) register with a value of 0x4. 3. in the gptm t imer mode (gptmtnmr) register , set the tnams bit to 0x1, the tncmr bit to 0x0, and the tnmr field to 0x2. 4. configure the output state of the pwm signal (whether or not it is inverted) in the tnevent field of the gptm control (gptmctl) register . 5. load the timer start value into the gptm t imern interval load (gptmtnilr) register . 6. load the gptm t imern match (gptmtnma tchr) register with the desired value. 7. if a prescaler is going to be used, configure the gptm t imern prescale (gptmtnpr) register and the gptm t imern prescale match (gptmtnpmr) register . 8. set the tnen bit in the gptm control (gptmctl) register to enable the timer and begin generation of the output pwm signal. in pwm t iming mode, the timer continues running after the pwm signal has been generated. the pwm period can be adjusted at any time by writing the gptmtnilr register , and the change takes ef fect at the next cycle after the write. 10.4 register map t able 10-2 on page 215 lists the gptm registers. the of fset listed is a hexadecimal increment to the register s address, relative to that timer s base address: t imer0: 0x4003.0000 t imer1: 0x4003.1000 t imer2: 0x4003.2000 t imer3: 0x4003.3000 t able 10-2. t imers register map see page description reset t ype name offset 217 gptm configuration 0x0000.0000 r/w gptmcfg 0x000 218 gptm t imera mode 0x0000.0000 r/w gptmt amr 0x004 215 september 02, 2007 preliminary lm3s8962 microcontroller see page description reset t ype name offset 220 gptm t imerb mode 0x0000.0000 r/w gptmtbmr 0x008 222 gptm control 0x0000.0000 r/w gptmctl 0x00c 225 gptm interrupt mask 0x0000.0000 r/w gptmimr 0x018 227 gptm raw interrupt status 0x0000.0000 ro gptmris 0x01c 228 gptm masked interrupt status 0x0000.0000 ro gptmmis 0x020 229 gptm interrupt clear 0x0000.0000 w1c gptmicr 0x024 231 gptm t imera interval load 0x0000.ffff (16-bit mode) 0xffff .ffff (32-bit mode) r/w gptmt ailr 0x028 232 gptm t imerb interval load 0x0000.ffff r/w gptmtbilr 0x02c 233 gptm t imera match 0x0000.ffff (16-bit mode) 0xffff .ffff (32-bit mode) r/w gptmt ama tchr 0x030 234 gptm t imerb match 0x0000.ffff r/w gptmtbma tchr 0x034 235 gptm t imera prescale 0x0000.0000 r/w gptmt apr 0x038 236 gptm t imerb prescale 0x0000.0000 r/w gptmtbpr 0x03c 237 gptm t imera prescale match 0x0000.0000 r/w gptmt apmr 0x040 238 gptm t imerb prescale match 0x0000.0000 r/w gptmtbpmr 0x044 239 gptm t imera 0x0000.ffff (16-bit mode) 0xffff .ffff (32-bit mode) ro gptmt ar 0x048 240 gptm t imerb 0x0000.ffff ro gptmtbr 0x04c 10.5 register descriptions the remainder of this section lists and describes the gptm registers, in numerical order by address of fset. september 02, 2007 216 preliminary general-purpose t imers register 1: gptm configuration (gptmcfg), offset 0x000 this register configures the global operation of the gptm module. the value written to this register determines whether the gptm is in 32- or 16-bit mode. gptm configuration (gptmcfg) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 t imer3 base: 0x4003.3000 of fset 0x000 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 gptmcfg reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:3 gptm configuration the gptmcfg values are defined as follows: description v alue 32-bit timer configuration. 0x0 32-bit real-time clock (r tc) counter configuration. 0x1 reserved. 0x2 reserved. 0x3 16-bit timer configuration, function is controlled by bits 1:0 of gptmt amr and gptmtbmr . 0x4-0x7 0x0 r/w gptmcfg 2:0 217 september 02, 2007 preliminary lm3s8962 microcontroller register 2: gptm t imera mode (gptmt amr), offset 0x004 this register configures the gptm based on the configuration selected in the gptmcfg register . when in 16-bit pwm mode, set the taams bit to 0x1, the tacmr bit to 0x0, and the tamr field to 0x2. gptm t imera mode (gptmt amr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 t imer3 base: 0x4003.3000 of fset 0x004 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t amr t acmr t aams reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:4 gptm t imera alternate mode select the taams values are defined as follows: description v alue capture mode is enabled. 0 pwm mode is enabled. 1 note: t o enable pwm mode, you must also clear the tacmr bit and set the tamr field to 0x2. 0 r/w t aams 3 gptm t imera capture mode the tacmr values are defined as follows: description v alue edge-count mode. 0 edge-t ime mode. 1 0 r/w t acmr 2 september 02, 2007 218 preliminary general-purpose t imers description reset t ype name bit/field gptm t imera mode the tamr values are defined as follows: description v alue reserved. 0x0 one-shot t imer mode. 0x1 periodic t imer mode. 0x2 capture mode. 0x3 the t imer mode is based on the timer configuration defined by bits 2:0 in the gptmcfg register (16-or 32-bit). in 16-bit timer configuration, tamr controls the 16-bit timer modes for t imera. in 32-bit timer configuration, this register controls the mode and the contents of gptmtbmr are ignored. 0x0 r/w t amr 1:0 219 september 02, 2007 preliminary lm3s8962 microcontroller register 3: gptm t imerb mode (gptmtbmr), offset 0x008 this register configures the gptm based on the configuration selected in the gptmcfg register . when in 16-bit pwm mode, set the tbams bit to 0x1, the tbcmr bit to 0x0, and the tbmr field to 0x2. gptm t imerb mode (gptmtbmr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 t imer3 base: 0x4003.3000 of fset 0x008 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 tbmr tbcmr tbams reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:4 gptm t imerb alternate mode select the tbams values are defined as follows: description v alue capture mode is enabled. 0 pwm mode is enabled. 1 note: t o enable pwm mode, you must also clear the tbcmr bit and set the tbmr field to 0x2. 0 r/w tbams 3 gptm t imerb capture mode the tbcmr values are defined as follows: description v alue edge-count mode. 0 edge-t ime mode. 1 0 r/w tbcmr 2 september 02, 2007 220 preliminary general-purpose t imers description reset t ype name bit/field gptm t imerb mode the tbmr values are defined as follows: description v alue reserved. 0x0 one-shot t imer mode. 0x1 periodic t imer mode. 0x2 capture mode. 0x3 the timer mode is based on the timer configuration defined by bits 2:0 in the gptmcfg register . in 16-bit timer configuration, these bits control the 16-bit timer modes for t imerb. in 32-bit timer configuration, this register s contents are ignored and gptmt amr is used. 0x0 r/w tbmr 1:0 221 september 02, 2007 preliminary lm3s8962 microcontroller register 4: gptm control (gptmctl), offset 0x00c this register is used alongside the gptmcfg and gmtmtnmr registers to fine-tune the timer configuration, and to enable other features such as timer stall and the output trigger . the output trigger can be used to initiate transfers on the adc module. gptm control (gptmctl) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 t imer3 base: 0x4003.3000 of fset 0x00c t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t aen t ast all t aevent r tcen t aote t apwml reserved tben tbst all tbevent reserved tbote tbpwml reserved r/w r/w r/w r/w r/w r/w r/w ro r/w r/w r/w r/w ro r/w r/w ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:15 gptm t imerb pwm output level the tbpwml values are defined as follows: description v alue output is unaf fected. 0 output is inverted. 1 0 r/w tbpwml 14 gptm t imerb output t rigger enable the tbote values are defined as follows: description v alue the output t imerb trigger is disabled. 0 the output t imerb trigger is enabled. 1 0 r/w tbote 13 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12 september 02, 2007 222 preliminary general-purpose t imers description reset t ype name bit/field gptm t imerb event mode the tbevent values are defined as follows: description v alue positive edge. 0x0 negative edge. 0x1 reserved 0x2 both edges. 0x3 0x0 r/w tbevent 1 1:10 gptm t imerb stall enable the tbstall values are defined as follows: description v alue t imerb stalling is disabled. 0 t imerb stalling is enabled. 1 0 r/w tbst all 9 gptm t imerb enable the tben values are defined as follows: description v alue t imerb is disabled. 0 t imerb is enabled and begins counting or the capture logic is enabled based on the gptmcfg register . 1 0 r/w tben 8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7 gptm t imera pwm output level the tapwml values are defined as follows: description v alue output is unaf fected. 0 output is inverted. 1 0 r/w t apwml 6 gptm t imera output t rigger enable the taote values are defined as follows: description v alue the output t imera trigger is disabled. 0 the output t imera trigger is enabled. 1 0 r/w t aote 5 223 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field gptm r tc enable the rtcen values are defined as follows: description v alue r tc counting is disabled. 0 r tc counting is enabled. 1 0 r/w r tcen 4 gptm t imera event mode the taevent values are defined as follows: description v alue positive edge. 0x0 negative edge. 0x1 reserved 0x2 both edges. 0x3 0x0 r/w t aevent 3:2 gptm t imera stall enable the tastall values are defined as follows: description v alue t imera stalling is disabled. 0 t imera stalling is enabled. 1 0 r/w t ast all 1 gptm t imera enable the taen values are defined as follows: description v alue t imera is disabled. 0 t imera is enabled and begins counting or the capture logic is enabled based on the gptmcfg register . 1 0 r/w t aen 0 september 02, 2007 224 preliminary general-purpose t imers register 5: gptm interrupt mask (gptmimr), offset 0x018 this register allows software to enable/disable gptm controller-level interrupts. w riting a 1 enables the interrupt, while writing a 0 disables it. gptm interrupt mask (gptmimr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 t imer3 base: 0x4003.3000 of fset 0x018 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t a t oim camim caeim r tcim reserved tbt oim cbmim cbeim reserved r/w r/w r/w r/w ro ro ro ro r/w r/w r/w ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 1 gptm captureb event interrupt mask the cbeim values are defined as follows: description v alue interrupt is disabled. 0 interrupt is enabled. 1 0 r/w cbeim 10 gptm captureb match interrupt mask the cbmim values are defined as follows: description v alue interrupt is disabled. 0 interrupt is enabled. 1 0 r/w cbmim 9 gptm t imerb t ime-out interrupt mask the tbtoim values are defined as follows: description v alue interrupt is disabled. 0 interrupt is enabled. 1 0 r/w tbt oim 8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:4 225 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field gptm r tc interrupt mask the rtcim values are defined as follows: description v alue interrupt is disabled. 0 interrupt is enabled. 1 0 r/w r tcim 3 gptm capturea event interrupt mask the caeim values are defined as follows: description v alue interrupt is disabled. 0 interrupt is enabled. 1 0 r/w caeim 2 gptm capturea match interrupt mask the camim values are defined as follows: description v alue interrupt is disabled. 0 interrupt is enabled. 1 0 r/w camim 1 gptm t imera t ime-out interrupt mask the tatoim values are defined as follows: description v alue interrupt is disabled. 0 interrupt is enabled. 1 0 r/w t a t oim 0 september 02, 2007 226 preliminary general-purpose t imers register 6: gptm raw interrupt status (gptmris), offset 0x01c this register shows the state of the gptm's internal interrupt signal. these bits are set whether or not the interrupt is masked in the gptmimr register . each bit can be cleared by writing a 1 to its corresponding bit in gptmicr . gptm raw interrupt status (gptmris) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 t imer3 base: 0x4003.3000 of fset 0x01c t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t a t oris camris caeris r tcris reserved tbt oris cbmris cberis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 1 gptm captureb event raw interrupt this is the captureb event interrupt status prior to masking. 0 ro cberis 10 gptm captureb match raw interrupt this is the captureb match interrupt status prior to masking. 0 ro cbmris 9 gptm t imerb t ime-out raw interrupt this is the t imerb time-out interrupt status prior to masking. 0 ro tbt oris 8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:4 gptm r tc raw interrupt this is the r tc event interrupt status prior to masking. 0 ro r tcris 3 gptm capturea event raw interrupt this is the capturea event interrupt status prior to masking. 0 ro caeris 2 gptm capturea match raw interrupt this is the capturea match interrupt status prior to masking. 0 ro camris 1 gptm t imera t ime-out raw interrupt this the t imera time-out interrupt status prior to masking. 0 ro t a t oris 0 227 september 02, 2007 preliminary lm3s8962 microcontroller register 7: gptm masked interrupt status (gptmmis), offset 0x020 this register show the state of the gptm's controller-level interrupt. if an interrupt is unmasked in gptmimr , and there is an event that causes the interrupt to be asserted, the corresponding bit is set in this register . all bits are cleared by writing a 1 to the corresponding bit in gptmicr . gptm masked interrupt status (gptmmis) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 t imer3 base: 0x4003.3000 of fset 0x020 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t a t omis cammis caemis r tcmis reserved tbt omis cbmmis cbemis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 1 gptm captureb event masked interrupt this is the captureb event interrupt status after masking. 0 ro cbemis 10 gptm captureb match masked interrupt this is the captureb match interrupt status after masking. 0 ro cbmmis 9 gptm t imerb t ime-out masked interrupt this is the t imerb time-out interrupt status after masking. 0 ro tbt omis 8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:4 gptm r tc masked interrupt this is the r tc event interrupt status after masking. 0 ro r tcmis 3 gptm capturea event masked interrupt this is the capturea event interrupt status after masking. 0 ro caemis 2 gptm capturea match masked interrupt this is the capturea match interrupt status after masking. 0 ro cammis 1 gptm t imera t ime-out masked interrupt this is the t imera time-out interrupt status after masking. 0 ro t a t omis 0 september 02, 2007 228 preliminary general-purpose t imers register 8: gptm interrupt clear (gptmicr), offset 0x024 this register is used to clear the status bits in the gptmris and gptmmis registers. w riting a 1 to a bit clears the corresponding bit in the gptmris and gptmmis registers. gptm interrupt clear (gptmicr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 t imer3 base: 0x4003.3000 of fset 0x024 t ype w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t a t ocint camcint caecint r tccint reserved tbt ocint cbmcint cbecint reserved w1c w1c w1c w1c ro ro ro ro w1c w1c w1c ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 1 gptm captureb event interrupt clear the cbecint values are defined as follows: description v alue the interrupt is unaf fected. 0 the interrupt is cleared. 1 0 w1c cbecint 10 gptm captureb match interrupt clear the cbmcint values are defined as follows: description v alue the interrupt is unaf fected. 0 the interrupt is cleared. 1 0 w1c cbmcint 9 gptm t imerb t ime-out interrupt clear the tbtocint values are defined as follows: description v alue the interrupt is unaf fected. 0 the interrupt is cleared. 1 0 w1c tbt ocint 8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:4 229 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field gptm r tc interrupt clear the rtccint values are defined as follows: description v alue the interrupt is unaf fected. 0 the interrupt is cleared. 1 0 w1c r tccint 3 gptm capturea event interrupt clear the caecint values are defined as follows: description v alue the interrupt is unaf fected. 0 the interrupt is cleared. 1 0 w1c caecint 2 gptm capturea match raw interrupt this is the capturea match interrupt status after masking. 0 w1c camcint 1 gptm t imera t ime-out raw interrupt the tatocint values are defined as follows: description v alue the interrupt is unaf fected. 0 the interrupt is cleared. 1 0 w1c t a t ocint 0 september 02, 2007 230 preliminary general-purpose t imers register 9: gptm t imera interval load (gptmt ailr), offset 0x028 this register is used to load the starting count value into the timer . when gptm is configured to one of the 32-bit modes, gptmt ailr appears as a 32-bit register (the upper 16-bits correspond to the contents of the gptm t imerb interval load (gptmtbilr) register). in 16-bit mode, the upper 16 bits of this register read as 0s and have no ef fect on the state of gptmtbilr . gptm t imera interval load (gptmt ailr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 t imer3 base: 0x4003.3000 of fset 0x028 t ype r/w , reset 0x0000.ffff (16-bit mode) and 0xffff .ffff (32-bit mode) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 t ailrh r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 1 1 1 1 0 1 1 1 1 0 1 0 1 1 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t ailrl r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field gptm t imera interval load register high when configured for 32-bit mode via the gptmcfg register , the gptm t imerb interval load (gptmtbilr) register loads this value on a write. a read returns the current value of gptmtbilr . in 16-bit mode, this field reads as 0 and does not have an ef fect on the state of gptmtbilr . 0xffff (32-bit mode) 0x0000 (16-bit mode) r/w t ailrh 31:16 gptm t imera interval load register low for both 16- and 32-bit modes, writing this field loads the counter for t imera. a read returns the current value of gptmt ailr . 0xffff r/w t ailrl 15:0 231 september 02, 2007 preliminary lm3s8962 microcontroller register 10: gptm t imerb interval load (gptmtbilr), offset 0x02c this register is used to load the starting count value into t imerb. when the gptm is configured to a 32-bit mode, gptmtbilr returns the current value of t imerb and ignores writes. gptm t imerb interval load (gptmtbilr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 t imer3 base: 0x4003.3000 of fset 0x02c t ype r/w , reset 0x0000.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 tbilrl r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 gptm t imerb interval load register when the gptm is not configured as a 32-bit timer , a write to this field updates gptmtbilr . in 32-bit mode, writes are ignored, and reads return the current value of gptmtbilr . 0xffff r/w tbilrl 15:0 september 02, 2007 232 preliminary general-purpose t imers register 1 1: gptm t imera match (gptmt ama tchr), offset 0x030 this register is used in 32-bit real-t ime clock mode and 16-bit pwm and input edge count modes. gptm t imera match (gptmt ama tchr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 t imer3 base: 0x4003.3000 of fset 0x030 t ype r/w , reset 0x0000.ffff (16-bit mode) and 0xffff .ffff (32-bit mode) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 t amrh r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 1 1 1 1 0 1 1 1 1 0 1 0 1 1 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t amrl r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field gptm t imera match register high when configured for 32-bit real-t ime clock (r tc) mode via the gptmcfg register , this value is compared to the upper half of gptmt ar , to determine match events. in 16-bit mode, this field reads as 0 and does not have an ef fect on the state of gptmtbma tchr . 0xffff (32-bit mode) 0x0000 (16-bit mode) r/w t amrh 31:16 gptm t imera match register low when configured for 32-bit real-t ime clock (r tc) mode via the gptmcfg register , this value is compared to the lower half of gptmt ar , to determine match events. when configured for pwm mode, this value along with gptmt ailr , determines the duty cycle of the output pwm signal. when configured for edge count mode, this value along with gptmt ailr , determines how many edge events are counted. the total number of edge events counted is equal to the value in gptmt ailr minus this value. 0xffff r/w t amrl 15:0 233 september 02, 2007 preliminary lm3s8962 microcontroller register 12: gptm t imerb match (gptmtbma tchr), offset 0x034 this register is used in 32-bit real-t ime clock mode and 16-bit pwm and input edge count modes. gptm t imerb match (gptmtbma tchr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 t imer3 base: 0x4003.3000 of fset 0x034 t ype r/w , reset 0x0000.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 tbmrl r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 gptm t imerb match register low when configured for pwm mode, this value along with gptmtbilr , determines the duty cycle of the output pwm signal. when configured for edge count mode, this value along with gptmtbilr , determines how many edge events are counted. the total number of edge events counted is equal to the value in gptmtbilr minus this value. 0xffff r/w tbmrl 15:0 september 02, 2007 234 preliminary general-purpose t imers register 13: gptm t imera prescale (gptmt apr), offset 0x038 this register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. gptm t imera prescale (gptmt apr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 t imer3 base: 0x4003.3000 of fset 0x038 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t apsr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gptm t imera prescale the register loads this value on a write. a read returns the current value of the register . refer to t able 10-1 on page 209 for more details and an example. 0x00 r/w t apsr 7:0 235 september 02, 2007 preliminary lm3s8962 microcontroller register 14: gptm t imerb prescale (gptmtbpr), offset 0x03c this register allows software to extend the range of the 16-bit timers when operating in one-shot or periodic mode. gptm t imerb prescale (gptmtbpr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 t imer3 base: 0x4003.3000 of fset 0x03c t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 tbpsr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gptm t imerb prescale the register loads this value on a write. a read returns the current value of this register . refer to t able 10-1 on page 209 for more details and an example. 0x00 r/w tbpsr 7:0 september 02, 2007 236 preliminary general-purpose t imers register 15: gptm t imera prescale match (gptmt apmr), offset 0x040 this register ef fectively extends the range of gptmt ama tchr to 24 bits when operating in 16-bit one-shot or periodic mode. gptm t imera prescale match (gptmt apmr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 t imer3 base: 0x4003.3000 of fset 0x040 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t apsmr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gptm t imera prescale match this value is used alongside gptmt ama tchr to detect timer match events while using a prescaler . 0x00 r/w t apsmr 7:0 237 september 02, 2007 preliminary lm3s8962 microcontroller register 16: gptm t imerb prescale match (gptmtbpmr), offset 0x044 this register ef fectively extends the range of gptmtbma tchr to 24 bits when operating in 16-bit one-shot or periodic mode. gptm t imerb prescale match (gptmtbpmr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 t imer3 base: 0x4003.3000 of fset 0x044 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 tbpsmr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 gptm t imerb prescale match this value is used alongside gptmtbma tchr to detect timer match events while using a prescaler . 0x00 r/w tbpsmr 7:0 september 02, 2007 238 preliminary general-purpose t imers register 17: gptm t imera (gptmt ar), offset 0x048 this register shows the current value of the t imera counter in all cases except for input edge count mode. when in this mode, this register contains the time at which the last edge event took place. gptm t imera (gptmt ar) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 t imer3 base: 0x4003.3000 of fset 0x048 t ype ro, reset 0x0000.ffff (16-bit mode) and 0xffff .ffff (32-bit mode) 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 t arh ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 1 1 1 1 0 1 1 1 1 0 1 0 1 1 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t arl ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field gptm t imera register high if the gptmcfg is in a 32-bit mode, t imerb value is read. if the gptmcfg is in a 16-bit mode, this is read as zero. 0xffff (32-bit mode) 0x0000 (16-bit mode) ro t arh 31:16 gptm t imera register low a read returns the current value of the gptm t imera count register , except in input edge count mode, when it returns the timestamp from the last edge event. 0xffff ro t arl 15:0 239 september 02, 2007 preliminary lm3s8962 microcontroller register 18: gptm t imerb (gptmtbr), offset 0x04c this register shows the current value of the t imerb counter in all cases except for input edge count mode. when in this mode, this register contains the time at which the last edge event took place. gptm t imerb (gptmtbr) t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 t imer3 base: 0x4003.3000 of fset 0x04c t ype ro, reset 0x0000.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 tbrl ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 gptm t imerb a read returns the current value of the gptm t imerb count register , except in input edge count mode, when it returns the timestamp from the last edge event. 0xffff ro tbrl 15:0 september 02, 2007 240 preliminary general-purpose t imers 1 1 w atchdog t imer a watchdog timer can generate nonmaskable interrupts (nmis) or a reset when a time-out value is reached. the watchdog timer is used to regain control when a system has failed due to a software error or due to the failure of an external device to respond in the expected way . the stellaris ? w atchdog t imer module consists of a 32-bit down counter , a programmable load register , interrupt generation logic, a locking register , and user-enabled stalling. the w atchdog t imer can be configured to generate an interrupt to the controller on its first time-out, and to generate a reset signal on its second time-out. once the w atchdog t imer has been configured, the lock register can be written to prevent the timer configuration from being inadvertently altered. 1 1.1 block diagram figure 1 1-1. wdt module block diagram 1 1.2 functional description the w atchdog t imer module generates the first time-out signal when the 32-bit counter reaches the zero state after being enabled; enabling the counter also enables the watchdog timer interrupt. after the first time-out event, the 32-bit counter is re-loaded with the value of the w atchdog t imer load (wdtload) register , and the timer resumes counting down from that value. once the 241 september 02, 2007 preliminary lm3s8962 microcontroller control / clock / interrupt generation wdtctl wdticr wdtris wdtmis wdtlock wdttest wdtload wdtv alue comparator 32-bit down counter 0x00000000 interrupt system clock identification registers wdtpcellid 0 wdtperiphid 0 wdtperiphid 4 wdtpcellid 1 wdtperiphid 1 wdtperiphid 5 wdtpcellid 2 wdtperiphid 2 wdtperiphid 6 wdtpcellid 3 wdtperiphid 3 wdtperiphid 7 w atchdog t imer has been configured, the w atchdog t imer lock (wdtlock) register is written, which prevents the timer configuration from being inadvertently altered by software. if the timer counts down to its zero state again before the first time-out interrupt is cleared, and the reset signal has been enabled (via the watchdogresetenable function), the w atchdog timer asserts its reset signal to the system. if the interrupt is cleared before the 32-bit counter reaches its second time-out, the 32-bit counter is loaded with the value in the wdtload register , and counting resumes from that value. if wdtload is written with a new value while the w atchdog t imer counter is counting, then the counter is loaded with the new value and continues counting. w riting to wdtload does not clear an active interrupt. an interrupt must be specifically cleared by writing to the w atchdog interrupt clear (wdticr) register . the w atchdog module interrupt and reset generation can be enabled or disabled as required. when the interrupt is re-enabled, the 32-bit counter is preloaded with the load register value and not its last state. 1 1.3 initialization and configuration t o use the wdt , its peripheral clock must be enabled by setting the wdt bit in the rcgc0 register . the w atchdog t imer is configured using the following sequence: 1. load the wdtload register with the desired timer load value. 2. if the w atchdog is configured to trigger system resets, set the resen bit in the wdtctl register . 3. set the inten bit in the wdtctl register to enable the w atchdog and lock the control register . if software requires that all of the watchdog registers are locked, the w atchdog t imer module can be fully locked by writing any value to the wdtlock register . t o unlock the w atchdog t imer , write a value of 0x1acc.e551. 1 1.4 register map t able 1 1-1 on page 242 lists the w atchdog registers. the of fset listed is a hexadecimal increment to the register s address, relative to the w atchdog t imer base address of 0x4000.0000. t able 1 1-1. w atchdog t imer register map see page description reset t ype name offset 244 w atchdog load 0xffff .ffff r/w wdtload 0x000 245 w atchdog v alue 0xffff .ffff ro wdtv alue 0x004 246 w atchdog control 0x0000.0000 r/w wdtctl 0x008 247 w atchdog interrupt clear - wo wdticr 0x00c 248 w atchdog raw interrupt status 0x0000.0000 ro wdtris 0x010 249 w atchdog masked interrupt status 0x0000.0000 ro wdtmis 0x014 250 w atchdog t est 0x0000.0000 r/w wdttest 0x418 251 w atchdog lock 0x0000.0000 r/w wdtlock 0xc00 september 02, 2007 242 preliminary w atchdog t imer see page description reset t ype name offset 252 w atchdog peripheral identification 4 0x0000.0000 ro wdtperiphid4 0xfd0 253 w atchdog peripheral identification 5 0x0000.0000 ro wdtperiphid5 0xfd4 254 w atchdog peripheral identification 6 0x0000.0000 ro wdtperiphid6 0xfd8 255 w atchdog peripheral identification 7 0x0000.0000 ro wdtperiphid7 0xfdc 256 w atchdog peripheral identification 0 0x0000.0005 ro wdtperiphid0 0xfe0 257 w atchdog peripheral identification 1 0x0000.0018 ro wdtperiphid1 0xfe4 258 w atchdog peripheral identification 2 0x0000.0018 ro wdtperiphid2 0xfe8 259 w atchdog peripheral identification 3 0x0000.0001 ro wdtperiphid3 0xfec 260 w atchdog primecell identification 0 0x0000.000d ro wdtpcellid0 0xff0 261 w atchdog primecell identification 1 0x0000.00f0 ro wdtpcellid1 0xff4 262 w atchdog primecell identification 2 0x0000.0005 ro wdtpcellid2 0xff8 263 w atchdog primecell identification 3 0x0000.00b1 ro wdtpcellid3 0xffc 1 1.5 register descriptions the remainder of this section lists and describes the wdt registers, in numerical order by address of fset. 243 september 02, 2007 preliminary lm3s8962 microcontroller register 1: w atchdog load (wdtload), offset 0x000 this register is the 32-bit interval value used by the 32-bit counter . when this register is written, the value is immediately loaded and the counter restarts counting down from the new value. if the wdtload register is loaded with 0x0000.0000, an interrupt is immediately generated. w atchdog load (wdtload) base 0x4000.0000 of fset 0x000 t ype r/w , reset 0xffff .ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wdtload r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 wdtload r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field w atchdog load v alue 0xffff .ffff r/w wdtload 31:0 september 02, 2007 244 preliminary w atchdog t imer register 2: w atchdog v alue (wdtv alue), offset 0x004 this register contains the current count value of the timer . w atchdog v alue (wdtv alue) base 0x4000.0000 of fset 0x004 t ype ro, reset 0xffff .ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wdtv alue ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 wdtv alue ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 reset description reset t ype name bit/field w atchdog v alue current value of the 32-bit down counter . 0xffff .ffff ro wdtv alue 31:0 245 september 02, 2007 preliminary lm3s8962 microcontroller register 3: w atchdog control (wdtctl), offset 0x008 this register is the watchdog control register . the watchdog timer can be configured to generate a reset signal (on second time-out) or an interrupt on time-out. when the watchdog interrupt has been enabled, all subsequent writes to the control register are ignored. the only mechanism that can re-enable writes is a hardware reset. w atchdog control (wdtctl) base 0x4000.0000 of fset 0x008 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 inten resen reserved r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:2 w atchdog reset enable the resen values are defined as follows: description v alue disabled. 0 enable the w atchdog module reset output. 1 0 r/w resen 1 w atchdog interrupt enable the inten values are defined as follows: description v alue interrupt event disabled (once this bit is set, it can only be cleared by a hardware reset). 0 interrupt event enabled. once enabled, all writes are ignored. 1 0 r/w inten 0 september 02, 2007 246 preliminary w atchdog t imer register 4: w atchdog interrupt clear (wdticr), offset 0x00c this register is the interrupt clear register . a write of any value to this register clears the w atchdog interrupt and reloads the 32-bit counter from the wdtload register . v alue for a read or reset is indeterminate. w atchdog interrupt clear (wdticr) base 0x4000.0000 of fset 0x00c t ype wo, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wdtintclr wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo t ype - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 wdtintclr wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo t ype - - - - - - - - - - - - - - - - reset description reset t ype name bit/field w atchdog interrupt clear - wo wdtintclr 31:0 247 september 02, 2007 preliminary lm3s8962 microcontroller register 5: w atchdog raw interrupt status (wdtris), offset 0x010 this register is the raw interrupt status register . w atchdog interrupt events can be monitored via this register if the controller interrupt is masked. w atchdog raw interrupt status (wdtris) base 0x4000.0000 of fset 0x010 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 wdtris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 w atchdog raw interrupt status gives the raw interrupt state (prior to masking) of wdtintr . 0 ro wdtris 0 september 02, 2007 248 preliminary w atchdog t imer register 6: w atchdog masked interrupt status (wdtmis), offset 0x014 this register is the masked interrupt status register . the value of this register is the logical and of the raw interrupt bit and the w atchdog interrupt enable bit. w atchdog masked interrupt status (wdtmis) base 0x4000.0000 of fset 0x014 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 wdtmis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 w atchdog masked interrupt status gives the masked interrupt state (after masking) of the wdtintr interrupt. 0 ro wdtmis 0 249 september 02, 2007 preliminary lm3s8962 microcontroller register 7: w atchdog t est (wdttest), offset 0x418 this register provides user-enabled stalling when the microcontroller asserts the cpu halt flag during debug. w atchdog t est (wdttest) base 0x4000.0000 of fset 0x418 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved st all reserved ro ro ro ro ro ro ro ro r/w ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:9 w atchdog stall enable when set to 1, if the stellaris ? microcontroller is stopped with a debugger , the watchdog timer stops counting. once the microcontroller is restarted, the watchdog timer resumes counting. 0 r/w st all 8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 7:0 september 02, 2007 250 preliminary w atchdog t imer register 8: w atchdog lock (wdtlock), offset 0xc00 w riting 0x1acc.e551 to the wdtlock register enables write access to all other registers. w riting any other value to the wdtlock register re-enables the locked state for register writes to all the other registers. reading the wdtlock register returns the lock status rather than the 32-bit value written. therefore, when write accesses are disabled, reading the wdtlock register returns 0x0000.0001 (when locked; otherwise, the returned value is 0x0000.0000 (unlocked)). w atchdog lock (wdtlock) base 0x4000.0000 of fset 0xc00 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 wdtlock r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 wdtlock r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field w atchdog lock a write of the value 0x1acc.e551 unlocks the watchdog registers for write access. a write of any other value reapplies the lock, preventing any register updates. a read of this register returns the following values: description v alue locked 0x0000.0001 unlocked 0x0000.0000 0x0000 r/w wdtlock 31:0 251 september 02, 2007 preliminary lm3s8962 microcontroller register 9: w atchdog peripheral identification 4 (wdtperiphid4), offset 0xfd0 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. w atchdog peripheral identification 4 (wdtperiphid4) base 0x4000.0000 of fset 0xfd0 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid4 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 wdt peripheral id register[7:0] 0x00 ro pid4 7:0 september 02, 2007 252 preliminary w atchdog t imer register 10: w atchdog peripheral identification 5 (wdtperiphid5), offset 0xfd4 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. w atchdog peripheral identification 5 (wdtperiphid5) base 0x4000.0000 of fset 0xfd4 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid5 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 wdt peripheral id register[15:8] 0x00 ro pid5 7:0 253 september 02, 2007 preliminary lm3s8962 microcontroller register 1 1: w atchdog peripheral identification 6 (wdtperiphid6), offset 0xfd8 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. w atchdog peripheral identification 6 (wdtperiphid6) base 0x4000.0000 of fset 0xfd8 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid6 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 wdt peripheral id register[23:16] 0x00 ro pid6 7:0 september 02, 2007 254 preliminary w atchdog t imer register 12: w atchdog peripheral identification 7 (wdtperiphid7), offset 0xfdc the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. w atchdog peripheral identification 7 (wdtperiphid7) base 0x4000.0000 of fset 0xfdc t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid7 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 wdt peripheral id register[31:24] 0x00 ro pid7 7:0 255 september 02, 2007 preliminary lm3s8962 microcontroller register 13: w atchdog peripheral identification 0 (wdtperiphid0), offset 0xfe0 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. w atchdog peripheral identification 0 (wdtperiphid0) base 0x4000.0000 of fset 0xfe0 t ype ro, reset 0x0000.0005 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 w atchdog peripheral id register[7:0] 0x05 ro pid0 7:0 september 02, 2007 256 preliminary w atchdog t imer register 14: w atchdog peripheral identification 1 (wdtperiphid1), offset 0xfe4 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. w atchdog peripheral identification 1 (wdtperiphid1) base 0x4000.0000 of fset 0xfe4 t ype ro, reset 0x0000.0018 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 w atchdog peripheral id register[15:8] 0x18 ro pid1 7:0 257 september 02, 2007 preliminary lm3s8962 microcontroller register 15: w atchdog peripheral identification 2 (wdtperiphid2), offset 0xfe8 the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. w atchdog peripheral identification 2 (wdtperiphid2) base 0x4000.0000 of fset 0xfe8 t ype ro, reset 0x0000.0018 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 w atchdog peripheral id register[23:16] 0x18 ro pid2 7:0 september 02, 2007 258 preliminary w atchdog t imer register 16: w atchdog peripheral identification 3 (wdtperiphid3), offset 0xfec the wdtperiphidn registers are hard-coded and the fields within the register determine the reset value. w atchdog peripheral identification 3 (wdtperiphid3) base 0x4000.0000 of fset 0xfec t ype ro, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 w atchdog peripheral id register[31:24] 0x01 ro pid3 7:0 259 september 02, 2007 preliminary lm3s8962 microcontroller register 17: w atchdog primecell identification 0 (wdtpcellid0), offset 0xff0 the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. w atchdog primecell identification 0 (wdtpcellid0) base 0x4000.0000 of fset 0xff0 t ype ro, reset 0x0000.000d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 w atchdog primecell id register[7:0] 0x0d ro cid0 7:0 september 02, 2007 260 preliminary w atchdog t imer register 18: w atchdog primecell identification 1 (wdtpcellid1), offset 0xff4 the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. w atchdog primecell identification 1 (wdtpcellid1) base 0x4000.0000 of fset 0xff4 t ype ro, reset 0x0000.00f0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 w atchdog primecell id register[15:8] 0xf0 ro cid1 7:0 261 september 02, 2007 preliminary lm3s8962 microcontroller register 19: w atchdog primecell identification 2 (wdtpcellid2), offset 0xff8 the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. w atchdog primecell identification 2 (wdtpcellid2) base 0x4000.0000 of fset 0xff8 t ype ro, reset 0x0000.0005 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 w atchdog primecell id register[23:16] 0x05 ro cid2 7:0 september 02, 2007 262 preliminary w atchdog t imer register 20: w atchdog primecell identification 3 (wdtpcellid3 ), offset 0xffc the wdtpcellidn registers are hard-coded and the fields within the register determine the reset value. w atchdog primecell identification 3 (wdtpcellid3) base 0x4000.0000 of fset 0xffc t ype ro, reset 0x0000.00b1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 w atchdog primecell id register[31:24] 0xb1 ro cid3 7:0 263 september 02, 2007 preliminary lm3s8962 microcontroller 12 analog-to-digital converter (adc) an analog-to-digital converter (adc) is a peripheral that converts a continuous analog voltage to a discrete digital number . the stellaris ? adc module features 10-bit conversion resolution and supports four input channels, plus an internal temperature sensor . the adc module contains a programmable sequencer which allows for the sampling of multiple analog input sources without controller intervention. each sample sequence provides flexible programming with fully configurable input source, trigger events, interrupt generation, and sequence priority . the stellaris ? adc provides the following features: four analog input channels single-ended and dif ferential-input configurations internal temperature sensor sample rate of 500 thousand samples/second four programmable sample conversion sequences from one to eight entries long, with corresponding conversion result fifos flexible trigger control C controller (software) C t imers C analog comparators C pwm C gpio hardware averaging of up to 64 samples for improved accuracy september 02, 2007 264 preliminary analog-to-digital converter (adc) 12.1 block diagram figure 12-1. adc module block diagram 12.2 functional description the stellaris ? adc collects sample data by using a programmable sequence-based approach instead of the traditional single or double-sampling approach found on many adc modules. each sample sequence is a fully programmed series of consecutive (back-to-back) samples, allowing the adc to collect data from multiple input sources without having to be re-configured or serviced by the controller . the programming of each sample in the sample sequence includes parameters such as the input source and mode (dif ferential versus single-ended input), interrupt generation on sample completion, and the indicator for the last sample in the sequence. 12.2.1 sample sequencers the sampling control and data capture is handled by the sample sequencers. all of the sequencers are identical in implementation except for the number of samples that can be captured and the depth of the fifo. t able 12-1 on page 265 shows the maximum number of samples that each sequencer can capture and its corresponding fifo depth. in this implementation, each fifo entry is a 32-bit word, with the lower 10 bits containing the conversion result. t able 12-1. samples and fifo depth of sequencers depth of fifo number of samples sequencer 1 1 ss3 4 4 ss2 4 4 ss1 8 8 ss0 265 september 02, 2007 preliminary lm3s8962 microcontroller analog-to-digital converter adcssfst a t0 adcssctl0 adcssmux0 sample sequencer 0 adcssfst a t1 adcssctl1 adcssmux1 sample sequencer 1 adcssfst a t2 adcssctl2 adcssmux2 sample sequencer 2 adcssfst a t3 adcssctl3 adcssmux3 sample sequencer 3 adcust a t adcost a t adcactss control/status adcsspri adcisc adcris adcim interrupt control analog inputs ss0 interrupt ss1 interrupt ss2 interrupt ss3 interrupt adcemux adcpssi t rigger events ss0 ss1 ss2 ss3 comparator gpio (pb4) t imer pwm comparator gpio (pb4) t imer pwm comparator gpio (pb4) t imer pwm comparator gpio (pb4) t imer pwm adcssfifo0 adcssfifo1 adcssfifo2 adcssfifo3 fifo block hardware a verager adcsac for a given sample sequence, each sample is defined by two 4-bit nibbles in the adc sample sequence input multiplexer select (adcssmuxn) and adc sample sequence control (adcssctln) registers, where "n" corresponds to the sequence number . the adcssmuxn nibbles select the input pin, while the adcssctln nibbles contain the sample control bits corresponding to parameters such as temperature sensor selection, interrupt enable, end of sequence, and dif ferential input mode. sample sequencers are enabled by setting the respective asenn bit in the adc active sample sequencer (adcactss) register , but can be configured before being enabled. when configuring a sample sequence, multiple uses of the same input pin within the same sequence is allowed. in the adcssctln register , the interrupt enable (ie) bits can be set for any combination of samples, allowing interrupts to be generated after every sample in the sequence if necessary . also, the end bit can be set at any point within a sample sequence. for example, if sequencer 0 is used, the end bit can be set in the nibble associated with the fifth sample, allowing sequencer 0 to complete execution of the sample sequence after the fifth sample. after a sample sequence completes execution, the result data can be retrieved from the adc sample sequence result fifo (adcssfifon) registers. the fifos are simple circular buf fers that read a single address to "pop" result data. for software debug purposes, the positions of the fifo head and tail pointers are visible in the adc sample sequence fifo status (adcssfst a tn) registers along with full and empty status flags. overflow and underflow conditions are monitored using the adcost a t and adcust a t registers. 12.2.2 module control outside of the sample sequencers, the remainder of the control logic is responsible for tasks such as interrupt generation, sequence prioritization, and trigger configuration. most of the adc control logic runs at the adc clock rate of 14-18 mhz. the internal adc divider is configured automatically by hardware when the system xtal is selected. the automatic clock divider configuration targets 16.667 mhz operation for all stellaris ? devices. 12.2.2.1 interrupts the sample sequencers dictate the events that cause interrupts, but they don't have control over whether the interrupt is actually sent to the interrupt controller . the adc module's interrupt signal is controlled by the state of the mask bits in the adc interrupt mask (adcim) register . interrupt status can be viewed at two locations: the adc raw interrupt status (adcris) register , which shows the raw status of a sample sequencer's interrupt signal, and the adc interrupt status and clear (adcisc) register , which shows the logical and of the adcris register s inr bit and the adcim register s mask bits. interrupts are cleared by writing a 1 to the corresponding in bit in adcisc . 12.2.2.2 prioritization when sampling events (triggers) happen concurrently , they are prioritized for processing by the values in the adc sample sequencer priority (adcsspri) register . v alid priority values are in the range of 0-3, with 0 being the highest priority and 3 being the lowest. multiple active sample sequencer units with the same priority do not provide consistent results, so software must ensure that all active sample sequencer units have a unique priority value. 12.2.2.3 sampling events sample triggering for each sample sequencer is defined in the adc event multiplexer select (adcemux) register . the external peripheral triggering sources vary by stellaris ? family member , september 02, 2007 266 preliminary analog-to-digital converter (adc) but all devices share the "controller" and "always" triggers. software can initiate sampling by setting the ch bits in the adc processor sample sequence initiate (adcpssi) register . when using the "always" trigger , care must be taken. if a sequence's priority is too high, it is possible to starve other lower priority sequences. 12.2.3 hardware sample a veraging circuit higher precision results can be generated using the hardware averaging circuit, however , the improved results are at the cost of throughput. up to 64 samples can be accumulated and averaged to form a single data entry in the sequencer fifo. throughput is decreased proportionally to the number of samples in the averaging calculation. for example, if the averaging circuit is configured to average 16 samples, the throughput is decreased by a factor of 16. by default the averaging circuit is of f and all data from the converter passes through to the sequencer fifo. the averaging hardware is controlled by the adc sample a veraging control (adcsac) register (see page 282 ). there is a single averaging circuit and all input channels receive the same amount of averaging whether they are single-ended or dif ferential. 12.2.4 analog-to-digital converter the converter itself generates a 10-bit output value for selected analog input. special analog pads are used to minimize the distortion on the input. 12.2.5 t est modes there is a user-available test mode that allows for loopback operation within the digital portion of the adc module. this can be useful for debugging software without having to provide actual analog stimulus. this mode is available through the adc t est mode loopback (adctmlb) register (see page 295 ). 12.2.6 internal t emperature sensor the internal temperature sensor provides an analog temperature reading as well as a reference voltage. the voltage at the output terminal senso is given by the following equation: senso = 2.7 - ((t + 55) / 75) this relation is shown in figure 12-2 on page 268 . 267 september 02, 2007 preliminary lm3s8962 microcontroller figure 12-2. internal t emperature sensor characteristic 12.3 initialization and configuration in order for the adc module to be used, the pll must be enabled and using a supported crystal frequency (see the rcc register). using unsupported frequencies can cause faulty operation in the adc module. 12.3.1 module initialization initialization of the adc module is a simple process with very few steps. the main steps include enabling the clock to the adc and reconfiguring the sample sequencer priorities (if needed). the initialization sequence for the adc is as follows: 1. enable the adc clock by writing a value of 0x0001.0000 to the rcgc1 register (see page 101 ). 2. if required by the application, reconfigure the sample sequencer priorities in the adcsspri register . the default configuration has sample sequencer 0 with the highest priority , and sample sequencer 3 as the lowest priority . 12.3.2 sample sequencer configuration configuration of the sample sequencers is slightly more complex than the module initialization since each sample sequence is completely programmable. the configuration for each sample sequencer should be as follows: 1. ensure that the sample sequencer is disabled by writing a 0 to the corresponding asen bit in the adcactss register . programming of the sample sequencers is allowed without having them enabled. disabling the sequencer during programming prevents erroneous execution if a trigger event were to occur during the configuration process. 2. configure the trigger event for the sample sequencer in the adcemux register . 3. for each sample in the sample sequence, configure the corresponding input source in the adcssmuxn register . september 02, 2007 268 preliminary analog-to-digital converter (adc) 4. for each sample in the sample sequence, configure the sample control bits in the corresponding nibble in the adcssctln register . when programming the last nibble, ensure that the end bit is set. failure to set the end bit causes unpredictable behavior . 5. if interrupts are to be used, write a 1 to the corresponding mask bit in the adcim register . 6. enable the sample sequencer logic by writing a 1 to the corresponding asen bit in the adcactss register . 12.4 register map t able 12-2 on page 269 lists the adc registers. the of fset listed is a hexadecimal increment to the register s address, relative to the adc base address of 0x4003.8000. t able 12-2. adc register map see page description reset t ype name offset 271 adc active sample sequencer 0x0000.0000 r/w adcactss 0x000 272 adc raw interrupt status 0x0000.0000 ro adcris 0x004 273 adc interrupt mask 0x0000.0000 r/w adcim 0x008 274 adc interrupt status and clear 0x0000.0000 r/w1c adcisc 0x00c 275 adc overflow status 0x0000.0000 r/w1c adcost a t 0x010 276 adc event multiplexer select 0x0000.0000 r/w adcemux 0x014 279 adc underflow status 0x0000.0000 r/w1c adcust a t 0x018 280 adc sample sequencer priority 0x0000.3210 r/w adcsspri 0x020 281 adc processor sample sequence initiate - wo adcpssi 0x028 282 adc sample a veraging control 0x0000.0000 r/w adcsac 0x030 283 adc sample sequence input multiplexer select 0 0x0000.0000 r/w adcssmux0 0x040 285 adc sample sequence control 0 0x0000.0000 r/w adcssctl0 0x044 288 adc sample sequence result fifo 0 0x0000.0000 ro adcssfifo0 0x048 289 adc sample sequence fifo 0 status 0x0000.0100 ro adcssfst a t0 0x04c 290 adc sample sequence input multiplexer select 1 0x0000.0000 r/w adcssmux1 0x060 291 adc sample sequence control 1 0x0000.0000 r/w adcssctl1 0x064 288 adc sample sequence result fifo 1 0x0000.0000 ro adcssfifo1 0x068 289 adc sample sequence fifo 1 status 0x0000.0100 ro adcssfst a t1 0x06c 290 adc sample sequence input multiplexer select 2 0x0000.0000 r/w adcssmux2 0x080 291 adc sample sequence control 2 0x0000.0000 r/w adcssctl2 0x084 288 adc sample sequence result fifo 2 0x0000.0000 ro adcssfifo2 0x088 289 adc sample sequence fifo 2 status 0x0000.0100 ro adcssfst a t2 0x08c 293 adc sample sequence input multiplexer select 3 0x0000.0000 r/w adcssmux3 0x0a0 269 september 02, 2007 preliminary lm3s8962 microcontroller see page description reset t ype name offset 294 adc sample sequence control 3 0x0000.0002 r/w adcssctl3 0x0a4 288 adc sample sequence result fifo 3 0x0000.0000 ro adcssfifo3 0x0a8 289 adc sample sequence fifo 3 status 0x0000.0100 ro adcssfst a t3 0x0ac 295 adc t est mode loopback 0x0000.0000 r/w adctmlb 0x100 12.5 register descriptions the remainder of this section lists and describes the adc registers, in numerical order by address of fset. september 02, 2007 270 preliminary analog-to-digital converter (adc) register 1: adc active sample sequencer (adcactss), offset 0x000 this register controls the activation of the sample sequencers. each sample sequencer can be enabled/disabled independently . adc active sample sequencer (adcactss) base 0x4003.8000 of fset 0x000 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 asen0 asen1 asen2 asen3 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:4 adc ss3 enable specifies whether sample sequencer 3 is enabled. if set, the sample sequence logic for sequencer 3 is active. otherwise, the sequencer is inactive. 0 r/w asen3 3 adc ss2 enable specifies whether sample sequencer 2 is enabled. if set, the sample sequence logic for sequencer 2 is active. otherwise, the sequencer is inactive. 0 r/w asen2 2 adc ss1 enable specifies whether sample sequencer 1 is enabled. if set, the sample sequence logic for sequencer 1 is active. otherwise, the sequencer is inactive. 0 r/w asen1 1 adc ss0 enable specifies whether sample sequencer 0 is enabled. if set, the sample sequence logic for sequencer 0 is active. otherwise, the sequencer is inactive. 0 r/w asen0 0 271 september 02, 2007 preliminary lm3s8962 microcontroller register 2: adc raw interrupt status (adcris), offset 0x004 this register shows the status of the raw interrupt signal of each sample sequencer . these bits may be polled by software to look for interrupt conditions without having to generate controller interrupts. adc raw interrupt status (adcris) base 0x4003.8000 of fset 0x004 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 inr0 inr1 inr2 inr3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:4 ss3 raw interrupt status set by hardware when a sample with its respective adcssctl3 ie bit has completed conversion. this bit is cleared by writing a 1 to the adcisc in3 bit. 0 ro inr3 3 ss2 raw interrupt status set by hardware when a sample with its respective adcssctl2 ie bit has completed conversion. this bit is cleared by writing a 1 to the adcisc in2 bit. 0 ro inr2 2 ss1 raw interrupt status set by hardware when a sample with its respective adcssctl1 ie bit has completed conversion. this bit is cleared by writing a 1 to the adcisc in1 bit. 0 ro inr1 1 ss0 raw interrupt status set by hardware when a sample with its respective adcssctl0 ie bit has completed conversion. this bit is cleared by writing a 1 to the adcisc in0 bit. 0 ro inr0 0 september 02, 2007 272 preliminary analog-to-digital converter (adc) register 3: adc interrupt mask (adcim), offset 0x008 this register controls whether the sample sequencer raw interrupt signals are promoted to controller interrupts. the raw interrupt signal for each sample sequencer can be masked independently . adc interrupt mask (adcim) base 0x4003.8000 of fset 0x008 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 mask0 mask1 mask2 mask3 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:4 ss3 interrupt mask specifies whether the raw interrupt signal from sample sequencer 3 ( adcris register inr3 bit) is promoted to a controller interrupt. if set, the raw interrupt signal is promoted to a controller interrupt. otherwise, it is not. 0 r/w mask3 3 ss2 interrupt mask specifies whether the raw interrupt signal from sample sequencer 2 ( adcris register inr2 bit) is promoted to a controller interrupt. if set, the raw interrupt signal is promoted to a controller interrupt. otherwise, it is not. 0 r/w mask2 2 ss1 interrupt mask specifies whether the raw interrupt signal from sample sequencer 1 ( adcris register inr1 bit) is promoted to a controller interrupt. if set, the raw interrupt signal is promoted to a controller interrupt. otherwise, it is not. 0 r/w mask1 1 ss0 interrupt mask specifies whether the raw interrupt signal from sample sequencer 0 ( adcris register inr0 bit) is promoted to a controller interrupt. if set, the raw interrupt signal is promoted to a controller interrupt. otherwise, it is not. 0 r/w mask0 0 273 september 02, 2007 preliminary lm3s8962 microcontroller register 4: adc interrupt status and clear (adcisc), offset 0x00c this register provides the mechanism for clearing interrupt conditions, and shows the status of controller interrupts generated by the sample sequencers. when read, each bit field is the logical and of the respective inr and mask bits. interrupts are cleared by writing a 1 to the corresponding bit position. if software is polling the adcris instead of generating interrupts, the inr bits are still cleared via the adcisc register , even if the in bit is not set. adc interrupt status and clear (adcisc) base 0x4003.8000 of fset 0x00c t ype r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 in0 in1 in2 in3 reserved r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:4 ss3 interrupt status and clear this bit is set by hardware when the mask3 and inr3 bits are both 1, providing a level-based interrupt to the controller . it is cleared by writing a 1, and also clears the inr3 bit. 0 r/w1c in3 3 ss2 interrupt status and clear this bit is set by hardware when the mask2 and inr2 bits are both 1, providing a level based interrupt to the controller . it is cleared by writing a 1, and also clears the inr2 bit. 0 r/w1c in2 2 ss1 interrupt status and clear this bit is set by hardware when the mask1 and inr1 bits are both 1, providing a level based interrupt to the controller . it is cleared by writing a 1, and also clears the inr1 bit. 0 r/w1c in1 1 ss0 interrupt status and clear this bit is set by hardware when the mask0 and inr0 bits are both 1, providing a level based interrupt to the controller . it is cleared by writing a 1, and also clears the inr0 bit. 0 r/w1c in0 0 september 02, 2007 274 preliminary analog-to-digital converter (adc) register 5: adc overflow status (adcost a t), offset 0x010 this register indicates overflow conditions in the sample sequencer fifos. once the overflow condition has been handled by software, the condition can be cleared by writing a 1 to the corresponding bit position. adc overflow status (adcost a t) base 0x4003.8000 of fset 0x010 t ype r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ov0 ov1 ov2 ov3 reserved r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:4 ss3 fifo overflow this bit specifies that the fifo for sample sequencer 3 has hit an overflow condition where the fifo is full and a write was requested. when an overflow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. this bit is cleared by writing a 1. 0 r/w1c ov3 3 ss2 fifo overflow this bit specifies that the fifo for sample sequencer 2 has hit an overflow condition where the fifo is full and a write was requested. when an overflow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. this bit is cleared by writing a 1. 0 r/w1c ov2 2 ss1 fifo overflow this bit specifies that the fifo for sample sequencer 1 has hit an overflow condition where the fifo is full and a write was requested. when an overflow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. this bit is cleared by writing a 1. 0 r/w1c ov1 1 ss0 fifo overflow this bit specifies that the fifo for sample sequencer 0 has hit an overflow condition where the fifo is full and a write was requested. when an overflow is detected, the most recent write is dropped and this bit is set by hardware to indicate the occurrence of dropped data. this bit is cleared by writing a 1. 0 r/w1c ov0 0 275 september 02, 2007 preliminary lm3s8962 microcontroller register 6: adc event multiplexer select (adcemux), offset 0x014 the adcemux selects the event (trigger) that initiates sampling for each sample sequencer . each sample sequencer can be configured with a unique trigger source. adc event multiplexer select (adcemux) base 0x4003.8000 of fset 0x014 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 em0 em1 em2 em3 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:16 ss3 t rigger select this field selects the trigger source for sample sequencer 3. the valid configurations for this field are: event v alue controller (default) 0x0 analog comparator 0 0x1 reserved 0x2 reserved 0x3 external (gpio pb4) 0x4 t imer 0x5 pwm0 0x6 pwm1 0x7 pwm2 0x8 reserved 0x9-0xe always (continuously sample) 0xf 0x00 r/w em3 15:12 september 02, 2007 276 preliminary analog-to-digital converter (adc) description reset t ype name bit/field ss2 t rigger select this field selects the trigger source for sample sequencer 2. the valid configurations for this field are: event v alue controller (default) 0x0 analog comparator 0 0x1 reserved 0x2 reserved 0x3 external (gpio pb4) 0x4 t imer 0x5 pwm0 0x6 pwm1 0x7 pwm2 0x8 reserved 0x9-0xe always (continuously sample) 0xf 0x00 r/w em2 1 1:8 ss1 t rigger select this field selects the trigger source for sample sequencer 1. the valid configurations for this field are: event v alue controller (default) 0x0 analog comparator 0 0x1 reserved 0x2 reserved 0x3 external (gpio pb4) 0x4 t imer 0x5 pwm0 0x6 pwm1 0x7 pwm2 0x8 reserved 0x9-0xe always (continuously sample) 0xf 0x00 r/w em1 7:4 277 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field ss0 t rigger select this field selects the trigger source for sample sequencer 0. the valid configurations for this field are: event v alue controller (default) 0x0 analog comparator 0 0x1 reserved 0x2 reserved 0x3 external (gpio pb4) 0x4 t imer 0x5 pwm0 0x6 pwm1 0x7 pwm2 0x8 reserved 0x9-0xe always (continuously sample) 0xf 0x00 r/w em0 3:0 september 02, 2007 278 preliminary analog-to-digital converter (adc) register 7: adc underflow status (adcust a t), offset 0x018 this register indicates underflow conditions in the sample sequencer fifos. the corresponding underflow condition can be cleared by writing a 1 to the relevant bit position. adc underflow status (adcust a t) base 0x4003.8000 of fset 0x018 t ype r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 uv0 uv1 uv2 uv3 reserved r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:4 ss3 fifo underflow this bit specifies that the fifo for sample sequencer 3 has hit an underflow condition where the fifo is empty and a read was requested. the problematic read does not move the fifo pointers, and 0s are returned. this bit is cleared by writing a 1. 0 r/w1c uv3 3 ss2 fifo underflow this bit specifies that the fifo for sample sequencer 2 has hit an underflow condition where the fifo is empty and a read was requested. the problematic read does not move the fifo pointers, and 0s are returned. this bit is cleared by writing a 1. 0 r/w1c uv2 2 ss1 fifo underflow this bit specifies that the fifo for sample sequencer 1 has hit an underflow condition where the fifo is empty and a read was requested. the problematic read does not move the fifo pointers, and 0s are returned. this bit is cleared by writing a 1. 0 r/w1c uv1 1 ss0 fifo underflow this bit specifies that the fifo for sample sequencer 0 has hit an underflow condition where the fifo is empty and a read was requested. the problematic read does not move the fifo pointers, and 0s are returned. this bit is cleared by writing a 1. 0 r/w1c uv0 0 279 september 02, 2007 preliminary lm3s8962 microcontroller register 8: adc sample sequencer priority (adcsspri), offset 0x020 this register sets the priority for each of the sample sequencers. out of reset, sequencer 0 has the highest priority , and sample sequence 3 has the lowest priority . when reconfiguring sequence priorities, each sequence must have a unique priority or the adc behavior is inconsistent. adc sample sequencer priority (adcsspri) base 0x4003.8000 of fset 0x020 t ype r/w , reset 0x0000.3210 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ss0 reserved ss1 reserved ss2 reserved ss3 reserved r/w r/w ro ro r/w r/w ro ro r/w r/w ro ro r/w r/w ro ro t ype 0 0 0 0 1 0 0 0 0 1 0 0 1 1 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:14 ss3 priority the ss3 field contains a binary-encoded value that specifies the priority encoding of sample sequencer 3. a priority encoding of 0 is highest and 3 is lowest. the priorities assigned to the sequencers must be uniquely mapped. adc behavior is not consistent if two or more fields are equal. 0x3 r/w ss3 13:12 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 1 1:10 ss2 priority the ss2 field contains a binary-encoded value that specifies the priority encoding of sample sequencer 2. 0x2 r/w ss2 9:8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:6 ss1 priority the ss1 field contains a binary-encoded value that specifies the priority encoding of sample sequencer 1. 0x1 r/w ss1 5:4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3:2 ss0 priority the ss0 field contains a binary-encoded value that specifies the priority encoding of sample sequencer 0. 0x0 r/w ss0 1:0 september 02, 2007 280 preliminary analog-to-digital converter (adc) register 9: adc processor sample sequence initiate (adcpssi), offset 0x028 this register provides a mechanism for application software to initiate sampling in the sample sequencers. sample sequences can be initiated individually or in any combination. when multiple sequences are triggered simultaneously , the priority encodings in adcsspri dictate execution order . adc processor sample sequence initiate (adcpssi) base 0x4003.8000 of fset 0x028 t ype wo, reset - 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo t ype - - - - - - - - - - - - - - - - reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ss0 ss1 ss2 ss3 reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo t ype - - - - - - - - - - - - - - - - reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. - wo reserved 31:4 ss3 initiate only a write by software is valid; a read of the register returns no meaningful data. when set by software, sampling is triggered on sample sequencer 3, assuming the sequencer is enabled in the adcactss register . - wo ss3 3 ss2 initiate only a write by software is valid; a read of the register returns no meaningful data. when set by software, sampling is triggered on sample sequencer 2, assuming the sequencer is enabled in the adcactss register . - wo ss2 2 ss1 initiate only a write by software is valid; a read of the register returns no meaningful data. when set by software, sampling is triggered on sample sequencer 1, assuming the sequencer is enabled in the adcactss register . - wo ss1 1 ss0 initiate only a write by software is valid; a read of the register returns no meaningful data. when set by software, sampling is triggered on sample sequencer 0, assuming the sequencer is enabled in the adcactss register . - wo ss0 0 281 september 02, 2007 preliminary lm3s8962 microcontroller register 10: adc sample a veraging control (adcsac), offset 0x030 this register controls the amount of hardware averaging applied to conversion results. the final conversion result stored in the fifo is averaged from 2 a vg consecutive adc samples at the specified adc speed. if a vg is 0, the sample is passed directly through without any averaging. if a vg=6, then 64 consecutive adc samples are averaged to generate one result in the sequencer fifo. an a vg = 7 provides unpredictable results. adc sample a veraging control (adcsac) base 0x4003.8000 of fset 0x030 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 a vg reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:3 hardware a veraging control specifies the amount of hardware averaging that will be applied to adc samples. the avg field can be any value between 0 and 6. entering a value of 7 creates unpredictable results. description v alue no hardware oversampling 0x0 2x hardware oversampling 0x1 4x hardware oversampling 0x2 8x hardware oversampling 0x3 16x hardware oversampling 0x4 32x hardware oversampling 0x5 64x hardware oversampling 0x6 reserved 0x7 0x0 r/w a vg 2:0 september 02, 2007 282 preliminary analog-to-digital converter (adc) register 1 1: adc sample sequence input multiplexer select 0 (adcssmux0), offset 0x040 this register defines the analog input configuration for each sample in a sequence executed with sample sequencer 0. this register is 32-bits wide and contains information for eight possible samples. adc sample sequence input multiplexer select 0 (adcssmux0) base 0x4003.8000 of fset 0x040 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mux4 reserved mux5 reserved mux6 reserved mux7 reserved r/w r/w ro ro r/w r/w ro ro r/w r/w ro ro r/w r/w ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 mux0 reserved mux1 reserved mux2 reserved mux3 reserved r/w r/w ro ro r/w r/w ro ro r/w r/w ro ro r/w r/w ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:30 8th sample input select the mux7 field is used during the eighth sample of a sequence executed with the sample sequencer . it specifies which of the analog inputs is sampled for the analog-to-digital conversion. the value set here indicates the corresponding pin, for example, a value of 1 indicates the input is adc1 . 0 r/w mux7 29:28 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 27:26 7th sample input select the mux6 field is used during the seventh sample of a sequence executed with the sample sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 0 r/w mux6 25:24 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 23:22 6th sample input select the mux5 field is used during the sixth sample of a sequence executed with the sample sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 0 r/w mux5 21:20 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 19:18 283 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field 5th sample input select the mux4 field is used during the fifth sample of a sequence executed with the sample sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 0 r/w mux4 17:16 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:14 4th sample input select the mux3 field is used during the fourth sample of a sequence executed with the sample sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 0 r/w mux3 13:12 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 1 1:10 3rd sample input select the mux2 field is used during the third sample of a sequence executed with the sample sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 0 r/w mux2 9:8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:6 2nd sample input select the mux1 field is used during the second sample of a sequence executed with the sample sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 0 r/w mux1 5:4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3:2 1st sample input select the mux0 field is used during the first sample of a sequence executed with the sample sequencer and specifies which of the analog inputs is sampled for the analog-to-digital conversion. 0 r/w mux0 1:0 september 02, 2007 284 preliminary analog-to-digital converter (adc) register 12: adc sample sequence control 0 (adcssctl0), offset 0x044 this register contains the configuration information for each sample for a sequence executed with sample sequencer 0. when configuring a sample sequence, the end bit must be set at some point, whether it be after the first sample, last sample, or any sample in between. this register is 32-bits wide and contains information for eight possible samples. adc sample sequence control 0 (adcssctl0) base 0x4003.8000 of fset 0x044 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 d4 end4 ie4 ts4 d5 end5 ie5 ts5 d6 end6 ie6 ts6 d7 end7 ie7 ts7 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 d0 end0 ie0 ts0 d1 end1 ie1 ts1 d2 end2 ie2 ts2 d3 end3 ie3 ts3 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field 8th sample t emp sensor select the ts7 bit is used during the eighth sample of the sample sequence and specifies the input source of the sample. if set, the temperature sensor is read. otherwise, the input pin specified by the adcssmux register is read. 0 r/w ts7 31 8th sample interrupt enable the ie7 bit is used during the eighth sample of the sample sequence and specifies whether the raw interrupt signal ( inr0 bit) is asserted at the end of the sample's conversion. if the mask0 bit in the adcim register is set, the interrupt is promoted to a controller-level interrupt. when this bit is set, the raw interrupt is asserted, otherwise it is not. it is legal to have multiple samples within a sequence generate interrupts. 0 r/w ie7 30 8th sample is end of sequence the end7 bit indicates that this is the last sample of the sequence. it is possible to end the sequence on any sample position. samples defined after the sample containing a set end are not requested for conversion even though the fields may be non-zero. it is required that software write the end bit somewhere within the sequence. (sample sequencer 3, which only has a single sample in the sequence, is hardwired to have the end0 bit set.) setting this bit indicates that this sample is the last in the sequence. 0 r/w end7 29 8th sample dif f input select the d7 bit indicates that the analog input is to be dif ferentially sampled. the corresponding adcssmuxx nibble must be set to the pair number "i", where the paired inputs are "2i and 2i+1". the temperature sensor does not have a dif ferential option. when set, the analog inputs are dif ferentially sampled. 0 r/w d7 28 7th sample t emp sensor select same definition as ts7 but used during the seventh sample. 0 r/w ts6 27 285 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field 7th sample interrupt enable same definition as ie7 but used during the seventh sample. 0 r/w ie6 26 7th sample is end of sequence same definition as end7 but used during the seventh sample. 0 r/w end6 25 7th sample dif f input select same definition as d7 but used during the seventh sample. 0 r/w d6 24 6th sample t emp sensor select same definition as ts7 but used during the sixth sample. 0 r/w ts5 23 6th sample interrupt enable same definition as ie7 but used during the sixth sample. 0 r/w ie5 22 6th sample is end of sequence same definition as end7 but used during the sixth sample. 0 r/w end5 21 6th sample dif f input select same definition as d7 but used during the sixth sample. 0 r/w d5 20 5th sample t emp sensor select same definition as ts7 but used during the fifth sample. 0 r/w ts4 19 5th sample interrupt enable same definition as ie7 but used during the fifth sample. 0 r/w ie4 18 5th sample is end of sequence same definition as end7 but used during the fifth sample. 0 r/w end4 17 5th sample dif f input select same definition as d7 but used during the fifth sample. 0 r/w d4 16 4th sample t emp sensor select same definition as ts7 but used during the fourth sample. 0 r/w ts3 15 4th sample interrupt enable same definition as ie7 but used during the fourth sample. 0 r/w ie3 14 4th sample is end of sequence same definition as end7 but used during the fourth sample. 0 r/w end3 13 4th sample dif f input select same definition as d7 but used during the fourth sample. 0 r/w d3 12 3rd sample t emp sensor select same definition as ts7 but used during the third sample. 0 r/w ts2 1 1 september 02, 2007 286 preliminary analog-to-digital converter (adc) description reset t ype name bit/field 3rd sample interrupt enable same definition as ie7 but used during the third sample. 0 r/w ie2 10 3rd sample is end of sequence same definition as end7 but used during the third sample. 0 r/w end2 9 3rd sample dif f input select same definition as d7 but used during the third sample. 0 r/w d2 8 2nd sample t emp sensor select same definition as ts7 but used during the second sample. 0 r/w ts1 7 2nd sample interrupt enable same definition as ie7 but used during the second sample. 0 r/w ie1 6 2nd sample is end of sequence same definition as end7 but used during the second sample. 0 r/w end1 5 2nd sample dif f input select same definition as d7 but used during the second sample. 0 r/w d1 4 1st sample t emp sensor select same definition as ts7 but used during the first sample. 0 r/w ts0 3 1st sample interrupt enable same definition as ie7 but used during the first sample. 0 r/w ie0 2 1st sample is end of sequence same definition as end7 but used during the first sample. since this sequencer has only one entry , this bit must be set. 0 r/w end0 1 1st sample dif f input select same definition as d7 but used during the first sample. 0 r/w d0 0 287 september 02, 2007 preliminary lm3s8962 microcontroller register 13: adc sample sequence result fifo 0 (adcssfifo0), offset 0x048 register 14: adc sample sequence result fifo 1 (adcssfifo1), offset 0x068 register 15: adc sample sequence result fifo 2 (adcssfifo2), offset 0x088 register 16: adc sample sequence result fifo 3 (adcssfifo3), offset 0x0a8 this register contains the conversion results for samples collected with the sample sequencer (the adcssfifo0 register is used for sample sequencer 0, adcssfifo1 for sequencer 1, adcssfifo2 for sequencer 2, and adcssfifo3 for sequencer 3). reads of this register return conversion result data in the order sample 0, sample 1, and so on, until the fifo is empty . if the fifo is not properly handled by software, overflow and underflow conditions are registered in the adcost a t and adcust a t registers. adc sample sequence result fifo 0 (adcssfifo0) base 0x4003.8000 of fset 0x048 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 da t a reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:10 conversion result data 0x00 ro da t a 9:0 september 02, 2007 288 preliminary analog-to-digital converter (adc) register 17: adc sample sequence fifo 0 status (adcssfst a t0), offset 0x04c register 18: adc sample sequence fifo 1 status (adcssfst a t1), offset 0x06c register 19: adc sample sequence fifo 2 status (adcssfst a t2), offset 0x08c register 20: adc sample sequence fifo 3 status (adcssfst a t3), offset 0x0ac this register provides a window into the sample sequencer , providing full/empty status information as well as the positions of the head and tail pointers. the reset value of 0x100 indicates an empty fifo. the adcssfst a t0 register provides status on fif0, adcssfst a t1 on fifo1, adcssfst a t2 on fifo2, and adcssfst a t3 on fifo3. adc sample sequence fifo 0 status (adcssfst a t0) base 0x4003.8000 of fset 0x04c t ype ro, reset 0x0000.0100 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 tptr hptr empty reserved full reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:13 fifo full when set, indicates that the fifo is currently full. 0 ro full 12 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 1 1:9 fifo empty when set, indicates that the fifo is currently empty . 1 ro empty 8 fifo head pointer this field contains the current "head" pointer index for the fifo, that is, the next entry to be written. 0x00 ro hptr 7:4 fifo t ail pointer this field contains the current "tail" pointer index for the fifo, that is, the next entry to be read. 0x00 ro tptr 3:0 289 september 02, 2007 preliminary lm3s8962 microcontroller register 21: adc sample sequence input multiplexer select 1 (adcssmux1), offset 0x060 register 22: adc sample sequence input multiplexer select 2 (adcssmux2), offset 0x080 this register defines the analog input configuration for each sample in a sequence executed with sample sequencer 1 or 2. these registers are 16-bits wide and contain information for four possible samples. see the adcssmux0 register on page 283 for detailed bit descriptions. adc sample sequence input multiplexer select 1 (adcssmux1) base 0x4003.8000 of fset 0x060 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 mux0 reserved mux1 reserved mux2 reserved mux3 reserved r/w r/w ro ro r/w r/w ro ro r/w r/w ro ro r/w r/w ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:14 4th sample input select 0 r/w mux3 13:12 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 1 1:10 3rd sample input select 0 r/w mux2 9:8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 7:6 2nd sample input select 0 r/w mux1 5:4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3:2 1st sample input select 0 r/w mux0 1:0 september 02, 2007 290 preliminary analog-to-digital converter (adc) register 23: adc sample sequence control 1 (adcssctl1), offset 0x064 register 24: adc sample sequence control 2 (adcssctl2), offset 0x084 these registers contain the configuration information for each sample for a sequence executed with sample sequencer 1 or 2. when configuring a sample sequence, the end bit must be set at some point, whether it be after the first sample, last sample, or any sample in between. this register is 16-bits wide and contains information for four possible samples. see the adcssctl0 register on page 285 for detailed bit descriptions. adc sample sequence control 1 (adcssctl1) base 0x4003.8000 of fset 0x064 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 d0 end0 ie0 ts0 d1 end1 ie1 ts1 d2 end2 ie2 ts2 d3 end3 ie3 ts3 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:16 4th sample t emp sensor select same definition as ts7 but used during the fourth sample. 0 r/w ts3 15 4th sample interrupt enable same definition as ie7 but used during the fourth sample. 0 r/w ie3 14 4th sample is end of sequence same definition as end7 but used during the fourth sample. 0 r/w end3 13 4th sample dif f input select same definition as d7 but used during the fourth sample. 0 r/w d3 12 3rd sample t emp sensor select same definition as ts7 but used during the third sample. 0 r/w ts2 1 1 3rd sample interrupt enable same definition as ie7 but used during the third sample. 0 r/w ie2 10 3rd sample is end of sequence same definition as end7 but used during the third sample. 0 r/w end2 9 3rd sample dif f input select same definition as d7 but used during the third sample. 0 r/w d2 8 291 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field 2nd sample t emp sensor select same definition as ts7 but used during the second sample. 0 r/w ts1 7 2nd sample interrupt enable same definition as ie7 but used during the second sample. 0 r/w ie1 6 2nd sample is end of sequence same definition as end7 but used during the second sample. 0 r/w end1 5 2nd sample dif f input select same definition as d7 but used during the second sample. 0 r/w d1 4 1st sample t emp sensor select same definition as ts7 but used during the first sample. 0 r/w ts0 3 1st sample interrupt enable same definition as ie7 but used during the first sample. 0 r/w ie0 2 1st sample is end of sequence same definition as end7 but used during the first sample. since this sequencer has only one entry , this bit must be set. 0 r/w end0 1 1st sample dif f input select same definition as d7 but used during the first sample. 0 r/w d0 0 september 02, 2007 292 preliminary analog-to-digital converter (adc) register 25: adc sample sequence input multiplexer select 3 (adcssmux3), offset 0x0a0 this register defines the analog input configuration for each sample in a sequence executed with sample sequencer 3. this register is 4-bits wide and contains information for one possible sample. see the adcssmux0 register on page 283 for detailed bit descriptions. adc sample sequence input multiplexer select 3 (adcssmux3) base 0x4003.8000 of fset 0x0a0 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 mux0 reserved r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:2 1st sample input select 0 r/w mux0 1:0 293 september 02, 2007 preliminary lm3s8962 microcontroller register 26: adc sample sequence control 3 (adcssctl3), offset 0x0a4 this register contains the configuration information for each sample for a sequence executed with sample sequencer 3. the end bit is always set since there is only one sample in this sequencer . this register is 4-bits wide and contains information for one possible sample. see the adcssctl0 register on page 285 for detailed bit descriptions. adc sample sequence control 3 (adcssctl3) base 0x4003.8000 of fset 0x0a4 t ype r/w , reset 0x0000.0002 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 d0 end0 ie0 ts0 reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:4 1st sample t emp sensor select same definition as ts7 but used during the first sample. 0 r/w ts0 3 1st sample interrupt enable same definition as ie7 but used during the first sample. 0 r/w ie0 2 1st sample is end of sequence same definition as end7 but used during the first sample. since this sequencer has only one entry , this bit must be set. 1 r/w end0 1 1st sample dif f input select same definition as d7 but used during the first sample. 0 r/w d0 0 september 02, 2007 294 preliminary analog-to-digital converter (adc) register 27: adc t est mode loopback (adctmlb), offset 0x100 this register provides loopback operation within the digital logic of the adc, which can be useful in debugging software without having to provide actual analog stimulus. this test mode is entered by writing a value of 0x0000.0001 to this register . when data is read from the fifo in loopback mode, the read-only portion of this register is returned. read-only register adc t est mode loopback (adctmlb) base 0x4003.8000 of fset 0x100 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 mux ts diff cont cnt reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:10 continuous sample counter continuous sample counter that is initialized to 0 and counts each sample as it processed. this helps provide a unique value for the data received. 0x0 ro cnt 9:6 continuation sample indicator when set, indicates that this is a continuation sample. for example, if two sequencers were to run back-to-back, this indicates that the controller kept continuously sampling at full rate. 0 ro cont 5 dif ferential sample indicator when set, indicates that this is a dif ferential sample. 0 ro diff 4 t emp sensor sample indicator when set, indicates that this is a temperature sensor sample. 0 ro ts 3 analog input indicator indicates which analog input is to be sampled. 0x0 ro mux 2:0 295 september 02, 2007 preliminary lm3s8962 microcontroller w rite-only register adc t est mode loopback (adctmlb) base 0x4003.8000 of fset 0x100 t ype wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 lb reserved wo ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 loopback mode enable when set, forces a loopback within the digital block to provide information on input and unique numbering. the 10-bit loopback data is defined as shown in the read for bits 9:0 above. 0 wo lb 0 september 02, 2007 296 preliminary analog-to-digital converter (adc) 13 universal asynchronous receivers/t ransmitters (uart s) the stellaris ? universal asynchronous receiver/t ransmitter (uar t) provides fully programmable, 16c550-type serial interface characteristics. the lm3s8962 controller is equipped with two uar t modules. each uar t has the following features: separate transmit and receive fifos programmable fifo length, including 1-byte deep operation providing conventional double-buf fered interface fifo trigger levels of 1/8, 1/4, 1/2, 3/4, and 7/8 programmable baud-rate generator allowing rates up to 3.125 mbps standard asynchronous communication bits for start, stop, and parity false start bit detection line-break generation and detection fully programmable serial interface characteristics: C 5, 6, 7, or 8 data bits C even, odd, stick, or no-parity bit generation/detection C 1 or 2 stop bit generation irda serial-ir (sir) encoder/decoder providing: C programmable use of irda serial infrared (sir) or uar t input/output C support of irda sir encoder/decoder functions for data rates up to 1 15.2 kbps half-duplex C support of normal 3/16 and low-power (1.41-2.23 s) bit durations C programmable internal clock generator enabling division of reference clock by 1 to 256 for low-power mode bit duration 297 september 02, 2007 preliminary lm3s8962 microcontroller 13.1 block diagram figure 13-1. uart module block diagram 13.2 functional description each stellaris ? uar t performs the functions of parallel-to-serial and serial-to-parallel conversions. it is similar in functionality to a 16c550 uar t , but is not register compatible. the uar t is configured for transmit and/or receive via the txe and rxe bits of the uart control (uartctl) register (see page 316 ). t ransmit and receive are both enabled out of reset. before any control registers are programmed, the uar t must be disabled by clearing the uarten bit in uartctl . if the uar t is disabled during a tx or rx operation, the current transaction is completed prior to the uar t stopping. the uar t peripheral also includes a serial ir (sir) encoder/decoder block that can be connected to an infrared transceiver to implement an irda sir physical layer . the sir function is programmed using the uar tctl register . 13.2.1 t ransmit/receive logic the transmit logic performs parallel-to-serial conversion on the data read from the transmit fifo. the control logic outputs the serial bit stream beginning with a start bit, and followed by the data september 02, 2007 298 preliminary universal asynchronous receivers/t ransmitters (uar t s) receiver t ransmitter system clock control / status uar trsr / ecr uar tfr uar tlcrh uar tctl uar tilpr interrupt control uar tifls uar tim uar tmis uar tris uar ticr baud rate generator uar tibrd uar tfbrd identification registers uar tpcellid 0 uar tpcellid 1 uar tpcellid 2 uar tpcellid 3 uar tperiphid 0 uar tperiphid 1 uar tperiphid 2 uar tperiphid 3 uar t periphid 4 uar tperiphid 5 uar tperiphid 6 uar tperiphid 7 uar tdr txfifo 16 x 8 . . . rxfifo 16 x 8 . . . interrupt untx unrx bits (lsb first), parity bit, and the stop bits according to the programmed configuration in the control registers. see figure 13-2 on page 299 for details. the receive logic performs serial-to-parallel conversion on the received bit stream after a valid start pulse has been detected. overrun, parity , frame error checking, and line-break detection are also performed, and their status accompanies the data that is written to the receive fifo. figure 13-2. uart character frame 13.2.2 baud-rate generation the baud-rate divisor is a 22-bit number consisting of a 16-bit integer and a 6-bit fractional part. the number formed by these two values is used by the baud-rate generator to determine the bit period. having a fractional baud-rate divider allows the uar t to generate all the standard baud rates. the 16-bit integer is loaded through the uart integer baud-rate divisor (uartibrd) register (see page 312 ) and the 6-bit fractional part is loaded with the uart fractional baud-rate divisor (uartfbrd) register (see page 313 ). the baud-rate divisor (brd) has the following relationship to the system clock (where brdi is the integer part of the brd and brdf is the fractional part, separated by a decimal place.): brd = brdi + brdf = sysclk / (16 * baud rate) the 6-bit fractional number (that is to be loaded into the divfrac bit field in the uartfbrd register) can be calculated by taking the fractional part of the baud-rate divisor , multiplying it by 64, and adding 0.5 to account for rounding errors: uartfbrd[divfrac] = integer(brdf * 64 + 0.5) the uar t generates an internal baud-rate reference clock at 16x the baud-rate (referred to as baud16 ). this reference clock is divided by 16 to generate the transmit clock, and is used for error detection during receive operations. along with the uart line control, high byte (uartlcrh) register (see page 314 ), the uartibrd and uartfbrd registers form an internal 30-bit register . this internal register is only updated when a write operation to uartlcrh is performed, so any changes to the baud-rate divisor must be followed by a write to the uartlcrh register for the changes to take ef fect. t o update the baud-rate registers, there are four possible sequences: uartibrd write, uartfbrd write, and uartlcrh write uartfbrd write, uartibrd write, and uartlcrh write uartibrd write and uartlcrh write uartfbrd write and uartlcrh write 299 september 02, 2007 preliminary lm3s8962 microcontroller 1 0 5 - 8 d a t a b i t s l s b m s b p a r i t y b i t i f e n a b l e d 1 - 2 s t o p b i t s u n t x n s t a r t 13.2.3 data t ransmission data received or transmitted is stored in two 16-byte fifos, though the receive fifo has an extra four bits per character for status information. for transmission, data is written into the transmit fifo. if the uar t is enabled, it causes a data frame to start transmitting with the parameters indicated in the uartlcrh register . data continues to be transmitted until there is no data left in the transmit fifo. the busy bit in the uart flag (uartfr) register (see page 309 ) is asserted as soon as data is written to the transmit fifo (that is, if the fifo is non-empty) and remains asserted while data is being transmitted. the busy bit is negated only when the transmit fifo is empty , and the last character has been transmitted from the shift register , including the stop bits. the uar t can indicate that it is busy even though the uar t may no longer be enabled. when the receiver is idle (the unrx is continuously 1) and the data input goes low (a start bit has been received), the receive counter begins running and data is sampled on the eighth cycle of baud16 (described in t ransmit/receive logic on page 298 ). the start bit is valid if unrx is still low on the eighth cycle of baud16 , otherwise a false start bit is detected and it is ignored. start bit errors can be viewed in the uart receive status (uartrsr) register (see page 307 ). if the start bit was valid, successive data bits are sampled on every 16th cycle of baud16 (that is, one bit period later) according to the programmed length of the data characters. the parity bit is then checked if parity mode was enabled. data length and parity are defined in the uartlcrh register . lastly , a valid stop bit is confirmed if unrx is high, otherwise a framing error has occurred. when a full word is received, the data is stored in the receive fifo, with any error bits associated with that word. 13.2.4 serial ir (sir) the uar t peripheral includes an irda serial-ir (sir) encoder/decoder block. the irda sir block provides functionality that converts between an asynchronous uar t data stream, and half-duplex serial sir interface. no analog processing is performed on-chip. the role of the sir block is to provide a digital encoded output, and decoded input to the uar t . the uar t signal pins can be connected to an infrared transceiver to implement an irda sir physical layer link. the sir block has two modes of operation: in normal irda mode, a zero logic level is transmitted as high pulse of 3/16th duration of the selected baud rate bit period on the output pin, while logic one levels are transmitted as a static low signal. these levels control the driver of an infrared transmitter , sending a pulse of light for each zero. on the reception side, the incoming light pulses energize the photo transistor base of the receiver , pulling its output low . this drives the uar t input pin low . in low-power irda mode, the width of the transmitted infrared pulse is set to three times the period of the internally generated irlpbaud16 signal (1.63 s, assuming a nominal 1.8432 mhz frequency) by changing the appropriate bit in the uartcr register . figure 13-3 on page 301 shows the uar t transmit and receive signals, with and without irda modulation. september 02, 2007 300 preliminary universal asynchronous receivers/t ransmitters (uar t s) figure 13-3. irda data modulation in both normal and low-power irda modes: during transmission, the uar t data bit is used as the base for encoding during reception, the decoded bits are transferred to the uar t receive logic the irda sir physical layer specifies a half-duplex communication link, with a minimum 10 ms delay between transmission and reception. this delay must be generated by software because it is not automatically supported by the uar t . the delay is required because the infrared receiver electronics might become biased, or even saturated from the optical power coupled from the adjacent transmitter led. this delay is known as latency , or receiver setup time. 13.2.5 fifo operation the uar t has two 16-entry fifos; one for transmit and one for receive. both fifos are accessed via the uart data (uartdr) register (see page 305 ). read operations of the uartdr register return a 12-bit value consisting of 8 data bits and 4 error flags while write operations place 8-bit data in the transmit fifo. out of reset, both fifos are disabled and act as 1-byte-deep holding registers. the fifos are enabled by setting the fen bit in uartlcrh ( page 314 ). fifo status can be monitored via the uart flag (uartfr) register (see page 309 ) and the uart receive status (uartrsr) register . hardware monitors empty , full and overrun conditions. the uartfr register contains empty and full flags ( txfe , txff , rxfe , and rxff bits) and the uartrsr register shows overrun status via the oe bit. the trigger points at which the fifos generate interrupts is controlled via the uart interrupt fifo level select (uartifls) register (see page 318 ). both fifos can be individually configured to trigger interrupts at dif ferent levels. a vailable configurations include 1/8, ?, ?, ?, and 7/8. for example, if the ? option is selected for the receive fifo, the uar t generates a receive interrupt after 4 data bytes are received. out of reset, both fifos are configured to trigger an interrupt at the ? mark. 13.2.6 interrupts the uar t can generate interrupts when the following conditions are observed: overrun error break error 301 september 02, 2007 preliminary lm3s8962 microcontroller 1 0 1 0 0 0 1 1 0 1 d a t a b i t s 1 0 1 0 0 0 1 1 0 1 d a t a b i t s s t a r t b i t s t a r t s t o p b i t p e r i o d b i t p e r i o d 3 1 6 u n t x u n t x w i t h i r d a u n r x w i t h i r d a unrx s t o p b i t parity error framing error receive t imeout t ransmit (when condition defined in the txiflsel bit in the uartifls register is met) receive (when condition defined in the rxiflsel bit in the uartifls register is met) all of the interrupt events are ored together before being sent to the interrupt controller , so the uar t can only generate a single interrupt request to the controller at any given time. software can service multiple interrupt events in a single interrupt service routine by reading the uart masked interrupt status (uartmis) register (see page 323 ). the interrupt events that can trigger a controller-level interrupt are defined in the uart interrupt mask (uartim ) register (see page 320 ) by setting the corresponding im bit to 1. if interrupts are not used, the raw interrupt status is always visible via the uart raw interrupt status (uartris) register (see page 322 ). interrupts are always cleared (for both the uartmis and uartris registers) by setting the corresponding bit in the uart interrupt clear (uarticr) register (see page 324 ). the receive timeout interrupt is asserted when the receive fifo is not empty , and no further data is received over a 32-bit period. the receive timeout interrupt is cleared either when the fifo becomes empty through reading all the data (or by reading the holding register), or when a 1 is written to the corresponding bit in the uarticr register . 13.2.7 loopback operation the uar t can be placed into an internal loopback mode for diagnostic or debug work. this is accomplished by setting the lbe bit in the uartctl register (see page 316 ). in loopback mode, data transmitted on untx is received on the unrx input. 13.2.8 irda sir block the irda sir block contains an irda serial ir (sir) protocol encoder/decoder . when enabled, the sir block uses the untx and unrx pins for the sir protocol, which should be connected to an ir transceiver . the sir block can receive and transmit, but it is only half-duplex so it cannot do both at the same time. t ransmission must be stopped before data can be received. the irda sir physical layer specifies a minimum 10-ms delay between transmission and reception. 13.3 initialization and configuration t o use the uar t s, the peripheral clock must be enabled by setting the uart0 or uart1 bits in the rcgc1 register . this section discusses the steps that are required for using a uar t module. for this example, the system clock is assumed to be 20 mhz and the desired uar t configuration is: 1 15200 baud rate data length of 8 bits one stop bit september 02, 2007 302 preliminary universal asynchronous receivers/t ransmitters (uar t s) no parity fifos disabled no interrupts the first thing to consider when programming the uar t is the baud-rate divisor (brd), since the uartibrd and uartfbrd registers must be written before the uartlcrh register . using the equation described in baud-rate generation on page 299 , the brd can be calculated: brd = 20,000,000 / (16 * 115,200) = 10.8507 which means that the divint field of the uartibrd register (see page 312 ) should be set to 10. the value to be loaded into the uartfbrd register (see page 313 ) is calculated by the equation: uartfbrd[divfrac] = integer(0.8507 * 64 + 0.5) = 54 with the brd values in hand, the uar t configuration is written to the module in the following order: 1. disable the uar t by clearing the uarten bit in the uartctl register . 2. w rite the integer portion of the brd to the uartibrd register . 3. w rite the fractional portion of the brd to the uartfbrd register . 4. w rite the desired serial parameters to the uartlcrh register (in this case, a value of 0x0000.0060). 5. enable the uar t by setting the uarten bit in the uartctl register . 13.4 register map t able 13-1 on page 303 lists the uar t registers. the of fset listed is a hexadecimal increment to the register s address, relative to that uar t s base address: uar t0: 0x4000.c000 uar t1: 0x4000.d000 note: the uar t must be disabled (see the uarten bit in the uartctl register on page 316 ) before any of the control registers are reprogrammed. when the uar t is disabled during a tx or rx operation, the current transaction is completed prior to the uar t stopping. t able 13-1. uart register map see page description reset t ype name offset 305 uar t data 0x0000.0000 r/w uar tdr 0x000 307 uar t receive status/error clear 0x0000.0000 r/w uar trsr/uar tecr 0x004 309 uar t flag 0x0000.0090 ro uar tfr 0x018 311 uar t irda low-power register 0x0000.0000 r/w uar tilpr 0x020 312 uar t integer baud-rate divisor 0x0000.0000 r/w uar tibrd 0x024 303 september 02, 2007 preliminary lm3s8962 microcontroller see page description reset t ype name offset 313 uar t fractional baud-rate divisor 0x0000.0000 r/w uar tfbrd 0x028 314 uar t line control 0x0000.0000 r/w uar tlcrh 0x02c 316 uar t control 0x0000.0300 r/w uar tctl 0x030 318 uar t interrupt fifo level select 0x0000.0012 r/w uar tifls 0x034 320 uar t interrupt mask 0x0000.0000 r/w uar tim 0x038 322 uar t raw interrupt status 0x0000.000f ro uar tris 0x03c 323 uar t masked interrupt status 0x0000.0000 ro uar tmis 0x040 324 uar t interrupt clear 0x0000.0000 w1c uar ticr 0x044 326 uar t peripheral identification 4 0x0000.0000 ro uar tperiphid4 0xfd0 327 uar t peripheral identification 5 0x0000.0000 ro uar tperiphid5 0xfd4 328 uar t peripheral identification 6 0x0000.0000 ro uar tperiphid6 0xfd8 329 uar t peripheral identification 7 0x0000.0000 ro uar tperiphid7 0xfdc 330 uar t peripheral identification 0 0x0000.001 1 ro uar tperiphid0 0xfe0 331 uar t peripheral identification 1 0x0000.0000 ro uar tperiphid1 0xfe4 332 uar t peripheral identification 2 0x0000.0018 ro uar tperiphid2 0xfe8 333 uar t peripheral identification 3 0x0000.0001 ro uar tperiphid3 0xfec 334 uar t primecell identification 0 0x0000.000d ro uar tpcellid0 0xff0 335 uar t primecell identification 1 0x0000.00f0 ro uar tpcellid1 0xff4 336 uar t primecell identification 2 0x0000.0005 ro uar tpcellid2 0xff8 337 uar t primecell identification 3 0x0000.00b1 ro uar tpcellid3 0xffc 13.5 register descriptions the remainder of this section lists and describes the uar t registers, in numerical order by address of fset. september 02, 2007 304 preliminary universal asynchronous receivers/t ransmitters (uar t s) register 1: uart data (uartdr), offset 0x000 this register is the data register (the interface to the fifos). when fifos are enabled, data written to this location is pushed onto the transmit fifo. if fifos are disabled, data is stored in the transmitter holding register (the bottom word of the transmit fifo). a write to this register initiates a transmission from the uar t . for received data, if the fifo is enabled, the data byte and the 4-bit status (break, frame, parity , and overrun) is pushed onto the 12-bit wide receive fifo. if fifos are disabled, the data byte and status are stored in the receiving holding register (the bottom word of the receive fifo). the received data can be retrieved by reading this register . uar t data (uar tdr) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x000 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 da t a fe pe be oe reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:12 uar t overrun error the oe values are defined as follows: description v alue there has been no data loss due to a fifo overrun. 0 new data was received when the fifo was full, resulting in data loss. 1 0 ro oe 1 1 uar t break error this bit is set to 1 when a break condition is detected, indicating that the receive data input was held low for longer than a full-word transmission time (defined as start, data, parity , and stop bits). in fifo mode, this error is associated with the character at the top of the fifo. when a break occurs, only one 0 character is loaded into the fifo. the next character is only enabled after the received data input goes to a 1 (marking state) and the next valid start bit is received. 0 ro be 10 305 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field uar t parity error this bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the uartlcrh register . in fifo mode, this error is associated with the character at the top of the fifo. 0 ro pe 9 uar t framing error this bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). 0 ro fe 8 data t ransmitted or received when written, the data that is to be transmitted via the uar t . when read, the data that was received by the uar t . 0 r/w da t a 7:0 september 02, 2007 306 preliminary universal asynchronous receivers/t ransmitters (uar t s) register 2: uart receive status/error clear (uartrsr/uartecr), offset 0x004 the uartrsr/uartecr register is the receive status register/error clear register . in addition to the uartdr register , receive status can also be read from the uartrsr register . if the status is read from this register , then the status information corresponds to the entry read from uartdr prior to reading uartrsr . the status information for overrun is set immediately when an overrun condition occurs. a write of any value to the uartecr register clears the framing, parity , break, and overrun errors. all the bits are cleared to 0 on reset. read-only receive status (uartrsr) register uar t receive status/error clear (uar trsr/uar tecr) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x004 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 fe pe be oe reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. the uartrsr register cannot be written. 0 ro reserved 31:4 uar t overrun error when this bit is set to 1, data is received and the fifo is already full. this bit is cleared to 0 by a write to uartecr . the fifo contents remain valid since no further data is written when the fifo is full, only the contents of the shift register are overwritten. the cpu must now read the data in order to empty the fifo. 0 ro oe 3 uar t break error this bit is set to 1 when a break condition is detected, indicating that the received data input was held low for longer than a full-word transmission time (defined as start, data, parity , and stop bits). this bit is cleared to 0 by a write to uartecr . in fifo mode, this error is associated with the character at the top of the fifo. when a break occurs, only one 0 character is loaded into the fifo. the next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received. 0 ro be 2 307 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field uar t parity error this bit is set to 1 when the parity of the received data character does not match the parity defined by bits 2 and 7 of the uartlcrh register . this bit is cleared to 0 by a write to uartecr . 0 ro pe 1 uar t framing error this bit is set to 1 when the received character does not have a valid stop bit (a valid stop bit is 1). this bit is cleared to 0 by a write to uartecr . in fifo mode, this error is associated with the character at the top of the fifo. 0 ro fe 0 w rite-only error clear (uartecr) register uar t receive status/error clear (uar trsr/uar tecr) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x004 t ype wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 da t a reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 wo reserved 31:8 error clear a write to this register of any data clears the framing, parity , break, and overrun flags. 0 wo da t a 7:0 september 02, 2007 308 preliminary universal asynchronous receivers/t ransmitters (uar t s) register 3: uart flag (uartfr), offset 0x018 the uartfr register is the flag register . after reset, the txff , rxff , and busy bits are 0, and txfe and rxfe bits are 1. uar t flag (uar tfr) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x018 t ype ro, reset 0x0000.0090 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved busy rxfe txff rxff txfe reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:8 uar t t ransmit fifo empty the meaning of this bit depends on the state of the fen bit in the uartlcrh register . if the fifo is disabled ( fen is 0), this bit is set when the transmit holding register is empty . if the fifo is enabled ( fen is 1), this bit is set when the transmit fifo is empty . 1 ro txfe 7 uar t receive fifo full the meaning of this bit depends on the state of the fen bit in the uartlcrh register . if the fifo is disabled, this bit is set when the receive holding register is full. if the fifo is enabled, this bit is set when the receive fifo is full. 0 ro rxff 6 uar t t ransmit fifo full the meaning of this bit depends on the state of the fen bit in the uartlcrh register . if the fifo is disabled, this bit is set when the transmit holding register is full. if the fifo is enabled, this bit is set when the transmit fifo is full. 0 ro txff 5 309 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field uar t receive fifo empty the meaning of this bit depends on the state of the fen bit in the uartlcrh register . if the fifo is disabled, this bit is set when the receive holding register is empty . if the fifo is enabled, this bit is set when the receive fifo is empty . 1 ro rxfe 4 uar t busy when this bit is 1, the uar t is busy transmitting data. this bit remains set until the complete byte, including all stop bits, has been sent from the shift register . this bit is set as soon as the transmit fifo becomes non-empty (regardless of whether uar t is enabled). 0 ro busy 3 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 2:0 september 02, 2007 310 preliminary universal asynchronous receivers/t ransmitters (uar t s) register 4: uart irda low-power register (uartilpr), offset 0x020 the uartilpr register is an 8-bit read/write register that stores the low-power counter divisor value used to generate the irlpbaud16 signal by dividing down the system clock (sysclk). all the bits are cleared to 0 when reset. the irlpbaud16 internal signal is generated by dividing down the uartclk signal according to the low-power divisor value written to uartilpr . the low-power divisor value is calculated as follows: ilpdvsr = sysclk / f irlpbaud16 where f irlpbaud16 is nominally 1.8432 mhz. irlpbaud16 is an internal signal used for sir pulse generation when low-power mode is used. y ou must choose the divisor so that 1.42 mhz < f irlpbaud16 < 2.12 mhz, which results in a low-power pulse duration of 1.41C2.1 1 s (three times the period of irlpbaud16 ). the minimum frequency of irlpbaud16 ensures that pulses less than one period of irlpbaud16 are rejected, but that pulses greater than 1.4 s are accepted as valid pulses. note: zero is an illegal value. programming a zero value results in no irlpbaud16 pulses being generated. uar t irda low-power register (uar tilpr) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x020 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ilpdvsr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:8 irda low-power divisor this is an 8-bit low-power divisor value. 0x00 r/w ilpdvsr 7:0 31 1 september 02, 2007 preliminary lm3s8962 microcontroller register 5: uart integer baud-rate divisor (uartibrd), offset 0x024 the uartibrd register is the integer part of the baud-rate divisor value. all the bits are cleared on reset. the minimum possible divide ratio is 1 (when uartibrd =0), in which case the uartfbrd register is ignored. when changing the uartibrd register , the new value does not take ef fect until transmission/reception of the current character is complete. any changes to the baud-rate divisor must be followed by a write to the uartlcrh register . see baud-rate generation on page 299 for configuration details. uar t integer baud-rate divisor (uar tibrd) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x024 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 divint r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:16 integer baud-rate divisor 0x0000 r/w divint 15:0 september 02, 2007 312 preliminary universal asynchronous receivers/t ransmitters (uar t s) register 6: uart fractional baud-rate divisor (uartfbrd), offset 0x028 the uartfbrd register is the fractional part of the baud-rate divisor value. all the bits are cleared on reset. when changing the uartfbrd register , the new value does not take ef fect until transmission/reception of the current character is complete. any changes to the baud-rate divisor must be followed by a write to the uartlcrh register . see baud-rate generation on page 299 for configuration details. uar t fractional baud-rate divisor (uar tfbrd) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x028 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 divfrac reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:6 fractional baud-rate divisor 0x000 r/w divfrac 5:0 313 september 02, 2007 preliminary lm3s8962 microcontroller register 7: uart line control (uartlcrh), offset 0x02c the uartlcrh register is the line control register . serial parameters such as data length, parity , and stop bit selection are implemented in this register . when updating the baud-rate divisor ( uartibrd and/or uartifrd ), the uartlcrh register must also be written. the write strobe for the baud-rate divisor registers is tied to the uartlcrh register . uar t line control (uar tlcrh) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x02c t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 brk pen eps stp2 fen wlen sps reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:8 uar t stick parity select when bits 1, 2, and 7 of uartlcrh are set, the parity bit is transmitted and checked as a 0. when bits 1 and 7 are set and 2 is cleared, the parity bit is transmitted and checked as a 1. when this bit is cleared, stick parity is disabled. 0 r/w sps 7 uar t w ord length the bits indicate the number of data bits transmitted or received in a frame as follows: description v alue 8 bits 0x3 7 bits 0x2 6 bits 0x1 5 bits (default) 0x0 0 r/w wlen 6:5 uar t enable fifos if this bit is set to 1, transmit and receive fifo buf fers are enabled (fifo mode). when cleared to 0, fifos are disabled (character mode). the fifos become 1-byte-deep holding registers. 0 r/w fen 4 september 02, 2007 314 preliminary universal asynchronous receivers/t ransmitters (uar t s) description reset t ype name bit/field uar t t wo stop bits select if this bit is set to 1, two stop bits are transmitted at the end of a frame. the receive logic does not check for two stop bits being received. 0 r/w stp2 3 uar t even parity select if this bit is set to 1, even parity generation and checking is performed during transmission and reception, which checks for an even number of 1s in data and parity bits. when cleared to 0, then odd parity is performed, which checks for an odd number of 1s. this bit has no ef fect when parity is disabled by the pen bit. 0 r/w eps 2 uar t parity enable if this bit is set to 1, parity checking and generation is enabled; otherwise, parity is disabled and no parity bit is added to the data frame. 0 r/w pen 1 uar t send break if this bit is set to 1, a low level is continually output on the untx output, after completing transmission of the current character . for the proper execution of the break command, the software must set this bit for at least two frames (character periods). for normal use, this bit must be cleared to 0. 0 r/w brk 0 315 september 02, 2007 preliminary lm3s8962 microcontroller register 8: uart control (uartctl), offset 0x030 the uartctl register is the control register . all the bits are cleared on reset except for the transmit enable (txe) and receive enable (rxe) bits, which are set to 1. t o enable the uar t module, the uarten bit must be set to 1. if software requires a configuration change in the module, the uarten bit must be cleared before the configuration changes are written. if the uar t is disabled during a transmit or receive operation, the current transaction is completed prior to the uar t stopping. uar t control (uar tctl) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x030 t ype r/w , reset 0x0000.0300 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 uar ten siren sirlp reserved lbe txe rxe reserved r/w r/w r/w ro ro ro ro r/w r/w r/w ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:10 uar t receive enable if this bit is set to 1, the receive section of the uar t is enabled. when the uar t is disabled in the middle of a receive, it completes the current character before stopping. note: t o enable reception, the uarten bit must also be set. 1 r/w rxe 9 uar t t ransmit enable if this bit is set to 1, the transmit section of the uar t is enabled. when the uar t is disabled in the middle of a transmission, it completes the current character before stopping. note: t o enable transmission, the uarten bit must also be set. 1 r/w txe 8 uar t loop back enable if this bit is set to 1, the untx path is fed through the unrx path. 0 r/w lbe 7 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 6:3 september 02, 2007 316 preliminary universal asynchronous receivers/t ransmitters (uar t s) description reset t ype name bit/field uar t sir low power mode this bit selects the irda encoding mode. if this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3/16th of the bit period. if this bit is set to 1, low-level bits are transmitted with a pulse width which is 3 times the period of the irlpbaud16 input signal, regardless of the selected bit rate. setting this bit uses less power , but might reduce transmission distances. see page 311 for more information. 0 r/w sirlp 2 uar t sir enable if this bit is set to 1, the irda sir block is enabled, and the uar t will transmit and receive data using sir protocol. 0 r/w siren 1 uar t enable if this bit is set to 1, the uar t is enabled. when the uar t is disabled in the middle of transmission or reception, it completes the current character before stopping. 0 r/w uar ten 0 317 september 02, 2007 preliminary lm3s8962 microcontroller register 9: uart interrupt fifo level select (uartifls), offset 0x034 the uartifls register is the interrupt fifo level select register . y ou can use this register to define the fifo level at which the txris and rxris bits in the uartris register are triggered. the interrupts are generated based on a transition through a level rather than being based on the level. that is, the interrupts are generated when the fill level progresses through the trigger level. for example, if the receive trigger level is set to the half-way mark, the interrupt is triggered as the module is receiving the 9th character . out of reset, the txiflsel and rxiflsel bits are configured so that the fifos trigger an interrupt at the half-way mark. uar t interrupt fifo level select (uar tifls) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x034 t ype r/w , reset 0x0000.0012 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 txiflsel rxiflsel reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro t ype 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:6 uar t receive interrupt fifo level select the trigger points for the receive interrupt are as follows: description v alue rx fifo 1/8 full 0x0 rx fifo ? full 0x1 rx fifo ? full (default) 0x2 rx fifo ? full 0x3 rx fifo 7/8 full 0x4 reserved 0x5-0x7 0x2 r/w rxiflsel 5:3 september 02, 2007 318 preliminary universal asynchronous receivers/t ransmitters (uar t s) description reset t ype name bit/field uar t t ransmit interrupt fifo level select the trigger points for the transmit interrupt are as follows: description v alue tx fifo 1/8 full 0x0 tx fifo ? full 0x1 tx fifo ? full (default) 0x2 tx fifo ? full 0x3 tx fifo 7/8 full 0x4 reserved 0x5-0x7 0x2 r/w txiflsel 2:0 319 september 02, 2007 preliminary lm3s8962 microcontroller register 10: uart interrupt mask (uartim), offset 0x038 the uartim register is the interrupt mask set/clear register . on a read, this register gives the current value of the mask on the relevant interrupt. w riting a 1 to a bit allows the corresponding raw interrupt signal to be routed to the interrupt controller . w riting a 0 prevents the raw interrupt signal from being sent to the interrupt controller . uar t interrupt mask (uar tim) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x038 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved rxim txim r tim feim peim beim oeim reserved ro ro ro ro r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 1 uar t overrun error interrupt mask on a read, the current mask for the oeim interrupt is returned. setting this bit to 1 promotes the oeim interrupt to the interrupt controller . 0 r/w oeim 10 uar t break error interrupt mask on a read, the current mask for the beim interrupt is returned. setting this bit to 1 promotes the beim interrupt to the interrupt controller . 0 r/w beim 9 uar t parity error interrupt mask on a read, the current mask for the peim interrupt is returned. setting this bit to 1 promotes the peim interrupt to the interrupt controller . 0 r/w peim 8 uar t framing error interrupt mask on a read, the current mask for the feim interrupt is returned. setting this bit to 1 promotes the feim interrupt to the interrupt controller . 0 r/w feim 7 uar t receive t ime-out interrupt mask on a read, the current mask for the rtim interrupt is returned. setting this bit to 1 promotes the rtim interrupt to the interrupt controller . 0 r/w r tim 6 uar t t ransmit interrupt mask on a read, the current mask for the txim interrupt is returned. setting this bit to 1 promotes the txim interrupt to the interrupt controller . 0 r/w txim 5 september 02, 2007 320 preliminary universal asynchronous receivers/t ransmitters (uar t s) description reset t ype name bit/field uar t receive interrupt mask on a read, the current mask for the rxim interrupt is returned. setting this bit to 1 promotes the rxim interrupt to the interrupt controller . 0 r/w rxim 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 3:0 321 september 02, 2007 preliminary lm3s8962 microcontroller register 1 1: uart raw interrupt status (uartris), offset 0x03c the uartris register is the raw interrupt status register . on a read, this register gives the current raw status value of the corresponding interrupt. a write has no ef fect. uar t raw interrupt status (uar tris) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x03c t ype ro, reset 0x0000.000f 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved rxris txris r tris feris peris beris oeris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 1 uar t overrun error raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 0 ro oeris 10 uar t break error raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 0 ro beris 9 uar t parity error raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 0 ro peris 8 uar t framing error raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 0 ro feris 7 uar t receive t ime-out raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 0 ro r tris 6 uar t t ransmit raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 0 ro txris 5 uar t receive raw interrupt status gives the raw interrupt state (prior to masking) of this interrupt. 0 ro rxris 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0xf ro reserved 3:0 september 02, 2007 322 preliminary universal asynchronous receivers/t ransmitters (uar t s) register 12: uart masked interrupt status (uartmis), offset 0x040 the uartmis register is the masked interrupt status register . on a read, this register gives the current masked status value of the corresponding interrupt. a write has no ef fect. uar t masked interrupt status (uar tmis) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x040 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved rxmis txmis r tmis femis pemis bemis oemis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 1 uar t overrun error masked interrupt status gives the masked interrupt state of this interrupt. 0 ro oemis 10 uar t break error masked interrupt status gives the masked interrupt state of this interrupt. 0 ro bemis 9 uar t parity error masked interrupt status gives the masked interrupt state of this interrupt. 0 ro pemis 8 uar t framing error masked interrupt status gives the masked interrupt state of this interrupt. 0 ro femis 7 uar t receive t ime-out masked interrupt status gives the masked interrupt state of this interrupt. 0 ro r tmis 6 uar t t ransmit masked interrupt status gives the masked interrupt state of this interrupt. 0 ro txmis 5 uar t receive masked interrupt status gives the masked interrupt state of this interrupt. 0 ro rxmis 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3:0 323 september 02, 2007 preliminary lm3s8962 microcontroller register 13: uart interrupt clear (uarticr), offset 0x044 the uarticr register is the interrupt clear register . on a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared. a write of 0 has no ef fect. uar t interrupt clear (uar ticr) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0x044 t ype w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved rxic txic r tic feic peic beic oeic reserved ro ro ro ro w1c w1c w1c w1c w1c w1c w1c ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 1 overrun error interrupt clear the oeic values are defined as follows: description v alue no ef fect on the interrupt. 0 clears interrupt. 1 0 w1c oeic 10 break error interrupt clear the beic values are defined as follows: description v alue no ef fect on the interrupt. 0 clears interrupt. 1 0 w1c beic 9 parity error interrupt clear the peic values are defined as follows: description v alue no ef fect on the interrupt. 0 clears interrupt. 1 0 w1c peic 8 september 02, 2007 324 preliminary universal asynchronous receivers/t ransmitters (uar t s) description reset t ype name bit/field framing error interrupt clear the feic values are defined as follows: description v alue no ef fect on the interrupt. 0 clears interrupt. 1 0 w1c feic 7 receive t ime-out interrupt clear the rtic values are defined as follows: description v alue no ef fect on the interrupt. 0 clears interrupt. 1 0 w1c r tic 6 t ransmit interrupt clear the txic values are defined as follows: description v alue no ef fect on the interrupt. 0 clears interrupt. 1 0 w1c txic 5 receive interrupt clear the rxic values are defined as follows: description v alue no ef fect on the interrupt. 0 clears interrupt. 1 0 w1c rxic 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 3:0 325 september 02, 2007 preliminary lm3s8962 microcontroller register 14: uart peripheral identification 4 (uartperiphid4), offset 0xfd0 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uar t peripheral identification 4 (uar tperiphid4) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xfd0 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid4 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t peripheral id register[7:0] can be used by software to identify the presence of this peripheral. 0x0000 ro pid4 7:0 september 02, 2007 326 preliminary universal asynchronous receivers/t ransmitters (uar t s) register 15: uart peripheral identification 5 (uartperiphid5), offset 0xfd4 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uar t peripheral identification 5 (uar tperiphid5) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xfd4 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid5 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t peripheral id register[15:8] can be used by software to identify the presence of this peripheral. 0x0000 ro pid5 7:0 327 september 02, 2007 preliminary lm3s8962 microcontroller register 16: uart peripheral identification 6 (uartperiphid6), offset 0xfd8 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uar t peripheral identification 6 (uar tperiphid6) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xfd8 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid6 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t peripheral id register[23:16] can be used by software to identify the presence of this peripheral. 0x0000 ro pid6 7:0 september 02, 2007 328 preliminary universal asynchronous receivers/t ransmitters (uar t s) register 17: uart peripheral identification 7 (uartperiphid7), offset 0xfdc the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uar t peripheral identification 7 (uar tperiphid7) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xfdc t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid7 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:8 uar t peripheral id register[31:24] can be used by software to identify the presence of this peripheral. 0x0000 ro pid7 7:0 329 september 02, 2007 preliminary lm3s8962 microcontroller register 18: uart peripheral identification 0 (uartperiphid0), offset 0xfe0 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uar t peripheral identification 0 (uar tperiphid0) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xfe0 t ype ro, reset 0x0000.001 1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t peripheral id register[7:0] can be used by software to identify the presence of this peripheral. 0x1 1 ro pid0 7:0 september 02, 2007 330 preliminary universal asynchronous receivers/t ransmitters (uar t s) register 19: uart peripheral identification 1 (uartperiphid1), offset 0xfe4 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uar t peripheral identification 1 (uar tperiphid1) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xfe4 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t peripheral id register[15:8] can be used by software to identify the presence of this peripheral. 0x00 ro pid1 7:0 331 september 02, 2007 preliminary lm3s8962 microcontroller register 20: uart peripheral identification 2 (uartperiphid2), offset 0xfe8 the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uar t peripheral identification 2 (uar tperiphid2) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xfe8 t ype ro, reset 0x0000.0018 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t peripheral id register[23:16] can be used by software to identify the presence of this peripheral. 0x18 ro pid2 7:0 september 02, 2007 332 preliminary universal asynchronous receivers/t ransmitters (uar t s) register 21: uart peripheral identification 3 (uartperiphid3), offset 0xfec the uartperiphidn registers are hard-coded and the fields within the registers determine the reset values. uar t peripheral identification 3 (uar tperiphid3) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xfec t ype ro, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t peripheral id register[31:24] can be used by software to identify the presence of this peripheral. 0x01 ro pid3 7:0 333 september 02, 2007 preliminary lm3s8962 microcontroller register 22: uart primecell identification 0 (uartpcellid0), offset 0xff0 the uartpcellidn registers are hard-coded and the fields within the registers determine the reset values. uar t primecell identification 0 (uar tpcellid0) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xff0 t ype ro, reset 0x0000.000d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t primecell id register[7:0] provides software a standard cross-peripheral identification system. 0x0d ro cid0 7:0 september 02, 2007 334 preliminary universal asynchronous receivers/t ransmitters (uar t s) register 23: uart primecell identification 1 (uartpcellid1), offset 0xff4 the uartpcellidn registers are hard-coded and the fields within the registers determine the reset values. uar t primecell identification 1 (uar tpcellid1) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xff4 t ype ro, reset 0x0000.00f0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t primecell id register[15:8] provides software a standard cross-peripheral identification system. 0xf0 ro cid1 7:0 335 september 02, 2007 preliminary lm3s8962 microcontroller register 24: uart primecell identification 2 (uartpcellid2), offset 0xff8 the uartpcellidn registers are hard-coded and the fields within the registers determine the reset values. uar t primecell identification 2 (uar tpcellid2) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xff8 t ype ro, reset 0x0000.0005 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t primecell id register[23:16] provides software a standard cross-peripheral identification system. 0x05 ro cid2 7:0 september 02, 2007 336 preliminary universal asynchronous receivers/t ransmitters (uar t s) register 25: uart primecell identification 3 (uartpcellid3), offset 0xffc the uartpcellidn registers are hard-coded and the fields within the registers determine the reset values. uar t primecell identification 3 (uar tpcellid3) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 of fset 0xffc t ype ro, reset 0x0000.00b1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 uar t primecell id register[31:24] provides software a standard cross-peripheral identification system. 0xb1 ro cid3 7:0 337 september 02, 2007 preliminary lm3s8962 microcontroller 14 synchronous serial interface (ssi) the stellaris ? synchronous serial interface (ssi) is a master or slave interface for synchronous serial communication with peripheral devices that have either freescale spi, microwire, or t exas instruments synchronous serial interfaces. the stellaris ? ssi module has the following features: master or slave operation programmable clock bit rate and prescale separate transmit and receive fifos, 16 bits wide, 8 locations deep programmable interface operation for freescale spi, microwire, or t exas instruments synchronous serial interfaces programmable data frame size from 4 to 16 bits internal loopback test mode for diagnostic/debug testing 14.1 block diagram figure 14-1. ssi module block diagram 14.2 functional description the ssi performs serial-to-parallel conversion on data received from a peripheral device. the cpu accesses data, control, and status information. the transmit and receive paths are buf fered with september 02, 2007 338 preliminary synchronous serial interface (ssi) t ransmit / receive logic clock prescaler ssicpsr control / status ssicr 0 ssicr 1 ssisr interrupt control ssiim ssimis ssiris ssiicr ssidr txfifo 8 x 16 . . . rxfifo 8 x 16 . . . system clock ssitx ssirx ssiclk ssifss interrupt identification registers ssipcellid 0 ssiperiphid 0 ssiperiphid 4 ssipcellid 1 ssiperiphid 1 ssiperiphid 5 ssipcellid 2 ssiperiphid 2 ssiperiphid 6 ssipcellid 3 ssiperiphid 3 ssiperiphid 7 internal fifo memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. 14.2.1 bit rate generation the ssi includes a programmable bit rate clock divider and prescaler to generate the serial output clock. bit rates are supported to 2 mhz and higher , although maximum bit rate is determined by peripheral devices. the serial bit rate is derived by dividing down the 50-mhz input clock. the clock is first divided by an even prescale value cpsdvsr from 2 to 254, which is programmed in the ssi clock prescale (ssicpsr) register (see page 357 ). the clock is further divided by a value from 1 to 256, which is 1 + scr , where scr is the value programmed in the ssi control0 (ssicr0) register (see page 350 ). the frequency of the output clock ssiclk is defined by: fssiclk = fsysclk / (cpsdvsr * (1 + scr)) note that although the ssiclk transmit clock can theoretically be 25 mhz, the module may not be able to operate at that speed. for master mode, the system clock must be at least two times faster than the ssiclk . for slave mode, the system clock must be at least 12 times faster than the ssiclk . see synchronous serial interface (ssi) on page 585 to view ssi timing parameters. 14.2.2 fifo operation 14.2.2.1 t ransmit fifo the common transmit fifo is a 16-bit wide, 8-locations deep, first-in, first-out memory buf fer . the cpu writes data to the fifo by writing the ssi data (ssidr) register (see page 354 ), and data is stored in the fifo until it is read out by the transmission logic. when configured as a master or a slave, parallel data is written into the transmit fifo prior to serial conversion and transmission to the attached slave or master , respectively , through the ssitx pin. 14.2.2.2 receive fifo the common receive fifo is a 16-bit wide, 8-locations deep, first-in, first-out memory buf fer . received data from the serial interface is stored in the buf fer until read out by the cpu, which accesses the read fifo by reading the ssidr register . when configured as a master or slave, serial data received through the ssirx pin is registered prior to parallel loading into the attached slave or master receive fifo, respectively . 14.2.3 interrupts the ssi can generate interrupts when the following conditions are observed: t ransmit fifo service receive fifo service receive fifo time-out receive fifo overrun all of the interrupt events are ored together before being sent to the interrupt controller , so the ssi can only generate a single interrupt request to the controller at any given time. y ou can mask each 339 september 02, 2007 preliminary lm3s8962 microcontroller of the four individual maskable interrupts by setting the appropriate bits in the ssi interrupt mask (ssiim) register (see page 358 ). setting the appropriate mask bit to 1 enables the interrupt. provision of the individual outputs, as well as a combined interrupt output, allows use of either a global interrupt service routine, or modular device drivers to handle interrupts. the transmit and receive dynamic dataflow interrupts have been separated from the status interrupts so that data can be read or written in response to the fifo trigger levels. the status of the individual interrupt sources can be read from the ssi raw interrupt status (ssiris) and ssi masked interrupt status (ssimis) registers (see page 360 and page 361 , respectively). 14.2.4 frame formats each data frame is between 4 and 16 bits long, depending on the size of data programmed, and is transmitted starting with the msb. there are three basic frame types that can be selected: t exas instruments synchronous serial freescale spi microwire for all three formats, the serial clock ( ssiclk ) is held inactive while the ssi is idle, and ssiclk transitions at the programmed frequency only during active transmission or reception of data. the idle state of ssiclk is utilized to provide a receive timeout indication that occurs when the receive fifo still contains data after a timeout period. for freescale spi and microwire frame formats, the serial frame ( ssifss ) pin is active low , and is asserted (pulled down) during the entire transmission of the frame. for t exas instruments synchronous serial frame format, the ssifss pin is pulsed for one serial clock period starting at its rising edge, prior to the transmission of each frame. for this frame format, both the ssi and the of f-chip slave device drive their output data on the rising edge of ssiclk , and latch data from the other device on the falling edge. unlike the full-duplex transmission of the other two frame formats, the microwire format uses a special master-slave messaging technique, which operates at half-duplex. in this mode, when a frame begins, an 8-bit control message is transmitted to the of f-chip slave. during this transmit, no incoming data is received by the ssi. after the message has been sent, the of f-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the requested data. the returned data can be 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. 14.2.4.1 t exas instruments synchronous serial frame format figure 14-2 on page 340 shows the t exas instruments synchronous serial frame format for a single transmitted frame. figure 14-2. ti synchronous serial frame format (single t ransfer) september 02, 2007 340 preliminary synchronous serial interface (ssi) s s i c l k 4 t o 1 6 b i t s s s i f s s s s i t x / s s i r x m s b l s b in this mode, ssiclk and ssifss are forced low , and the transmit data line ssitx is tristated whenever the ssi is idle. once the bottom entry of the transmit fifo contains data, ssifss is pulsed high for one ssiclk period. the value to be transmitted is also transferred from the transmit fifo to the serial shift register of the transmit logic. on the next rising edge of ssiclk , the msb of the 4 to 16-bit data frame is shifted out on the ssitx pin. likewise, the msb of the received data is shifted onto the ssirx pin by the of f-chip serial slave device. both the ssi and the of f-chip serial slave device then clock each data bit into their serial shifter on the falling edge of each ssiclk . the received data is transferred from the serial shifter to the receive fifo on the first rising edge of ssiclk after the lsb has been latched. figure 14-3 on page 341 shows the t exas instruments synchronous serial frame format when back-to-back frames are transmitted. figure 14-3. ti synchronous serial frame format (continuous t ransfer) 14.2.4.2 freescale spi frame format the freescale spi interface is a four-wire interface where the ssifss signal behaves as a slave select. the main feature of the freescale spi format is that the inactive state and phase of the ssiclk signal are programmable through the spo and sph bits within the ssiscr0 control register . spo clock polarity bit when the spo clock polarity control bit is low , it produces a steady state low value on the ssiclk pin. if the spo bit is high, a steady state high value is placed on the ssiclk pin when data is not being transferred. sph phase control bit the sph phase control bit selects the clock edge that captures data and allows it to change state. it has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. when the sph phase control bit is low , data is captured on the first clock edge transition. if the sph bit is high, data is captured on the second clock edge transition. 14.2.4.3 freescale spi frame format with spo=0 and sph=0 single and continuous transmission signal sequences for freescale spi format with spo=0 and sph=0 are shown in figure 14-4 on page 342 and figure 14-5 on page 342 . 341 september 02, 2007 preliminary lm3s8962 microcontroller m s b l s b 4 t o 1 6 b i t s s s i c l k s s i f s s s s i t x / s s i r x figure 14-4. freescale spi format (single t ransfer) with spo=0 and sph=0 note: q is undefined. figure 14-5. freescale spi format (continuous t ransfer) with spo=0 and sph=0 in this configuration, during idle periods: ssiclk is forced low ssifss is forced high the transmit data line ssitx is arbitrarily forced low when the ssi is configured as a master , it enables the ssiclk pad when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and there is valid data within the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low . this causes slave data to be enabled onto the ssirx input line of the master . the master ssitx output pad is enabled. one half ssiclk period later , valid master data is transferred to the ssitx pin. now that both the master and slave data have been set, the ssiclk master clock pin goes high after one further half ssiclk period. the data is now captured on the rising and propagated on the falling edges of the ssiclk signal. in the case of a single word transmission, after all bits of the data word have been transferred, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. however , in the case of continuous back-to-back transmissions, the ssifss signal must be pulsed high between each data word transfer . this is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the sph bit is logic zero. therefore, the master device must raise the ssifss pin of the slave device between each data transfer to enable the serial peripheral data write. on completion of the continuous transfer , the ssifss pin is returned to its idle state one ssiclk period after the last bit has been captured. september 02, 2007 342 preliminary synchronous serial interface (ssi) 4 t o 1 6 b i t s s s i c l k s s i f s s s s i r x q s s i t x m s b m s b l s b l s b s s i c l k s s i f s s s s i r x l s b s s i t x m s b l s b 4 t o 1 6 b i t s l s b m s b m s b m s b l s b 14.2.4.4 freescale spi frame format with spo=0 and sph=1 the transfer signal sequence for freescale spi format with spo=0 and sph=1 is shown in figure 14-6 on page 343 , which covers both single and continuous transfers. figure 14-6. freescale spi frame format with spo=0 and sph=1 note: q is undefined. in this configuration, during idle periods: ssiclk is forced low ssifss is forced high the transmit data line ssitx is arbitrarily forced low when the ssi is configured as a master , it enables the ssiclk pad when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and there is valid data within the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low . the master ssitx output is enabled. after a further one half ssiclk period, both master and slave valid data is enabled onto their respective transmission lines. at the same time, the ssiclk is enabled with a rising edge transition. data is then captured on the falling edges and propagated on the rising edges of the ssiclk signal. in the case of a single word transfer , after all bits have been transferred, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. for continuous back-to-back transfers, the ssifss pin is held low between successive data words and termination is the same as that of the single word transfer . 14.2.4.5 freescale spi frame format with spo=1 and sph=0 single and continuous transmission signal sequences for freescale spi format with spo=1 and sph=0 are shown in figure 14-7 on page 344 and figure 14-8 on page 344 . 343 september 02, 2007 preliminary lm3s8962 microcontroller 4 t o 1 6 b i t s s s i c l k s s i f s s s s i r x s s i t x q m s b q m s b l s b l s b figure 14-7. freescale spi frame format (single t ransfer) with spo=1 and sph=0 note: q is undefined. figure 14-8. freescale spi frame format (continuous t ransfer) with spo=1 and sph=0 in this configuration, during idle periods: ssiclk is forced high ssifss is forced high the transmit data line ssitx is arbitrarily forced low when the ssi is configured as a master , it enables the ssiclk pad when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and there is valid data within the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low , which causes slave data to be immediately transferred onto the ssirx line of the master . the master ssitx output pad is enabled. one half period later , valid master data is transferred to the ssitx line. now that both the master and slave data have been set, the ssiclk master clock pin becomes low after one further half ssiclk period. this means that data is captured on the falling edges and propagated on the rising edges of the ssiclk signal. in the case of a single word transmission, after all bits of the data word are transferred, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. however , in the case of continuous back-to-back transmissions, the ssifss signal must be pulsed high between each data word transfer . this is because the slave select pin freezes the data in its serial peripheral register and does not allow it to be altered if the sph bit is logic zero. therefore, the master device must raise the ssifss pin of the slave device between each data transfer to enable the serial peripheral data write. on completion of the continuous transfer , the ssifss pin is returned to its idle state one ssiclk period after the last bit has been captured. september 02, 2007 344 preliminary synchronous serial interface (ssi) 4 t o 1 6 b i t s s s i c l k s s i f s s s s i r x s s i t x q m s b m s b l s b l s b s s i c l k s s i f s s s s i t x / s s i r x m s b l s b 4 t o 1 6 b i t s l s b m s b 14.2.4.6 freescale spi frame format with spo=1 and sph=1 the transfer signal sequence for freescale spi format with spo=1 and sph=1 is shown in figure 14-9 on page 345 , which covers both single and continuous transfers. figure 14-9. freescale spi frame format with spo=1 and sph=1 note: q is undefined. in this configuration, during idle periods: ssiclk is forced high ssifss is forced high the transmit data line ssitx is arbitrarily forced low when the ssi is configured as a master , it enables the ssiclk pad when the ssi is configured as a slave, it disables the ssiclk pad if the ssi is enabled and there is valid data within the transmit fifo, the start of transmission is signified by the ssifss master signal being driven low . the master ssitx output pad is enabled. after a further one-half ssiclk period, both master and slave data are enabled onto their respective transmission lines. at the same time, ssiclk is enabled with a falling edge transition. data is then captured on the rising edges and propagated on the falling edges of the ssiclk signal. after all bits have been transferred, in the case of a single word transmission, the ssifss line is returned to its idle high state one ssiclk period after the last bit has been captured. for continuous back-to-back transmissions, the ssifss pin remains in its active low state, until the final bit of the last word has been captured, and then returns to its idle state as described above. for continuous back-to-back transfers, the ssifss pin is held low between successive data words and termination is the same as that of the single word transfer . 14.2.4.7 microwire frame format figure 14-10 on page 346 shows the microwire frame format, again for a single frame. figure 14-1 1 on page 347 shows the same format when back-to-back frames are transmitted. 345 september 02, 2007 preliminary lm3s8962 microcontroller 4 t o 1 6 b i t s s s i c l k s s i f s s s s i r x s s i t x q q m s b m s b l s b l s b figure 14-10. microwire frame format (single frame) microwire format is very similar to spi format, except that transmission is half-duplex instead of full-duplex, using a master-slave message passing technique. each serial transmission begins with an 8-bit control word that is transmitted from the ssi to the of f-chip slave device. during this transmission, no incoming data is received by the ssi. after the message has been sent, the of f-chip slave decodes it and, after waiting one serial clock after the last bit of the 8-bit control message has been sent, responds with the required data. the returned data is 4 to 16 bits in length, making the total frame length anywhere from 13 to 25 bits. in this configuration, during idle periods: ssiclk is forced low ssifss is forced high the transmit data line ssitx is arbitrarily forced low a transmission is triggered by writing a control byte to the transmit fifo. the falling edge of ssifss causes the value contained in the bottom entry of the transmit fifo to be transferred to the serial shift register of the transmit logic, and the msb of the 8-bit control frame to be shifted out onto the ssitx pin. ssifss remains low for the duration of the frame transmission. the ssirx pin remains tristated during this transmission. the of f-chip serial slave device latches each control bit into its serial shifter on the rising edge of each ssiclk . after the last bit is latched by the slave device, the control byte is decoded during a one clock wait-state, and the slave responds by transmitting data back to the ssi. each bit is driven onto the ssirx line on the falling edge of ssiclk . the ssi in turn latches each bit on the rising edge of ssiclk . at the end of the frame, for single transfers, the ssifss signal is pulled high one clock period after the last bit has been latched in the receive serial shifter , which causes the data to be transferred to the receive fifo. note: the of f-chip slave device can tristate the receive line either on the falling edge of ssiclk after the lsb has been latched by the receive shifter , or when the ssifss pin goes high. for continuous transfers, data transmission begins and ends in the same manner as a single transfer . however , the ssifss line is continuously asserted (held low) and transmission of data occurs back-to-back. the control byte of the next frame follows directly after the lsb of the received data from the current frame. each of the received values is transferred from the receive shifter on the falling edge of ssiclk , after the lsb of the frame has been latched into the ssi. september 02, 2007 346 preliminary synchronous serial interface (ssi) s s i c l k s s i f s s l s b m s b s s i r x 4 t o 1 6 b i t s o u t p u t d a t a 0 s s i t x m s b l s b 8 - b i t c o n t r o l figure 14-1 1. microwire frame format (continuous t ransfer) in the microwire mode, the ssi slave samples the first bit of receive data on the rising edge of ssiclk after ssifss has gone low . masters that drive a free-running ssiclk must ensure that the ssifss signal has suf ficient setup and hold margins with respect to the rising edge of ssiclk . figure 14-12 on page 347 illustrates these setup and hold time requirements. with respect to the ssiclk rising edge on which the first bit of receive data is to be sampled by the ssi slave, ssifss must have a setup of at least two times the period of ssiclk on which the ssi operates. with respect to the ssiclk rising edge previous to this edge, ssifss must have a hold of at least one ssiclk period. figure 14-12. microwire frame format, ssifss input setup and hold requirements 14.3 initialization and configuration t o use the ssi, its peripheral clock must be enabled by setting the ssi bit in the rcgc1 register . for each of the frame formats, the ssi is configured using the following steps: 1. ensure that the sse bit in the ssicr1 register is disabled before making any configuration changes. 2. select whether the ssi is a master or slave: a. for master operations, set the ssicr1 register to 0x0000.0000. b. for slave mode (output enabled), set the ssicr1 register to 0x0000.0004. c. for slave mode (output disabled), set the ssicr1 register to 0x0000.000c. 3. configure the clock prescale divisor by writing the ssicpsr register . 347 september 02, 2007 preliminary lm3s8962 microcontroller 8 - b i t c o n t r o l s s i c l k s s i f s s l s b m s b s s i r x 4 t o 1 6 b i t s o u t p u t d a t a 0 s s i t x m s b l s b l s b m s b s s i c l k s s i f s s s s i r x f i r s t r x d a t a t o b e s a m p l e d b y s s i s l a v e t s e t u p = ( 2 * t s s i c l k ) t h o l d = t s s i c l k 4. w rite the ssicr0 register with the following configuration: serial clock rate ( scr ) desired clock phase/polarity , if using freescale spi mode ( sph and spo ) the protocol mode: freescale spi, ti ssf , microwire ( frf ) the data size ( dss ) 5. enable the ssi by setting the sse bit in the ssicr1 register . as an example, assume the ssi must be configured to operate with the following parameters: master operation freescale spi mode (spo=1, sph=1) 1 mbps bit rate 8 data bits assuming the system clock is 20 mhz, the bit rate calculation would be: fssiclk = fsysclk / (cpsdvsr * (1 + scr)) 1x106 = 20x106 / (cpsdvsr * (1 + scr)) in this case, if cpsdvsr =2, scr must be 9. the configuration sequence would be as follows: 1. ensure that the sse bit in the ssicr1 register is disabled. 2. w rite the ssicr1 register with a value of 0x0000.0000. 3. w rite the ssicpsr register with a value of 0x0000.0002. 4. w rite the ssicr0 register with a value of 0x0000.09c7. 5. the ssi is then enabled by setting the sse bit in the ssicr1 register to 1. 14.4 register map t able 14-1 on page 348 lists the ssi registers. the of fset listed is a hexadecimal increment to the register s address, relative to that ssi module s base address: ssi0: 0x4000.8000 note: the ssi must be disabled (see the sse bit in the ssicr1 register) before any of the control registers are reprogrammed. t able 14-1. ssi register map see page description reset t ype name offset 350 ssi control 0 0x0000.0000 r/w ssicr0 0x000 september 02, 2007 348 preliminary synchronous serial interface (ssi) see page description reset t ype name offset 352 ssi control 1 0x0000.0000 r/w ssicr1 0x004 354 ssi data 0x0000.0000 r/w ssidr 0x008 355 ssi status 0x0000.0003 ro ssisr 0x00c 357 ssi clock prescale 0x0000.0000 r/w ssicpsr 0x010 358 ssi interrupt mask 0x0000.0000 r/w ssiim 0x014 360 ssi raw interrupt status 0x0000.0008 ro ssiris 0x018 361 ssi masked interrupt status 0x0000.0000 ro ssimis 0x01c 362 ssi interrupt clear 0x0000.0000 w1c ssiicr 0x020 363 ssi peripheral identification 4 0x0000.0000 ro ssiperiphid4 0xfd0 364 ssi peripheral identification 5 0x0000.0000 ro ssiperiphid5 0xfd4 365 ssi peripheral identification 6 0x0000.0000 ro ssiperiphid6 0xfd8 366 ssi peripheral identification 7 0x0000.0000 ro ssiperiphid7 0xfdc 367 ssi peripheral identification 0 0x0000.0022 ro ssiperiphid0 0xfe0 368 ssi peripheral identification 1 0x0000.0000 ro ssiperiphid1 0xfe4 369 ssi peripheral identification 2 0x0000.0018 ro ssiperiphid2 0xfe8 370 ssi peripheral identification 3 0x0000.0001 ro ssiperiphid3 0xfec 371 ssi primecell identification 0 0x0000.000d ro ssipcellid0 0xff0 372 ssi primecell identification 1 0x0000.00f0 ro ssipcellid1 0xff4 373 ssi primecell identification 2 0x0000.0005 ro ssipcellid2 0xff8 374 ssi primecell identification 3 0x0000.00b1 ro ssipcellid3 0xffc 14.5 register descriptions the remainder of this section lists and describes the ssi registers, in numerical order by address of fset. 349 september 02, 2007 preliminary lm3s8962 microcontroller register 1: ssi control 0 (ssicr0), offset 0x000 ssicr0 is control register 0 and contains bit fields that control various functions within the ssi module. functionality such as protocol mode, clock rate, and data size are configured in this register . ssi control 0 (ssicr0) ssi0 base: 0x4000.8000 of fset 0x000 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 dss frf spo sph scr r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:16 ssi serial clock rate the value scr is used to generate the transmit and receive bit rate of the ssi. the bit rate is: br=fssiclk/(cpsdvsr * (1 + scr)) where cpsdvsr is an even value from 2-254 programmed in the ssicpsr register , and scr is a value from 0-255. 0x0000 r/w scr 15:8 ssi serial clock phase this bit is only applicable to the freescale spi format. the sph control bit selects the clock edge that captures data and allows it to change state. it has the most impact on the first bit transmitted by either allowing or not allowing a clock transition before the first data capture edge. when the sph bit is 0, data is captured on the first clock edge transition. if sph is 1, data is captured on the second clock edge transition. 0 r/w sph 7 ssi serial clock polarity this bit is only applicable to the freescale spi format. when the spo bit is 0, it produces a steady state low value on the ssiclk pin. if spo is 1, a steady state high value is placed on the ssiclk pin when data is not being transferred. 0 r/w spo 6 september 02, 2007 350 preliminary synchronous serial interface (ssi) description reset t ype name bit/field ssi frame format select the frf values are defined as follows: frame format v alue freescale spi frame format 0x0 t exas intruments synchronous serial frame format 0x1 microwire frame format 0x2 reserved 0x3 0x0 r/w frf 5:4 ssi data size select the dss values are defined as follows: data size v alue reserved 0x0-0x2 4-bit data 0x3 5-bit data 0x4 6-bit data 0x5 7-bit data 0x6 8-bit data 0x7 9-bit data 0x8 10-bit data 0x9 1 1-bit data 0xa 12-bit data 0xb 13-bit data 0xc 14-bit data 0xd 15-bit data 0xe 16-bit data 0xf 0x00 r/w dss 3:0 351 september 02, 2007 preliminary lm3s8962 microcontroller register 2: ssi control 1 (ssicr1), offset 0x004 ssicr1 is control register 1 and contains bit fields that control various functions within the ssi module. master and slave mode functionality is controlled by this register . ssi control 1 (ssicr1) ssi0 base: 0x4000.8000 of fset 0x004 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 lbm sse ms sod reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:4 ssi slave mode output disable this bit is relevant only in the slave mode ( ms =1). in multiple-slave systems, it is possible for the ssi master to broadcast a message to all slaves in the system while ensuring that only one slave drives data onto the serial output line. in such systems, the txd lines from multiple slaves could be tied together . t o operate in such a system, the sod bit can be configured so that the ssi slave does not drive the ssitx pin. the sod values are defined as follows: description v alue ssi can drive ssitx output in slave output mode. 0 ssi must not drive the ssitx output in slave mode. 1 0 r/w sod 3 ssi master/slave select this bit selects master or slave mode and can be modified only when ssi is disabled ( sse =0). the ms values are defined as follows: description v alue device configured as a master . 0 device configured as a slave. 1 0 r/w ms 2 september 02, 2007 352 preliminary synchronous serial interface (ssi) description reset t ype name bit/field ssi synchronous serial port enable setting this bit enables ssi operation. the sse values are defined as follows: description v alue ssi operation disabled. 0 ssi operation enabled. 1 note: this bit must be set to 0 before any control registers are reprogrammed. 0 r/w sse 1 ssi loopback mode setting this bit enables loopback t est mode. the lbm values are defined as follows: description v alue normal serial port operation enabled. 0 output of the transmit serial shift register is connected internally to the input of the receive serial shift register . 1 0 r/w lbm 0 353 september 02, 2007 preliminary lm3s8962 microcontroller register 3: ssi data (ssidr), offset 0x008 ssidr is the data register and is 16-bits wide. when ssidr is read, the entry in the receive fifo (pointed to by the current fifo read pointer) is accessed. as data values are removed by the ssi receive logic from the incoming data frame, they are placed into the entry in the receive fifo (pointed to by the current fifo write pointer). when ssidr is written to, the entry in the transmit fifo (pointed to by the write pointer) is written to. data values are removed from the transmit fifo one value at a time by the transmit logic. it is loaded into the transmit serial shifter , then serially shifted out onto the ssitx pin at the programmed bit rate. when a data size of less than 16 bits is selected, the user must right-justify data written to the transmit fifo. the transmit logic ignores the unused bits. received data less than 16 bits is automatically right-justified in the receive buf fer . when the ssi is programmed for microwire frame format, the default size for transmit data is eight bits (the most significant byte is ignored). the receive data size is controlled by the programmer . the transmit fifo and the receive fifo are not cleared even when the sse bit in the ssicr1 register is set to zero. this allows the software to fill the transmit fifo before enabling the ssi. ssi data (ssidr) ssi0 base: 0x4000.8000 of fset 0x008 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 da t a r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 ssi receive/t ransmit data a read operation reads the receive fifo. a write operation writes the transmit fifo. software must right-justify data when the ssi is programmed for a data size that is less than 16 bits. unused bits at the top are ignored by the transmit logic. the receive logic automatically right-justifies the data. 0x0000 r/w da t a 15:0 september 02, 2007 354 preliminary synchronous serial interface (ssi) register 4: ssi status (ssisr), offset 0x00c ssisr is a status register that contains bits that indicate the fifo fill status and the ssi busy status. ssi status (ssisr) ssi0 base: 0x4000.8000 of fset 0x00c t ype ro, reset 0x0000.0003 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 tfe tnf rne rff bsy reserved r0 ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:5 ssi busy bit the bsy values are defined as follows: description v alue ssi is idle. 0 ssi is currently transmitting and/or receiving a frame, or the transmit fifo is not empty . 1 0 ro bsy 4 ssi receive fifo full the rff values are defined as follows: description v alue receive fifo is not full. 0 receive fifo is full. 1 0 ro rff 3 ssi receive fifo not empty the rne values are defined as follows: description v alue receive fifo is empty . 0 receive fifo is not empty . 1 0 ro rne 2 ssi t ransmit fifo not full the tnf values are defined as follows: description v alue t ransmit fifo is full. 0 t ransmit fifo is not full. 1 1 ro tnf 1 355 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field ssi t ransmit fifo empty the tfe values are defined as follows: description v alue t ransmit fifo is not empty . 0 t ransmit fifo is empty . 1 1 r0 tfe 0 september 02, 2007 356 preliminary synchronous serial interface (ssi) register 5: ssi clock prescale (ssicpsr), offset 0x010 ssicpsr is the clock prescale register and specifies the division factor by which the system clock must be internally divided before further use. the value programmed into this register must be an even number between 2 and 254. the least-significant bit of the programmed number is hard-coded to zero. if an odd number is written to this register , data read back from this register has the least-significant bit as zero. ssi clock prescale (ssicpsr) ssi0 base: 0x4000.8000 of fset 0x010 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cpsdvsr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi clock prescale divisor this value must be an even number from 2 to 254, depending on the frequency of ssiclk . the lsb always returns 0 on reads. 0x00 r/w cpsdvsr 7:0 357 september 02, 2007 preliminary lm3s8962 microcontroller register 6: ssi interrupt mask (ssiim), offset 0x014 the ssiim register is the interrupt mask set or clear register . it is a read/write register and all bits are cleared to 0 on reset. on a read, this register gives the current value of the mask on the relevant interrupt. a write of 1 to the particular bit sets the mask, enabling the interrupt to be read. a write of 0 clears the corresponding mask. ssi interrupt mask (ssiim) ssi0 base: 0x4000.8000 of fset 0x014 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 rorim r tim rxim txim reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:4 ssi t ransmit fifo interrupt mask the txim values are defined as follows: description v alue tx fifo half-full or less condition interrupt is masked. 0 tx fifo half-full or less condition interrupt is not masked. 1 0 r/w txim 3 ssi receive fifo interrupt mask the tfe values are defined as follows: description v alue rx fifo half-full or more condition interrupt is masked. 0 rx fifo half-full or more condition interrupt is not masked. 1 0 r/w rxim 2 ssi receive t ime-out interrupt mask the rtim values are defined as follows: description v alue rx fifo time-out interrupt is masked. 0 rx fifo time-out interrupt is not masked. 1 0 r/w r tim 1 september 02, 2007 358 preliminary synchronous serial interface (ssi) description reset t ype name bit/field ssi receive overrun interrupt mask the rorim values are defined as follows: description v alue rx fifo overrun interrupt is masked. 0 rx fifo overrun interrupt is not masked. 1 0 r/w rorim 0 359 september 02, 2007 preliminary lm3s8962 microcontroller register 7: ssi raw interrupt status (ssiris), offset 0x018 the ssiris register is the raw interrupt status register . on a read, this register gives the current raw status value of the corresponding interrupt prior to masking. a write has no ef fect. ssi raw interrupt status (ssiris) ssi0 base: 0x4000.8000 of fset 0x018 t ype ro, reset 0x0000.0008 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 rorris r tris rxris txris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:4 ssi t ransmit fifo raw interrupt status indicates that the transmit fifo is half full or less, when set. 1 ro txris 3 ssi receive fifo raw interrupt status indicates that the receive fifo is half full or more, when set. 0 ro rxris 2 ssi receive t ime-out raw interrupt status indicates that the receive time-out has occurred, when set. 0 ro r tris 1 ssi receive overrun raw interrupt status indicates that the receive fifo has overflowed, when set. 0 ro rorris 0 september 02, 2007 360 preliminary synchronous serial interface (ssi) register 8: ssi masked interrupt status (ssimis), offset 0x01c the ssimis register is the masked interrupt status register . on a read, this register gives the current masked status value of the corresponding interrupt. a write has no ef fect. ssi masked interrupt status (ssimis) ssi0 base: 0x4000.8000 of fset 0x01c t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 rormis r tmis rxmis txmis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:4 ssi t ransmit fifo masked interrupt status indicates that the transmit fifo is half full or less, when set. 0 ro txmis 3 ssi receive fifo masked interrupt status indicates that the receive fifo is half full or more, when set. 0 ro rxmis 2 ssi receive t ime-out masked interrupt status indicates that the receive time-out has occurred, when set. 0 ro r tmis 1 ssi receive overrun masked interrupt status indicates that the receive fifo has overflowed, when set. 0 ro rormis 0 361 september 02, 2007 preliminary lm3s8962 microcontroller register 9: ssi interrupt clear (ssiicr), offset 0x020 the ssiicr register is the interrupt clear register . on a write of 1, the corresponding interrupt is cleared. a write of 0 has no ef fect. ssi interrupt clear (ssiicr) ssi0 base: 0x4000.8000 of fset 0x020 t ype w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 roric r tic reserved w1c w1c ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:2 ssi receive t ime-out interrupt clear the rtic values are defined as follows: description v alue no ef fect on interrupt. 0 clears interrupt. 1 0 w1c r tic 1 ssi receive overrun interrupt clear the roric values are defined as follows: description v alue no ef fect on interrupt. 0 clears interrupt. 1 0 w1c roric 0 september 02, 2007 362 preliminary synchronous serial interface (ssi) register 10: ssi peripheral identification 4 (ssiperiphid4), offset 0xfd0 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 4 (ssiperiphid4) ssi0 base: 0x4000.8000 of fset 0xfd0 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid4 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi peripheral id register[7:0] can be used by software to identify the presence of this peripheral. 0x00 ro pid4 7:0 363 september 02, 2007 preliminary lm3s8962 microcontroller register 1 1: ssi peripheral identification 5 (ssiperiphid5), offset 0xfd4 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 5 (ssiperiphid5) ssi0 base: 0x4000.8000 of fset 0xfd4 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid5 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi peripheral id register[15:8] can be used by software to identify the presence of this peripheral. 0x00 ro pid5 7:0 september 02, 2007 364 preliminary synchronous serial interface (ssi) register 12: ssi peripheral identification 6 (ssiperiphid6), offset 0xfd8 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 6 (ssiperiphid6) ssi0 base: 0x4000.8000 of fset 0xfd8 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid6 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi peripheral id register[23:16] can be used by software to identify the presence of this peripheral. 0x00 ro pid6 7:0 365 september 02, 2007 preliminary lm3s8962 microcontroller register 13: ssi peripheral identification 7 (ssiperiphid7), offset 0xfdc the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 7 (ssiperiphid7) ssi0 base: 0x4000.8000 of fset 0xfdc t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid7 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi peripheral id register[31:24] can be used by software to identify the presence of this peripheral. 0x00 ro pid7 7:0 september 02, 2007 366 preliminary synchronous serial interface (ssi) register 14: ssi peripheral identification 0 (ssiperiphid0), offset 0xfe0 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 0 (ssiperiphid0) ssi0 base: 0x4000.8000 of fset 0xfe0 t ype ro, reset 0x0000.0022 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 31:8 ssi peripheral id register[7:0] can be used by software to identify the presence of this peripheral. 0x22 ro pid0 7:0 367 september 02, 2007 preliminary lm3s8962 microcontroller register 15: ssi peripheral identification 1 (ssiperiphid1), offset 0xfe4 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 1 (ssiperiphid1) ssi0 base: 0x4000.8000 of fset 0xfe4 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi peripheral id register [15:8] can be used by software to identify the presence of this peripheral. 0x00 ro pid1 7:0 september 02, 2007 368 preliminary synchronous serial interface (ssi) register 16: ssi peripheral identification 2 (ssiperiphid2), offset 0xfe8 the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 2 (ssiperiphid2) ssi0 base: 0x4000.8000 of fset 0xfe8 t ype ro, reset 0x0000.0018 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi peripheral id register [23:16] can be used by software to identify the presence of this peripheral. 0x18 ro pid2 7:0 369 september 02, 2007 preliminary lm3s8962 microcontroller register 17: ssi peripheral identification 3 (ssiperiphid3), offset 0xfec the ssiperiphidn registers are hard-coded and the fields within the register determine the reset value. ssi peripheral identification 3 (ssiperiphid3) ssi0 base: 0x4000.8000 of fset 0xfec t ype ro, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi peripheral id register [31:24] can be used by software to identify the presence of this peripheral. 0x01 ro pid3 7:0 september 02, 2007 370 preliminary synchronous serial interface (ssi) register 18: ssi primecell identification 0 (ssipcellid0), offset 0xff0 the ssipcellidn registers are hard-coded and the fields within the register determine the reset value. ssi primecell identification 0 (ssipcellid0) ssi0 base: 0x4000.8000 of fset 0xff0 t ype ro, reset 0x0000.000d 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi primecell id register [7:0] provides software a standard cross-peripheral identification system. 0x0d ro cid0 7:0 371 september 02, 2007 preliminary lm3s8962 microcontroller register 19: ssi primecell identification 1 (ssipcellid1), offset 0xff4 the ssipcellidn registers are hard-coded and the fields within the register determine the reset value. ssi primecell identification 1 (ssipcellid1) ssi0 base: 0x4000.8000 of fset 0xff4 t ype ro, reset 0x0000.00f0 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid1 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi primecell id register [15:8] provides software a standard cross-peripheral identification system. 0xf0 ro cid1 7:0 september 02, 2007 372 preliminary synchronous serial interface (ssi) register 20: ssi primecell identification 2 (ssipcellid2), offset 0xff8 the ssipcellidn registers are hard-coded and the fields within the register determine the reset value. ssi primecell identification 2 (ssipcellid2) ssi0 base: 0x4000.8000 of fset 0xff8 t ype ro, reset 0x0000.0005 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi primecell id register [23:16] provides software a standard cross-peripheral identification system. 0x05 ro cid2 7:0 373 september 02, 2007 preliminary lm3s8962 microcontroller register 21: ssi primecell identification 3 (ssipcellid3), offset 0xffc the ssipcellidn registers are hard-coded and the fields within the register determine the reset value. ssi primecell identification 3 (ssipcellid3) ssi0 base: 0x4000.8000 of fset 0xffc t ype ro, reset 0x0000.00b1 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 cid3 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 ssi primecell id register [31:24] provides software a standard cross-peripheral identification system. 0xb1 ro cid3 7:0 september 02, 2007 374 preliminary synchronous serial interface (ssi) 15 inter-integrated circuit (i 2 c) interface the inter-integrated circuit (i 2 c) bus provides bi-directional data transfer through a two-wire design (a serial data line sda and a serial clock line scl), and interfaces to external i 2 c devices such as serial memory (rams and roms), networking devices, lcds, tone generators, and so on. the i 2 c bus may also be used for system testing and diagnostic purposes in product development and manufacture. the lm3s8962 microcontroller includes one i 2 c module, providing the ability to interact (both send and receive) with other i 2 c devices on the bus. devices on the i 2 c bus can be designated as either a master or a slave. the stellaris ? i 2 c module supports both sending and receiving data as either a master or a slave, and also supports the simultaneous operation as both a master and a slave. there are a total of four i 2 c modes: master t ransmit, master receive, slave t ransmit, and slave receive. the stellaris ? i 2 c module can operate at two speeds: standard (100 kbps) and fast (400 kbps). both the i 2 c master and slave can generate interrupts; the i 2 c master generates interrupts when a transmit or receive operation completes (or aborts due to an error) and the i 2 c slave generates interrupts when data has been sent or requested by a master . 15.1 block diagram figure 15-1. i 2 c block diagram 15.2 functional description the i 2 c module is comprised of both master and slave functions which are implemented as separate peripherals. for proper operation, the sda and scl pins must be connected to bi-directional open-drain pads. a typical i 2 c bus configuration is shown in figure 15-2 on page 376 . see i 2 c on page 581 for i 2 c timing diagrams. 375 september 02, 2007 preliminary lm3s8962 microcontroller i 2 c i /o select i 2 c master core interrupt i 2 c slave core i2cscl i2csda i2csda i2cscl i2csda i2cscl i2cmsa i2cmcs i2cmdr i2cmtpr i2cmimr i2cmris i2cmicr i2cmcr i2csoar i2cscsr i2csdr i2csim i2csris i2csmis i2csicr i2cmmis i 2 c control figure 15-2. i 2 c bus configuration 15.2.1 i 2 c bus functional overview the i 2 c bus uses only two signals: sda and scl, named i2csda and i2cscl on stellaris ? microcontrollers. sda is the bi-directional serial data line and scl is the bi-directional serial clock line. the bus is considered idle when both lines are high. every transaction on the i 2 c bus is nine bits long, consisting of eight data bits and a single acknowledge bit. the number of bytes per transfer (defined as the time between a valid st ar t and st op condition, described in st ar t and st op conditions on page 376 ) is unrestricted, but each byte has to be followed by an acknowledge bit, and data must be transferred msb first. when a receiver cannot receive another complete byte, it can hold the clock line scl low and force the transmitter into a wait state. the data transfer continues when the receiver releases the clock scl. 15.2.1.1 st art and st op conditions the protocol of the i 2 c bus defines two states to begin and end a transaction: st ar t and st op . a high-to-low transition on the sda line while the scl is high is defined as a st ar t condition, and a low-to-high transition on the sda line while scl is high is defined as a st op condition. the bus is considered busy after a st ar t condition and free after a st op condition. see figure 15-3 on page 376 . figure 15-3. st art and st op conditions 15.2.1.2 data format with 7-bit address data transfers follow the format shown in figure 15-4 on page 377 . after the st ar t condition, a slave address is sent. this address is 7-bits long followed by an eighth bit, which is a data direction bit ( r/s bit in the i2cmsa register). a zero indicates a transmit operation (send), and a one indicates a request for data (receive). a data transfer is always terminated by a st op condition generated by the master , however , a master can initiate communications with another device on the bus by generating a repeated st ar t condition and addressing another slave without first generating a st op condition. v arious combinations of receive/send formats are then possible within a single transfer . september 02, 2007 376 preliminary inter-integrated circuit (i 2 c) interface r pup stellar is tm i2cscl i2csd a r pup 3rd p ar ty de vice with i 2 c interf ace scl sd a i 2 c bus scl sd a 3rd p ar ty de vice with i 2 c interf ace scl sd a s t a r t c o n d i t i o n sd a sc l s t o p c o n d i t i o n sd a sc l figure 15-4. complete data t ransfer with a 7-bit address the first seven bits of the first byte make up the slave address (see figure 15-5 on page 377 ). the eighth bit determines the direction of the message. a zero in the r/s position of the first byte means that the master will write (send) data to the selected slave, and a one in this position means that the master will receive data from the slave. figure 15-5. r/s bit in first byte 15.2.1.3 data v alidity the data on the sda line must be stable during the high period of the clock, and the data line can only change when scl is low (see figure 15-6 on page 377 ). figure 15-6. data v alidity during bit t ransfer on the i 2 c bus 15.2.1.4 acknowledge all bus transactions have a required acknowledge clock cycle that is generated by the master . during the acknowledge cycle, the transmitter (which can be the master or slave) releases the sda line. t o acknowledge the transaction, the receiver must pull down sda during the acknowledge clock cycle. the data sent out by the receiver during the acknowledge cycle must comply with the data validity requirements described in data v alidity on page 377 . when a slave receiver does not acknowledge the slave address, sda must be left high by the slave so that the master can generate a st op condition and abort the current transfer . if the master device is acting as a receiver during a transfer , it is responsible for acknowledging each transfer made by the slave. since the master controls the number of bytes in the transfer , it signals the end of data to the slave transmitter by not generating an acknowledge on the last data byte. the slave transmitter must then release sda to allow the master to generate the st op or a repeated st ar t condition. 377 september 02, 2007 preliminary lm3s8962 microcontroller d a t a s l a v e a d d r e s s a c k l s b m s b a c k r / s l s b m s b s d a s c l 1 2 7 8 9 1 2 7 8 9 r / s l s b s l a v e a d d r e s s msb c h a n g e o f d a t a a l l o w e d d a t a l i n e s t a b l e s d a s c l 15.2.1.5 arbitration a master may start a transfer only if the bus is idle. it's possible for two or more masters to generate a st ar t condition within minimum hold time of the st ar t condition. in these situations, an arbitration scheme takes place on the sda line, while scl is high. during arbitration, the first of the competing master devices to place a '1' (high) on sda while another master transmits a '0' (low) will switch of f its data output stage and retire until the bus is idle again. arbitration can take place over several bits. its first stage is a comparison of address bits, and if both masters are trying to address the same device, arbitration continues on to the comparison of data bits. 15.2.2 a vailable speed modes the i 2 c clock rate is determined by the parameters: clk_prd , timer_prd , scl_lp , and scl_hp . where: clk_prd is the system clock period scl_lp is the low phase of scl (fixed at 6) scl_hp is the high phase of scl (fixed at 4) timer_prd is the programmed value in the i 2 c master t imer period (i2cmtpr) register (see page 395 ). the i 2 c clock period is calculated as follows: scl_period = 2*(1 + timer_prd)*(scl_lp + scl_hp)*clk_prd for example: clk_prd = 50 ns timer_prd = 2 scl_lp=6 scl_hp=4 yields a scl frequency of: 1/t = 333 khz t able 15-1 on page 378 gives examples of timer period, system clock, and speed mode (standard or fast). t able 15-1. examples of i 2 c master t imer period versus speed mode fast mode t imer period standard mode t imer period system clock - - 100 kbps 0x01 4 mhz - - 100 kbps 0x02 6 mhz 312 kbps 0x01 89 kbps 0x06 12.5 mhz 278 kbps 0x02 93 kbps 0x08 16.7 mhz 333 kbps 0x02 100 kbps 0x09 20 mhz 330 kbps 0x04 97.1 kbps 0x10 33mhz 400 kbps 0x04 100 kbps 0x13 40mhz 357 kbps 0x06 100 kbps 0x18 50mhz september 02, 2007 378 preliminary inter-integrated circuit (i 2 c) interface 15.2.3 interrupts the i 2 c can generate interrupts when the following conditions are observed: master transaction completed master transaction error slave transaction received slave transaction requested there is a separate interrupt signal for the i 2 c master and i 2 c modules. while both modules can generate interrupts for multiple conditions, only a single interrupt signal is sent to the interrupt controller . 15.2.3.1 i 2 c master interrupts the i 2 c master module generates an interrupt when a transaction completes (either transmit or receive), or when an error occurs during a transaction. t o enable the i 2 c master interrupt, software must write a '1' to the i 2 c master interrupt mask (i2cmimr) register . when an interrupt condition is met, software must check the error bit in the i 2 c master control/status (i2cmcs) register to verify that an error didn't occur during the last transaction. an error condition is asserted if the last transaction wasn't acknowledge by the slave or if the master was forced to give up ownership of the bus due to a lost arbitration round with another master . if an error is not detected, the application can proceed with the transfer . the interrupt is cleared by writing a '1' to the i 2 c master interrupt clear (i2cmicr) register . if the application doesn't require the use of interrupts, the raw interrupt status is always visible via the i 2 c master raw interrupt status (i2cmris) register . 15.2.3.2 i 2 c slave interrupts the slave module generates interrupts as it receives requests from an i 2 c master . t o enable the i 2 c slave interrupt, write a '1' to the i 2 c slave interrupt mask (i2csimr) register . software determines whether the module should write (transmit) or read (receive) data from the i 2 c slave data (i2csdr) register , by checking the rreq and treq bits of the i 2 c slave control/status (i2cscsr) register . if the slave module is in receive mode and the first byte of a transfer is received, the fbr bit is set along with the rreq bit. the interrupt is cleared by writing a '1' to the i 2 c slave interrupt clear (i2csicr) register . if the application doesn't require the use of interrupts, the raw interrupt status is always visible via the i 2 c slave raw interrupt status (i2csris) register . 15.2.4 loopback operation the i 2 c modules can be placed into an internal loopback mode for diagnostic or debug work. this is accomplished by setting the lpbk bit in the i 2 c master configuration (i2cmcr) register . in loopback mode, the sda and scl signals from the master and slave modules are tied together . 15.2.5 command sequence flow charts this section details the steps required to perform the various i 2 c transfer types in both master and slave mode. 379 september 02, 2007 preliminary lm3s8962 microcontroller 15.2.5.1 i 2 c master command sequences the figures that follow show the command sequences available for the i 2 c master . figure 15-7. master single send september 02, 2007 380 preliminary inter-integrated circuit (i 2 c) interface idle w rite slave address to i 2cmsa w rite data to i 2cmdr read i2cmcs sequence may be omitted in a single master system busbsy bit=0? no w rite --- 0 - 111 to i 2cmcs yes read i2cmcs busy bit=0? error bit=0? yes error service idle yes no no figure 15-8. master single receive 381 september 02, 2007 preliminary lm3s8962 microcontroller idle w rite slave address to i 2cmsa read i2cmcs sequence may be omitted in a single master system busbsy bit=0? no w rite --- 00111 to i 2cmcs yes read i2cmcs busy bit=0? error bit=0? yes error service idle no no read data from i 2cmdr yes figure 15-9. master burst send september 02, 2007 382 preliminary inter-integrated circuit (i 2 c) interface idle w rite slave address to i 2cmsa w rite data to i 2cmdr read i2cmcs busbsy bit=0? yes w rite --- 0 - 011 to i 2cmcs no read i2cmcs busy bit=0? yes error bit=0? yes arblst bit=1? w rite data to i 2cmdr w rite --- 0 - 100 to i 2cmcs index=n? no error service idle yes w rite --- 0 - 001 to i 2cmcs w rite --- 0 - 101 to i 2cmcs yes read i2cmcs busy bit=0? error bit=0? yes no idle yes error service no no no no sequence may be omitted in a single master system figure 15-10. master burst receive 383 september 02, 2007 preliminary lm3s8962 microcontroller idle w rite slave address to i 2cmsa read i2cmcs busbsy bit=0? no w rite --- 01011 to i 2cmcs yes read i2cmcs busy bit=0? no error bit=0? yes arblst bit=1? w rite --- 0 - 100 to i 2cmcs no error service yes idle read data from i 2cmdr index=m-1? w rite --- 00101 to i 2cmcs yes idle read data from i 2cmdr error service error bit=0? yes w rite --- 01001 to i 2cmcs read i2cmcs busy bit=0? no yes sequence may be omitted in a single master system no no no figure 15-1 1. master burst receive after burst send september 02, 2007 384 preliminary inter-integrated circuit (i 2 c) interface idle master operates in master t ransmit mode st op condition is not generated w rite slave address to i 2cmsa w rite --- 01011 to i 2cmcs master operates in master receive mode idle repeated st ar t condition is generated with changing data direction figure 15-12. master burst send after burst receive 15.2.5.2 i 2 c slave command sequences figure 15-13 on page 386 presents the command sequence available for the i 2 c slave. 385 september 02, 2007 preliminary lm3s8962 microcontroller idle master operates in master receive mode st op condition is not generated w rite slave address to i 2cmsa w rite --- 0 - 011 to i 2cmcs master operates in master t ransmit mode idle repeated st ar t condition is generated with changing data direction figure 15-13. slave command sequence 15.3 initialization and configuration the following example shows how to configure the i 2 c module to send a single byte as a master . this assumes the system clock is 20 mhz. 1. enable the i 2 c clock by writing a value of 0x0000.1000 to the rcgc1 register in the system control module. 2. enable the clock to the appropriate gpio module via the rcgc2 register in the system control module. 3. in the gpio module, enable the appropriate pins for their alternate function using the gpioafsel register . also, be sure to enable the same pins for open drain operation. 4. initialize the i 2 c master by writing the i2cmcr register with a value of 0x0000.0020. 5. set the desired scl clock speed of 100 kbps by writing the i2cmtpr register with the correct value. the value written to the i2cmtpr register represents the number of system clock periods in one scl clock period. the tpr value is determined by the following equation: september 02, 2007 386 preliminary inter-integrated circuit (i 2 c) interface idle w rite own slave address to i 2csoar w rite ------- 1 to i 2cscsr read i2cscsr rreq bit=1? read data from i 2csdr yes treq bit=1? no w rite data to i 2csdr yes no fbr is also valid tpr = (system clock / (2 * (scl_lp + scl_hp) * scl_clk)) - 1; tpr = (20mhz / (2 * (6 + 4) * 100000)) - 1; tpr = 9 w rite the i2cmtpr register with the value of 0x0000.0009. 6. specify the slave address of the master and that the next operation will be a send by writing the i2cmsa register with a value of 0x0000.0076. this sets the slave address to 0x3b. 7. place data (byte) to be sent in the data register by writing the i2cmdr register with the desired data. 8. initiate a single byte send of the data from master to slave by writing the i2cmcs register with a value of 0x0000.0007 (st op , st ar t , run). 9. w ait until the transmission completes by polling the i2cmcs register s busbsy bit until it has been cleared. 15.4 i 2 c register map t able 15-2 on page 387 lists the i 2 c registers. all addresses given are relative to the i 2 c base addresses for the master and slave: i 2 c master 0: 0x4002.0000 i 2 c slave 0: 0x4002.0800 t able 15-2. inter-integrated circuit (i 2 c) interface register map see page description reset t ype name offset i 2 c master 389 i2c master slave address 0x0000.0000 r/w i2cmsa 0x000 390 i2c master control/status 0x0000.0000 r/w i2cmcs 0x004 394 i2c master data 0x0000.0000 r/w i2cmdr 0x008 395 i2c master t imer period 0x0000.0001 r/w i2cmtpr 0x00c 396 i2c master interrupt mask 0x0000.0000 r/w i2cmimr 0x010 397 i2c master raw interrupt status 0x0000.0000 ro i2cmris 0x014 398 i2c master masked interrupt status 0x0000.0000 ro i2cmmis 0x018 399 i2c master interrupt clear 0x0000.0000 wo i2cmicr 0x01c 400 i2c master configuration 0x0000.0000 r/w i2cmcr 0x020 i 2 c slave 402 i2c slave own address 0x0000.0000 r/w i2csoar 0x000 403 i2c slave control/status 0x0000.0000 ro i2cscsr 0x004 405 i2c slave data 0x0000.0000 r/w i2csdr 0x008 406 i2c slave interrupt mask 0x0000.0000 r/w i2csimr 0x00c 387 september 02, 2007 preliminary lm3s8962 microcontroller see page description reset t ype name offset 407 i2c slave raw interrupt status 0x0000.0000 ro i2csris 0x010 408 i2c slave masked interrupt status 0x0000.0000 ro i2csmis 0x014 409 i2c slave interrupt clear 0x0000.0000 wo i2csicr 0x018 15.5 register descriptions (i 2 c master) the remainder of this section lists and describes the i 2 c master registers, in numerical order by address of fset. see also register descriptions (i2c slave) on page 401 . september 02, 2007 388 preliminary inter-integrated circuit (i 2 c) interface register 1: i 2 c master slave address (i2cmsa), offset 0x000 this register consists of eight bits: seven address bits (a6-a0), and a receive/send bit, which determines if the next operation is a receive (high), or send (low). i2c master slave address (i2cmsa) i2c master 0 base: 0x4002.0000 of fset 0x000 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 r/s sa reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 i 2 c slave address this field specifies bits a6 through a0 of the slave address. 0 r/w sa 7:1 receive/send the r/s bit specifies if the next operation is a receive (high) or send (low). 0: send 1: receive 0 r/w r/s 0 389 september 02, 2007 preliminary lm3s8962 microcontroller register 2: i 2 c master control/status (i2cmcs), offset 0x004 this register accesses four control bits when written, and accesses seven status bits when read. the status register consists of seven bits, which when read determine the state of the i 2 c bus controller . the control register consists of four bits: the run , start , stop , and ack bits. the start bit causes the generation of the st ar t , or repea ted st ar t condition. the stop bit determines if the cycle stops at the end of the data cycle, or continues on to a burst. t o generate a single send cycle, the i 2 c master slave address (i2cmsa) register is written with the desired address, the r/s bit is set to 0, and the control register is written with ack =x (0 or 1), stop =1, start =1, and run =1 to perform the operation and stop. when the operation is completed (or aborted due an error), the interrupt pin becomes active and the data may be read from the i2cmdr register . when the i 2 c module operates in master receiver mode, the ack bit must be set normally to logic 1. this causes the i 2 c bus controller to send an acknowledge automatically after each byte. this bit must be reset when the i 2 c bus controller requires no further data to be sent from the slave transmitter . read-only status register i2c master control/status (i2cmcs) i2c master 0 base: 0x4002.0000 of fset 0x004 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 busy error adrack da t ack arblst idle busbsy reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:7 bus busy this bit specifies the state of the i 2 c bus. if set, the bus is busy; otherwise, the bus is idle. the bit changes based on the st ar t and st op conditions. 0 ro busbsy 6 i 2 c idle this bit specifies the i 2 c controller state. if set, the controller is idle; otherwise the controller is not idle. 0 ro idle 5 arbitration lost this bit specifies the result of bus arbitration. if set, the controller lost arbitration; otherwise, the controller won arbitration. 0 ro arblst 4 september 02, 2007 390 preliminary inter-integrated circuit (i 2 c) interface description reset t ype name bit/field acknowledge data this bit specifies the result of the last data operation. if set, the transmitted data was not acknowledged; otherwise, the data was acknowledged. 0 ro da t ack 3 acknowledge address this bit specifies the result of the last address operation. if set, the transmitted address was not acknowledged; otherwise, the address was acknowledged. 0 ro adrack 2 error this bit specifies the result of the last bus operation. if set, an error occurred on the last operation; otherwise, no error was detected. the error can be from the slave address not being acknowledged, the transmit data not being acknowledged, or because the controller lost arbitration. 0 ro error 1 i 2 c busy this bit specifies the state of the controller . if set, the controller is busy; otherwise, the controller is idle. when the busy bit is set, the other status bits are not valid. 0 ro busy 0 w rite-only control register i2c master control/status (i2cmcs) i2c master 0 base: 0x4002.0000 of fset 0x004 t ype wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 run st ar t st op ack reserved wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 wo reserved 31:4 data acknowledge enable when set, causes received data byte to be acknowledged automatically by the master . see field decoding in t able 15-3 on page 392 . 0 wo ack 3 generate st op when set, causes the generation of the st op condition. see field decoding in t able 15-3 on page 392 . 0 wo st op 2 391 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field generate st ar t when set, causes the generation of a st ar t or repeated st ar t condition. see field decoding in t able 15-3 on page 392 . 0 wo st ar t 1 i 2 c master enable when set, allows the master to send or receive data. see field decoding in t able 15-3 on page 392 . 0 wo run 0 t able 15-3. w rite field decoding for i2cmcs[3:0] field (sheet 1 of 3) description i2cmcs[3:0] i2cmsa[0] current state run st art st op ack r/s st ar t condition followed by send (master goes to the master t ransmit state). 1 1 0 x a 0 idle st ar t condition followed by a send and st op condition (master remains in idle state). 1 1 1 x 0 st ar t condition followed by receive operation with negative ack (master goes to the master receive state). 1 1 0 0 1 st ar t condition followed by receive and st op condition (master remains in idle state). 1 1 1 0 1 st ar t condition followed by receive (master goes to the master receive state). 1 1 0 1 1 illegal. 1 1 1 1 1 nop . all other combinations not listed are non-operations. send operation (master remains in master t ransmit state). 1 0 0 x x master t ransmit st op condition (master goes to idle state). 0 0 1 x x send followed by st op condition (master goes to idle state). 1 0 1 x x repeated st ar t condition followed by a send (master remains in master t ransmit state). 1 1 0 x 0 repeated st ar t condition followed by send and st op condition (master goes to idle state). 1 1 1 x 0 repeated st ar t condition followed by a receive operation with a negative ack (master goes to master receive state). 1 1 0 0 1 repeated st ar t condition followed by a send and st op condition (master goes to idle state). 1 1 1 0 1 repeated st ar t condition followed by receive (master goes to master receive state). 1 1 0 1 1 illegal. 1 1 1 1 1 nop . all other combinations not listed are non-operations. september 02, 2007 392 preliminary inter-integrated circuit (i 2 c) interface description i2cmcs[3:0] i2cmsa[0] current state run st art st op ack r/s receive operation with negative ack (master remains in master receive state). 1 0 0 0 x master receive st op condition (master goes to idle state). b 0 0 1 x x receive followed by st op condition (master goes to idle state). 1 0 1 0 x receive operation (master remains in master receive state). 1 0 0 1 x illegal. 1 0 1 1 x repeated st ar t condition followed by receive operation with a negative ack (master remains in master receive state). 1 1 0 0 1 repeated st ar t condition followed by receive and st op condition (master goes to idle state). 1 1 1 0 1 repeated st ar t condition followed by receive (master remains in master receive state). 1 1 0 1 1 repeated st ar t condition followed by send (master goes to master t ransmit state). 1 1 0 x 0 repeated st ar t condition followed by send and st op condition (master goes to idle state). 1 1 1 x 0 nop . all other combinations not listed are non-operations. a. an x in a table cell indicates the bit can be 0 or 1. b. in master receive mode, a st op condition should be generated only after a data negative acknowledge executed by the master or an address negative acknowledge executed by the slave. 393 september 02, 2007 preliminary lm3s8962 microcontroller register 3: i 2 c master data (i2cmdr), offset 0x008 this register contains the data to be transmitted when in the master t ransmit state, and the data received when in the master receive state. i2c master data (i2cmdr) i2c master 0 base: 0x4002.0000 of fset 0x008 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 da t a reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 data t ransferred data transferred during transaction. 0x00 r/w da t a 7:0 september 02, 2007 394 preliminary inter-integrated circuit (i 2 c) interface register 4: i 2 c master t imer period (i2cmtpr), offset 0x00c this register specifies the period of the scl clock. i2c master t imer period (i2cmtpr) i2c master 0 base: 0x4002.0000 of fset 0x00c t ype r/w , reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 tpr reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 scl clock period this field specifies the period of the scl clock. scl_prd = 2*(1 + tpr)*(scl_lp + scl_hp)*clk_prd where: scl_prd is the scl line period (i 2 c clock). tpr is the t imer period register value (range of 1 to 255). scl_lp is the scl low period (fixed at 6). scl_hp is the scl high period (fixed at 4). 0x1 r/w tpr 7:0 395 september 02, 2007 preliminary lm3s8962 microcontroller register 5: i 2 c master interrupt mask (i2cmimr), offset 0x010 this register controls whether a raw interrupt is promoted to a controller interrupt. i2c master interrupt mask (i2cmimr) i2c master 0 base: 0x4002.0000 of fset 0x010 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 im reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 interrupt mask this bit controls whether a raw interrupt is promoted to a controller interrupt. if set, the interrupt is not masked and the interrupt is promoted; otherwise, the interrupt is masked. 0 r/w im 0 september 02, 2007 396 preliminary inter-integrated circuit (i 2 c) interface register 6: i 2 c master raw interrupt status (i2cmris), offset 0x014 this register specifies whether an interrupt is pending. i2c master raw interrupt status (i2cmris) i2c master 0 base: 0x4002.0000 of fset 0x014 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 raw interrupt status this bit specifies the raw interrupt state (prior to masking) of the i 2 c master block. if set, an interrupt is pending; otherwise, an interrupt is not pending. 0 ro ris 0 397 september 02, 2007 preliminary lm3s8962 microcontroller register 7: i 2 c master masked interrupt status (i2cmmis), offset 0x018 this register specifies whether an interrupt was signaled. i2c master masked interrupt status (i2cmmis) i2c master 0 base: 0x4002.0000 of fset 0x018 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 mis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 masked interrupt status this bit specifies the raw interrupt state (after masking) of the i 2 c master block. if set, an interrupt was signaled; otherwise, an interrupt has not been generated since the bit was last cleared. 0 ro mis 0 september 02, 2007 398 preliminary inter-integrated circuit (i 2 c) interface register 8: i 2 c master interrupt clear (i2cmicr), offset 0x01c this register clears the raw interrupt. i2c master interrupt clear (i2cmicr) i2c master 0 base: 0x4002.0000 of fset 0x01c t ype wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ic reserved wo ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 interrupt clear this bit controls the clearing of the raw interrupt. a write of 1 clears the interrupt; otherwise, a write of 0 has no af fect on the interrupt state. a read of this register returns no meaningful data. 0 wo ic 0 399 september 02, 2007 preliminary lm3s8962 microcontroller register 9: i 2 c master configuration (i2cmcr), offset 0x020 this register configures the mode (master or slave) and sets the interface for test mode loopback. i2c master configuration (i2cmcr) i2c master 0 base: 0x4002.0000 of fset 0x020 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 lpbk reserved mfe sfe reserved r/w ro ro ro r/w r/w ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:6 i 2 c slave function enable this bit specifies whether the interface may operate in slave mode. if set, slave mode is enabled; otherwise, slave mode is disabled. 0 r/w sfe 5 i 2 c master function enable this bit specifies whether the interface may operate in master mode. if set, master mode is enabled; otherwise, master mode is disabled and the interface clock is disabled. 0 r/w mfe 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 3:1 i 2 c loopback this bit specifies whether the interface is operating normally or in loopback mode. if set, the device is put in a test mode loopback configuration; otherwise, the device operates normally . 0 r/w lpbk 0 september 02, 2007 400 preliminary inter-integrated circuit (i 2 c) interface 15.6 register descriptions (i2c slave) the remainder of this section lists and describes the i 2 c slave registers, in numerical order by address of fset. see also register descriptions (i 2 c master) on page 388 . 401 september 02, 2007 preliminary lm3s8962 microcontroller register 10: i 2 c slave own address (i2csoar), offset 0x000 this register consists of seven address bits that identify the stellaris ? i 2 c device on the i 2 c bus. i2c slave own address (i2csoar) i2c slave 0 base: 0x4002.0800 of fset 0x000 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 oar reserved r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:7 i 2 c slave own address this field specifies bits a6 through a0 of the slave address. 0x00 r/w oar 6:0 september 02, 2007 402 preliminary inter-integrated circuit (i 2 c) interface register 1 1: i 2 c slave control/status (i2cscsr), offset 0x004 this register accesses one control bit when written, and three status bits when read. the read-only status register consists of three bits: the fbr , rreq , and treq bits. the first byte received (fbr) bit is set only after the stellaris ? device detects its own slave address and receives the first data byte from the i 2 c master . the receive request (rreq) bit indicates that the stellaris ? i 2 c device has received a data byte from an i 2 c master . read one data byte from the i 2 c slave data (i2csdr) register to clear the rreq bit. the transmit request (treq) bit indicates that the stellaris ? i 2 c device is addressed as a slave t ransmitter . w rite one data byte into the i 2 c slave data (i2csdr) register to clear the treq bit. the write-only control register consists of one bit: the da bit. the da bit enables and disables the stellaris ? i 2 c slave operation. read-only status register i2c slave control/status (i2cscsr) i2c slave 0 base: 0x4002.0800 of fset 0x004 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 rreq treq fbr reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:3 first byte received indicates that the first byte following the slave s own address is received. this bit is only valid when the rreq bit is set, and is automatically cleared when data has been read from the i2csdr register . note: this bit is not used for slave transmit operations. 0 ro fbr 2 t ransmit request this bit specifies the state of the i 2 c slave with regards to outstanding transmit requests. if set, the i 2 c unit has been addressed as a slave transmitter and uses clock stretching to delay the master until data has been written to the i2csdr register . otherwise, there is no outstanding transmit request. 0 ro treq 1 receive request this bit specifies the status of the i 2 c slave with regards to outstanding receive requests. if set, the i 2 c unit has outstanding receive data from the i 2 c master and uses clock stretching to delay the master until the data has been read from the i2csdr register . otherwise, no receive data is outstanding. 0 ro rreq 0 403 september 02, 2007 preliminary lm3s8962 microcontroller w rite-only control register i2c slave control/status (i2cscsr) i2c slave 0 base: 0x4002.0800 of fset 0x004 t ype wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 da reserved wo ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 device active 1=enables the i 2 c slave operation. 0=disables the i 2 c slave operation. 0 wo da 0 september 02, 2007 404 preliminary inter-integrated circuit (i 2 c) interface register 12: i 2 c slave data (i2csdr), offset 0x008 this register contains the data to be transmitted when in the slave t ransmit state, and the data received when in the slave receive state. i2c slave data (i2csdr) i2c slave 0 base: 0x4002.0800 of fset 0x008 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 da t a reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:8 data for t ransfer this field contains the data for transfer during a slave receive or transmit operation. 0x0 r/w da t a 7:0 405 september 02, 2007 preliminary lm3s8962 microcontroller register 13: i 2 c slave interrupt mask (i2csimr), offset 0x00c this register controls whether a raw interrupt is promoted to a controller interrupt. i2c slave interrupt mask (i2csimr) i2c slave 0 base: 0x4002.0800 of fset 0x00c t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 im reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 interrupt mask this bit controls whether a raw interrupt is promoted to a controller interrupt. if set, the interrupt is not masked and the interrupt is promoted; otherwise, the interrupt is masked. 0 r/w im 0 september 02, 2007 406 preliminary inter-integrated circuit (i 2 c) interface register 14: i 2 c slave raw interrupt status (i2csris), offset 0x010 this register specifies whether an interrupt is pending. i2c slave raw interrupt status (i2csris) i2c slave 0 base: 0x4002.0800 of fset 0x010 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ris reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 raw interrupt status this bit specifies the raw interrupt state (prior to masking) of the i 2 c slave block. if set, an interrupt is pending; otherwise, an interrupt is not pending. 0 ro ris 0 407 september 02, 2007 preliminary lm3s8962 microcontroller register 15: i 2 c slave masked interrupt status (i2csmis), offset 0x014 this register specifies whether an interrupt was signaled. i2c slave masked interrupt status (i2csmis) i2c slave 0 base: 0x4002.0800 of fset 0x014 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 mis reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 masked interrupt status this bit specifies the raw interrupt state (after masking) of the i 2 c slave block. if set, an interrupt was signaled; otherwise, an interrupt has not been generated since the bit was last cleared. 0 ro mis 0 september 02, 2007 408 preliminary inter-integrated circuit (i 2 c) interface register 16: i 2 c slave interrupt clear (i2csicr), offset 0x018 this register clears the raw interrupt. i2c slave interrupt clear (i2csicr) i2c slave 0 base: 0x4002.0800 of fset 0x018 t ype wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ic reserved wo ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 clear interrupt this bit controls the clearing of the raw interrupt. a write of 1 clears the interrupt; otherwise a write of 0 has no af fect on the interrupt state. a read of this register returns no meaningful data. 0 wo ic 0 409 september 02, 2007 preliminary lm3s8962 microcontroller 16 controller area network (can) module 16.1 controller area network overview controller area network (can) is a multicast shared serial bus standard for connecting electronic control units (ecus). can was specifically designed to be robust in electromagnetically noisy environments and can utilize a dif ferential balanced line like rs-485 or a more robust twisted-pair wire. originally created for automotive purposes, it is also used in many embedded control applications (such as industrial and medical). bit rates up to 1 mbps are possible at network lengths below 40 meters. decreased bit rates allow longer network distances (for example, 125 kbps at 500 m). 16.2 controller area network features the stellaris ? can module supports the following features: can protocol version 2.0 part a/b bit rates up to 1 mbps 32 message objects each message object has its own identifier mask maskable interrupt disable automatic retransmission mode for t ime t riggered can (ttcan) applications programmable loopback mode for self-test operation programmable fifo mode gluelessly attach to an external can phy through the can0tx and can0rx pins september 02, 2007 410 preliminary controller area network (can) module 16.3 controller area network block diagram figure 16-1. can module block diagram 41 1 september 02, 2007 preliminary lm3s8962 microcontroller canctl cansts canbit canint cantst canbrpe can control canif1crq canif1cmsk canif1msk1 canif1msk2 canif1arb1 canif1arb2 canif1da1 canif1da2 canif1mctl apb interface apb pins can core message ram 32 message objects canif1db1 canif1db2 canif2crq canif2cmsk canif2msk1 canif2msk2 canif2arb1 canif2arb2 canif2da1 canif2da2 canif2mctl canif2db1 canif2db2 can tx/rx 16.4 controller area network functional description the can module conforms to the can protocol version 2.0 (parts a and b). message transfers that include data, remote, error , and overload frames with an 1 1-bit identifier (standard) or a 29-bit identifier (extended) are supported. t ransfer rates can be programmed up to 1 mbps. the can module consists of three major parts: can protocol controller and message handler message memory can register interface the protocol controller transfers and receives the serial data from the can bus and passes the data on to the message handler . the message handler then loads this information into the appropriate message object based on the current filtering and identifiers in the message object memory . the message handler is also responsible for generating interrupts based on events on the can bus. the message object memory is a set of 32 identical memory blocks that hold the current configuration, status, and actual data for each message object. these are accessed via the can message object register interface. the message memory is not directly accessable in the stellaris ? memory map, so the stellaris ? can controller provides an interface to communicate with the message memory . the can message object register interface provides two register sets for communicating with the message objects. since there is no direct access to the message object memory , these two interfaces must be used to read or write to each message object. the two message object interfaces allow parallel access to the can controller message objects when multiple objects may have new information that needs to be processed. 16.4.1 initialization the software initialization is started by setting the init bit in the can control (canctl) register , with software or by a hardware reset, or by going bus-of f, which occurs when the transmitter's error counter exceeds a count of 255. while init is set, all message transfers to and from the can bus are stopped and the status of the can transmit output is recessive (high). entering the initialization state does not change the configuration of the can controller , the message objects, or the error counters. however , some configuration registers are only accessible when in the initialization state. t o initialize the can controller , set the can bit t iming (canbit) register and configure each message object. if a message object is not needed, it is suf ficient to set it as not valid by clearing the msgval bit in the canifnarb2 register . otherwise, the whole message object has to be initialized, as the fields of the message object may not have valid information causing unexpected results. access to the can bit t iming (canbit) register and to the can baud rate prescalar extension (canbrpe) register to configure the bit timing are enabled when both the init and cce bits in the canctl register are set. t o leave the initialization state, the init bit must be cleared. afterwards, the internal bit stream processor (bsp) synchronizes itself to the data transfer on the can bus by waiting for the occurrence of a sequence of 1 1 consecutive recessive bits (bus idle) before it takes part in bus activities and starts message transfers. the initialization of the message objects is independent of being in the initialization state and can be done on the fly , but message objects should all be configured to particular identifiers or set to not valid before the bsp starts the message transfer . t o change the configuration of a message object during normal operation, set the msgval bit in the canifnarb2 register to 0 (not valid). when the configuration is completed, msgval is set to 1 again (valid). september 02, 2007 412 preliminary controller area network (can) module 16.4.2 operation once the can module is initialized and the init bit in the canctl register is reset to 0, the can module synchronizes itself to the can bus and starts the message transfer . as messages are received, they are stored in their appropriate message objects if they pass the message handler's filtering. the whole message (including all arbitration bits, data-length code, and eight data bytes) is stored in the message object. if the identifier mask (the msk bits in the canifnmskn registers) is used, the arbitration bits which are masked to "don't care" may be overwritten in the message object. the cpu may read or write each message any time via the can interface registers ( canifncrq , canifncmsk , canifnmskn , canifnarbn , canifnmctl , canifndan , and canifndbn ). the message handler guarantees data consistency in case of concurrent accesses. the transmission of message objects are under the control of the software that is managing the can hardware. these can be message objects used for one-time data transfers, or permanent message objects used to respond in a more periodic manner . permanent message objects have all arbitration and control set up, and only the data bytes are updated. t o start the transmission, the txrqst bit in the cantxrqn register and the newdat bit in the cannwdan register are set. if several transmit messages are assigned to the same message object (when the number of message objects is not suf ficient), the whole message object has to be configured before the transmission of this message is requested. the transmission of any number of message objects may be requested at the same time; they are transmitted according to their internal priority , which is based on the message identifier for the message object. messages may be updated or set to not valid any time, even when their requested transmission is still pending. the old data is discarded when a message is updated before its pending transmission has started. depending on the configuration of the message object, the transmission of a message may be requested autonomously by the reception of a remote frame with a matching identifier . there are two sets of can interface registers ( canif1x and canif2x ), which are used to access the message objects in the message ram. the can controller coordinates transfers to and from the message ram to and from the registers. the function of the two sets are independent and identical and can be used to queue transactions. 16.4.3 t ransmitting message objects if the internal transmit shift register of the can module is ready for loading, and if there is no data transfer between the can interface registers and message ram, the valid message object with the highest priority and that has a pending transmission request is loaded into the transmit shift register by the message handler and the transmission is started. the message object's newdat bit is reset and can be viewed in the cannwdan register . after a successful transmission, and if no new data was written to the message object since the start of the transmission, the txrqst bit in the canifncmsk register is reset. if the txie bit in the canifnmctl register is set, the intpnd bit in the canifnmctl register is set after a successful transmission. if the can module has lost the arbitration or if an error occurred during the transmission, the message is re-transmitted as soon as the can bus is free again. if, meanwhile, the transmission of a message with higher priority has been requested, the messages are transmitted in the order of their priority . 16.4.4 configuring a t ransmit message object t able 16-1 on page 414 specifies the bit settings for a transmit message object. 413 september 02, 2007 preliminary lm3s8962 microcontroller t able 16-1. t ransmit message object bit settings canifnmctl canifnarb2 canifnmctl canifncmsk canifnarb2 register txrqst rmten intpnd txie rxie msglst newdat dir eob mask data arb msgv al bit 0 appl 0 appl 0 0 0 1 1 appl appl appl 1 v alue the xtd and id bit fields in the canifnarbn registers are set by an application. they define the identifier and type of the outgoing message. if an 1 1-bit identifier (standard frame) is used, it is programmed to bits [28:18] of canifnarb1 , as bits 17:0 of canifnarbn are not used by the can controller for 1 1-bit identifiers. if the txie bit is set, the intpnd bit is set after a successful transmission of the message object. if the rmten bit is set, a matching received remote frame causes the txrqst bit to be set and the remote frame is autonomously answered by a data frame with the data from the message object. the dlc bit in the canifnmctl register is set by an application. txrqst and rmten may not be set before the data is valid. the can mask registers ( msk bits in canifnmskn , umask bit in canifnmctl register , and mxtd and mdir bits in canifnmsk2 register) may be used ( umask =1) to allow groups of remote frames with similar identifiers to set the txrqst bit. the dir bit should not be masked. 16.4.5 updating a t ransmit message object the cpu may update the data bytes of a t ransmit message object any time via the can interface registers and neither the msgval nor the txrqst bits have to be reset before the update. even if only a part of the data bytes are to be updated, all four bytes of the corresponding canifndan or canifndbn register have to be valid before the content of that register is transferred to the message object. either the cpu has to write all four bytes into the canifndan or canifndbn register or the message object is transferred to the canifndan or canifndbn register before the cpu writes the new data bytes. in order to only update the data in a message object, the wr , newdat , dataa , and datab bits are written to the can ifn command mask (canifnmskn) register , followed by writing the can ifn data registers, and then the number of the message object is written to the can ifn command request (canifncrq) register , to update the data bytes and the txrqst bit at the same time. t o prevent the reset of txrqst at the end of a transmission that may already be in progress while the data is updated, newdat has to be set together with txrqst . when newdat is set together with txrqst , newdat is reset as soon as the new transmission has started. 16.4.6 accepting received message objects when the arbitration and control field ( id + xtd + rmten + dlc ) of an incoming message is completely shifted into the can module, the message handling capability of the module starts scanning the message ram for a matching valid message object. t o scan the message ram for a matching message object, the acceptance filtering unit is loaded with the arbitration bits from the core. then the arbitration and mask fields (including msgval , umask , newdat , and eob ) of message object 1 are loaded into the acceptance filtering unit and compared with the arbitration field from the shift register . this is repeated with each following message object until a matching message object is found or until the end of the message ram is reached. if a match occurs, the scanning is stopped and the message handler proceeds depending on the type of frame received. september 02, 2007 414 preliminary controller area network (can) module 16.4.7 receiving a data frame the message handler stores the message from the can module receive shift register into the respective message object in the message ram. it stores the data bytes, all arbitration bits, and the data length code into the corresponding message object. this is implemented to keep the data bytes connected with the identifier even if arbitration mask registers are used. the canifnmctl.newdat bit is set to indicate that new data has been received. the cpu should reset canifnmctl.newdat when it reads the message object to indicate to the controller that the message has been received and the buf fer is free to receive more messages. if the can controller receives a message and the canifnmctl.newdat bit was already set, the msglst bit is set to indicate that the previous data was lost. if the canifnmctl.rxie bit is set, the canifnmctl.intpnd bit is set, causing the canint interrupt register to point to the message object that just received a message. the canifnmctl.txrqst bit of this message object is reset to prevent the transmission of a remote frame, while the requested data frame has just been received. 16.4.8 receiving a remote frame when a remote frame is received, three dif ferent configurations of the matching message object have to be considered: dir = 1 (direction = transmit), rmten = 1, umask = 1 or 0 at the reception of a matching remote frame, the txrqst bit of this message object is set. the rest of the message object remains unchanged. dir = 1 (direction = transmit), rmten = 0, umask = 0 at the reception of a matching remote frame, the txrqst bit of this message object remains unchanged; the remote frame is ignored. this remote frame is disabled and will not automatically respond or indicate that the remote frame ever happened. dir = 1 (direction = transmit), rmten = 0, umask = 1 at the reception of a matching remote frame, the txrqst bit of this message object is reset. the arbitration and control field ( id + xtd + rmten + dlc ) from the shift register is stored into the message object in the message ram and the newdat bit of this message object is set. the data field of the message object remains unchanged; the remote frame is treated similar to a received data frame. this is useful for a remote data request from another can device for which the stellaris ? controller does not have readily available data. the software must fill the data and answer the frame manually . 16.4.9 receive/t ransmit priority the receive/transmit priority for the message objects is controlled by the message number . message object 1 has the highest priority , while message object 32 has the lowest priority . if more than one transmission request is pending, the message objects are transmitted in order based on the message object with the lowest message number . this should not be confused with the message identifier as that priority is enforced by the can bus. this means that if message object 1 and message object 2 both have valid messages that need to be transmitted, message object 1 will always be transmitted first regardless of the message identifier in the message object itself. 16.4.10 configuring a receive message object t able 16-2 on page 416 specifies the bit settings for a transmit message object. 415 september 02, 2007 preliminary lm3s8962 microcontroller t able 16-2. receive message object bit settings canifnmctl canifnarb2 canifnmctl canifncmsk canifnarb2 register txrqst rmten intpnd txie rxie msglst newdat dir eob mask data arb msgv al bit 0 0 0 0 appl 0 0 0 1 appl appl appl 1 v alue the xtd and id bit fields in the canifnarbn registers are set by an application. they define the identifier and type of accepted received messages. if an 1 1-bit identifier (standard frame) is used, it is programmed to bits [28:18] of canifnarb1 , and bits [17:0] are ignored by the can controller . when a data frame with an 1 1-bit identifier is received, bits [17:0] are set to 0. if the rxie bit is set, the intpnd bit is set when a received data frame is accepted and stored in the message object. when the message handler stores a data frame in the message object, it stores the received data length code and eight data bytes. if the data length code is less than 8, the remaining bytes of the message object are overwritten by nonspecified values. the can mask registers ( msk bits in canifnmskn , umask bit in canifnmctl register , and mxtd and mdir bits in canifnmsk2 register) may be used ( umask =1) to allow groups of data frames with similar identifiers to be accepted. the dir bit should not be masked in typical applications. 16.4.1 1 handling of received message objects the cpu may read a received message any time via the can interface registers because the data consistency is guaranteed by the message handler state machine. t ypically , the cpu first writes 0x007f to the can ifn command mask (canifncmsk) register and then writes the number of the message object to the can ifn command request (canifncrq) register . that combination transfers the whole received message from the message ram into the message buf fer registers ( canifnmskn , canifnarbn , and canifnmctl ). additionally , the newdat and intpnd bits are cleared in the message ram, acknowledging that the message has been read and clearing the pending interrupt being generated by this message object. if the message object uses masks for acceptance filtering, the arbitration bits show which of the matching messages has been received. the actual value of newdat shows whether a new message has been received since the last time this message object was read. the actual value of msglst shows whether more than one message has been received since the last time this message object was read. msglst is not automatically reset. using a remote frame, the cpu may request new data from another can node on the can bus. setting the txrqst bit of a receive object causes the transmission of a remote frame with the receive object's identifier . this remote frame triggers the other can node to start the transmission of the matching data frame. if the matching data frame is received before the remote frame could be transmitted, the txrqst bit is automatically reset. this prevents the possible loss of data when the other device on the can bus has already transmitted the data, slightly earlier than expected. 16.4.12 handling of interrupts if several interrupts are pending, the can interrupt (canint) register points to the pending interrupt with the highest priority , disregarding their chronological order . an interrupt remains pending until the cpu has cleared it. september 02, 2007 416 preliminary controller area network (can) module the status interrupt has the highest priority . among the message interrupts, the message object's interrupt priority decreases with increasing message number . a message interrupt is cleared by clearing the message object's intpnd bit. the status interrupt is cleared by reading the can status (cansts) register . the interrupt identifier intid in the canint register indicates the cause of the interrupt. when no interrupt is pending, the register holds the value to 0. if the value of canint is dif ferent from 0, then there is an interrupt pending. if the ie bit is set in the canctl register , the interrupt line to the cpu is active. the interrupt line remains active until canint is 0, all interrupt sources have been cleared, (the cause of the interrupt is reset), or until ie is reset, which disables interrupts from the can controller . the value 0x8000 in the canint register indicates that an interrupt is pending because the can module has updated, but not necessarily changed, the cansts register (error interrupt or status interrupt). this indicates that there is either a new error interrupt or a new status interrupt. a write access can clear the rxok , txok , and lec flags in the cansts register , however , only a read access to the cansts register will clear the source of the status interrupt. intid points to the pending message interrupt with the highest interrupt priority . the sie bit in the canctl register controls whether a change of the status register may cause an interrupt. the eie bit in the canctl register controls whether any interrupt from the can controller actually generates an interrupt to the microcontroller's interrupt controller . the canint interrupt register is updated even when the ie bit is set to zero. there are two possibilities when handling the source of a message interrupt. the first is to read the intid bit in the canint interrupt register to determine the highest priority interrupt that is pending, and the second is to read the can message interrupt pending (canmsgnint) register to see all of the message objects that have pending interrupts. an interrupt service routine reading the message that is the source of the interrupt may read the message and reset the message object's intpnd at the same time by setting the clrintpnd bit in the can ifn command mask (canifncmsk) register . when the intpnd bit is cleared, the canint register will contain the message number for the next message object with a pending interrupt. 16.4.13 bit t iming configuration error considerations even if minor errors in the configuration of the can bit timing do not result in immediate failure, the performance of a can network can be reduced significantly . in many cases, the can bit synchronization amends a faulty configuration of the can bit timing to such a degree that only occasionally an error frame is generated. in the case of arbitration, however , when two or more can nodes simultaneously try to transmit a frame, a misplaced sample point may cause one of the transmitters to become error passive. the analysis of such sporadic errors requires a detailed knowledge of the can bit synchronization inside a can node and of the can nodes' interaction on the can bus. 16.4.14 bit t ime and bit rate the can system supports bit rates in the range of lower than 1 kbps up to 1000 kbps. each member of the can network has its own clock generator . the timing parameter of the bit time can be configured individually for each can node, creating a common bit rate even though the can nodes' oscillator periods may be dif ferent. because of small variations in frequency caused by changes in temperature or voltage and by deteriorating components, these oscillators are not absolutely stable. as long as the variations 417 september 02, 2007 preliminary lm3s8962 microcontroller remain inside a specific oscillator's tolerance range, the can nodes are able to compensate for the dif ferent bit rates by periodically resynchronizing to the bit stream. according to the can specification, the bit time is divided into four segments (see figure 16-2 on page 418 ): the synchronization segment, the propagation t ime segment, the phase buf fer segment 1, and the phase buf fer segment 2. each segment consists of a specific, programmable number of time quanta (see t able 16-3 on page 418 ). the length of the time quantum ( tq ), which is the basic time unit of the bit time, is defined by the can controller's system clock ( fsys ) and the baud rate prescaler ( brp ): tq = brp / fsys the can module's system clock fsys is the frequency of its can module clock ( can_clk ) input. the synchronization segment sync_seg is that part of the bit time where edges of the can bus level are expected to occur; the distance between an edge that occurs outside of sync_seg and the sync_seg is called the phase error of that edge. the propagation t ime segment prop_seg is intended to compensate for the physical delay times within the can network. the phase buf fer segments phase_seg1 and phase_seg2 surround the sample point. the (re-)synchronization jump width (sjw) defines how far a resynchronization may move the sample point inside the limits defined by the phase buf fer segments to compensate for edge phase errors. a given bit rate may be met by dif ferent bit-time configurations, but for the proper function of the can network, the physical delay times and the oscillator's tolerance range have to be considered. figure 16-2. can bit t ime t able 16-3. can protocol ranges a remark range parameter defines the length of the time quantum t q [1 .. 32] brp fixed length, synchronization of bus input to system clock 1 t q sync_seg compensates for the physical delay times [1 .. 8] t q prop_seg may be lengthened temporarily by synchronization [1 .. 8] t q phase_seg1 may be shortened temporarily by synchronization [1 .. 8] t q phase_seg2 september 02, 2007 418 preliminary controller area network (can) module remark range parameter may not be longer than either phase buf fer segment [1 .. 4] t q sjw a. this table describes the minimum programmable ranges required by the can protocol. the bit timing configuration is programmed in two register bytes in the canbit register . the sum of prop_seg and phase_seg1 (as tseg1 ) is combined with phase_seg2 (as tseg2 ) in one byte, and sjw and brp are combined in the other byte. in these bit timing registers, the four components tseg1 , tseg2 , sjw , and brp have to be programmed to a numerical value that is one less than its functional value; so instead of values in the range of [1..n], values in the range of [0..n-1] are programmed. that way , for example, sjw (functional range of [1..4]) is represented by only two bits. therefore, the length of the bit time is (programmed values): [tseg1 + tseg2 + 3] tq or (functional values): [sync_seg + prop_seg + phase_seg1 + phase_seg2] tq the data in the bit timing registers are the configuration input of the can protocol controller . the baud rate prescalar (configured by brp ) defines the length of the time quantum, the basic time unit of the bit time; the bit t iming logic (configured by tseg1 , tseg2 , and sjw ) defines the number of time quanta in the bit time. the processing of the bit time, the calculation of the position of the sample point, and occasional synchronizations are controlled by the can controller and are evaluated once per time quantum. the can controller translates messages to and from frames. it generates and discards the enclosing fixed format bits, inserts and extracts stuf f bits, calculates and checks the crc code, performs the error management, and decides which type of synchronization is to be used. it is evaluated at the sample point and processes the sampled bus input bit. the time after the sample point that is needed to calculate the next bit to be sent (that is, the data bit, crc bit, stuf f bit, error flag, or idle) is called the information processing t ime (ipt). the ipt is application-specific but may not be longer than 2 tq; the can's ipt is 0 tq. its length is the lower limit of the programmed length of phase_seg2 . in case of synchronization, phase_seg2 may be shortened to a value less than ipt , which does not af fect bus timing. 16.4.15 calculating the bit t iming parameters usually , the calculation of the bit timing configuration starts with a desired bit rate or bit time. the resulting bit time (1/bit rate) must be an integer multiple of the system clock period. the bit time may consist of 4 to 25 time quanta. several combinations may lead to the desired bit time, allowing iterations of the following steps. the first part of the bit time to be defined is the prop_seg . its length depends on the delay times measured in the system. a maximum bus length as well as a maximum node delay has to be defined for expandable can bus systems. the resulting time for prop_seg is converted into time quanta (rounded up to the nearest integer multiple of tq ). the sync_seg is 1 tq long (fixed), which leaves (bit time - prop_seg - 1) tq for the two phase buf fer segments. if the number of remaining tq is even, the phase buf fer segments have the same length, that is, phase_seg2 = phase_seg1 , else phase_seg2 = phase_seg1 + 1. 419 september 02, 2007 preliminary lm3s8962 microcontroller the minimum nominal length of phase_seg2 has to be regarded as well. phase_seg2 may not be shorter than the can controller's information processing t ime, which is, depending on the actual implementation, in the range of [0..2] tq. the length of the synchronization jump width is set to its maximum value, which is the minimum of 4 and phase_seg1 . the oscillator tolerance range necessary for the resulting configuration is calculated by the formula given below: (1 -df) x fnom <= fosc <= (1+ df) x fnom where: df = maximum tolerance of oscillator frequency fosc = actual oscillator frequency fnom = nominal oscillator frequency maximum frequency tolerance must take into account the following formulas: df <= (phase_seg1,phase_seg2)min/ 2 x (13 x tbit - phase_seg2) dfmax = 2 x df x fnom where: phase_seg1 and phase_seg2 are from t able 16-3 on page 418 tbit = bit t ime dfmax = maximum dif ference between two oscillators if more than one configuration is possible, that configuration allowing the highest oscillator tolerance range should be chosen. can nodes with dif ferent system clocks require dif ferent configurations to come to the same bit rate. the calculation of the propagation time in the can network, based on the nodes with the longest delay times, is done once for the whole network. the can system's oscillator tolerance range is limited by the node with the lowest tolerance range. the calculation may show that bus length or bit rate have to be decreased or that the oscillator frequencies' stability has to be increased in order to find a protocol-compliant configuration of the can bit timing. the resulting configuration is written into the can bit t iming (canbit) register : (phase_seg2-1)&(phase_seg1+prop_seg-1)&(synchronizationjumpwidth-1)&(prescaler-1) 16.4.15.1 example for bit t iming at high baud rate in this example, the frequency of can_clk is 10 mhz, brp is 0, and the bit rate is 1 mbps. tq 100 ns = tcan_clk delay of bus driver 50 ns delay of receiver circuit 30 ns delay of bus line (40m) 220 ns september 02, 2007 420 preliminary controller area network (can) module tprop 600 ns = 6 tq tsjw 100 ns = 1 tq ttseg1 700 ns = tprop + tsjw ttseg2 200 ns = information processing time + 1 tq tsync-seg 100 ns = 1 tq bit time 1000 ns = tsync-seg + ttseg1 + ttseg2 tolerance for can_clk 0.39 % = min(pb1,pb2)/ 2 (13 x bit time - pb2) = 0.1us/ 2 x (13x 1us - 2us) in the above example, the concatenated bit time parameters are (2-1)3&(7-1)4&(1-1)2&(1-1)6, and canbit is programmed to 0x1600. 16.4.15.2 example for bit t iming at low baud rate in this example, the frequency of can_clk is 2 mhz, brp is 1, and the bit rate is 100 kbps. tq 1 ms = 2 tcan_clk delay of bus driver 200 ns delay of receiver circuit 80 ns delay of bus line (40m) 220 ns tprop 1 ms = 1 tq tsjw 4 ms = 4 tq ttseg1 5 ms = tprop + tsjw ttseg2 4 ms = information processing time + 3 tq tsync-seg 1 ms = 1 tq bit time 10 ms = tsync-seg + ttseg1 + ttseg2 tolerance for can_clk 1.58 % = min(pb1,pb2)/ 2 x (13 x bit time - pb2) = 4us/ 2 x (13 x 10us - 4us) in this example, the concatenated bit time parameters are (4-1)3&(5-1)4&(4-1)2&(2-1)6, and canbit is programmed to 0x34c1. 16.5 controller area network register map t able 16-4 on page 421 lists the registers. all addresses given are relative to the can base address of: can0: 0x4004.0000 all accesses are on word (32-bit) boundaries. t able 16-4. can register map see page description reset t ype name offset 424 can control 0x0000.0001 r/w canctl 0x000 426 can status 0x0000.0000 r/w cansts 0x004 429 can error counter 0x0000.0000 ro canerr 0x008 430 can bit t iming 0x0000.2301 r/w canbit 0x00c 432 can interrupt 0x0000.0000 ro canint 0x010 421 september 02, 2007 preliminary lm3s8962 microcontroller see page description reset t ype name offset 433 can t est 0x0000.0000 r/w cantst 0x014 435 can baud rate prescalar extension 0x0000.0000 r/w canbrpe 0x018 436 can if1 command request 0x0000.0001 r/w canif1crq 0x020 437 can if1 command mask 0x0000.0000 r/w canif1cmsk 0x024 440 can if1 mask 1 0x0000.ffff r/w canif1msk1 0x028 441 can if1 mask 2 0x0000.ffff r/w canif1msk2 0x02c 442 can if1 arbitration 1 0x0000.0000 r/w canif1arb1 0x030 443 can if1 arbitration 2 0x0000.0000 r/w canif1arb2 0x034 444 can if1 message control 0x0000.0000 r/w canif1mctl 0x038 446 can if1 data a1 0x0000.0000 r/w canif1da1 0x03c 446 can if1 data a2 0x0000.0000 r/w canif1da2 0x040 446 can if1 data b1 0x0000.0000 r/w canif1db1 0x044 446 can if1 data b2 0x0000.0000 r/w canif1db2 0x048 436 can if2 command request 0x0000.0001 r/w canif2crq 0x080 437 can if2 command mask 0x0000.0000 r/w canif2cmsk 0x084 440 can if2 mask 1 0x0000.ffff r/w canif2msk1 0x088 441 can if2 mask 2 0x0000.ffff r/w canif2msk2 0x08c 442 can if2 arbitration 1 0x0000.0000 r/w canif2arb1 0x090 443 can if2 arbitration 2 0x0000.0000 r/w canif2arb2 0x094 444 can if2 message control 0x0000.0000 r/w canif2mctl 0x098 446 can if2 data a1 0x0000.0000 r/w canif2da1 0x09c 446 can if2 data a2 0x0000.0000 r/w canif2da2 0x0a0 446 can if2 data b1 0x0000.0000 r/w canif2db1 0x0a4 446 can if2 data b2 0x0000.0000 r/w canif2db2 0x0a8 447 can t ransmission request 1 0x0000.0000 ro cantxrq1 0x100 447 can t ransmission request 2 0x0000.0000 ro cantxrq2 0x104 448 can new data 1 0x0000.0000 ro cannwda1 0x120 448 can new data 2 0x0000.0000 ro cannwda2 0x124 449 can message 1 interrupt pending 0x0000.0000 ro canmsg1int 0x140 449 can message 2 interrupt pending 0x0000.0000 ro canmsg2int 0x144 450 can message 1 v alid 0x0000.0000 ro canmsg1v al 0x160 450 can message 2 v alid 0x0000.0000 ro canmsg2v al 0x164 september 02, 2007 422 preliminary controller area network (can) module 16.6 register descriptions the remainder of this section lists and describes the can registers, in numerical order by address of fset. there are two sets of interface registers which are used to access the message objects in the message ram: canif1x and canif2x . the function of the two sets are identical and are used to queue transactions. 423 september 02, 2007 preliminary lm3s8962 microcontroller register 1: can control (canctl), offset 0x000 this control register initializes the module and enables test mode and interrupts. the bus-of f recovery sequence (see can specification rev . 2.0) cannot be shortened by setting or resetting init . if the device goes bus-of f, it sets init , stopping all bus activities. once init has been cleared by the cpu, the device then waits for 129 occurrences of bus idle (129 * 1 1 consecutive high bits) before resuming normal operations. at the end of the bus-of f recovery sequence, the error management counters are reset. during the waiting time after init is reset, each time a sequence of 1 1 high bits has been monitored, a bit0error code is written to the cansts status register , enabling the cpu to readily check whether the can bus is stuck at dominant or continuously disturbed and to monitor the proceeding of the bus-of f recovery sequence. can control (canctl) can0 base: 0x4004.0000 of fset 0x000 t ype r/w , reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 init ie sie eie reserved dar cce t est reserved r/w r/w r/w r/w ro r/w r/w r/w ro ro ro ro ro ro ro ro t ype 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:8 t est mode enable 0: normal operation 1: t est mode 0 r/w t est 7 configuration change enable 0: do not allow write access to the canbit register . 1: allow write access to the canbit register if the init bit is 1. 0 r/w cce 6 disable automatic retransmission 0: auto retransmission of disturbed messages is enabled. 1: auto retransmission is disabled. 0 r/w dar 5 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 4 error interrupt enable 0: disabled. no error status interrupt is generated. 1: enabled. a change in the boff or ewarn bits in the cansts register generates an interrupt. 0 r/w eie 3 september 02, 2007 424 preliminary controller area network (can) module description reset t ype name bit/field status change interrupt enable 0: disabled. no status change interrupt is generated. 1: enabled. an interrupt is generated when a message has successfully been transmitted or received, or a can bus error has been detected. a change in the txok or rxok bits in the cansts register generates an interrupt. 0 r/w sie 2 can interrupt enable 0: interrupt disabled. 1: interrupt enabled. 0 r/w ie 1 initialization 0: normal operation. 1: initialization started. 1 r/w init 0 425 september 02, 2007 preliminary lm3s8962 microcontroller register 2: can status (cansts), offset 0x004 the status register contains information for interrupt servicing such as bus-of f, error count threshold, and error types. the lec field holds the code that indicates the type of the last error to occur on the can bus. this field is cleared to 0 when a message has been transferred (reception or transmission) without error . the unused error code 7 may be written by the cpu to check for updates. an error interrupt is generated by the boff and ewarn bits and a status change interrupt is generated by the rxok , txok , and lec bits, assuming that the corresponding enable bits in the can control (canctl) register are set. a change of the epass bit or a write to the rxok , txok , or lec bits does not generate an interrupt. reading the can status (cansts) register clears the can interrupt (canint) register , if it is pending. can status (cansts) can0 base: 0x4004.0000 of fset 0x004 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 lec txok rxok epass ew arn bof f reserved r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:8 bus-of f status 0: module is not in bus-of f state. 1: module is in bus-of f state. 0 ro bof f 7 w arning status 0: both error counters are below the error warning limit of 96. 1: at least one of the error counters has reached the error warning limit of 96. 0 ro ew arn 6 error passive 0: the can module is in the error active state, that is, the receive or transmit error count is less than or equal to 127. 1: the can module is in the error passive state, that is, the receive or transmit error count is greater than 127. 0 ro epass 5 september 02, 2007 426 preliminary controller area network (can) module description reset t ype name bit/field received a message successfully 0: since this bit was last reset to 0, no message has been successfully received. 1: since this bit was last reset to 0, a message has been successfully received, independent of the result of the acceptance filtering. this bit is never reset by the can module. 0 r/w rxok 4 t ransmitted a message successfully 0: since this bit was last reset to 0, no message has been successfully transmitted. 1: since this bit was last reset to 0, a message has been successfully transmitted error-free and acknowledged by at least one other node. this bit is never reset by the can module. 0 r/w txok 3 427 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field last error code this is the type of the last error to occur on the can bus. definition v alue no error 0x0 stuf f error more than 5 equal bits in a sequence have occurred in a part of a received message where this is not allowed. 0x1 form error a fixed format part of the received frame has the wrong format. 0x2 ack error the message transmitted was not acknowledged by another node. 0x3 bit 1 error when a message is transmitted, the can controller monitors the data lines to detect any conflicts. when the arbitration field is transmitted, data conflicts are a part of the arbitration protocol. when other frame fields are transmitted, data conflicts are considered errors. a bit 1 error indicates that the device wanted to send a high level (logical 1) but the monitored bus value was low (logical 0). 0x4 bit 0 error a bit 0 error indicates that the device wanted to send a low level (logical 0) but the monitored bus value was high (logical 1). during bus-of f recovery , this status is set each time a sequence of 1 1 high bits has been monitored. this enables the cpu to monitor the proceeding of the bus-of f recovery sequence without any disturbances to the bus. 0x5 crc error the crc checksum was incorrect in the received message, indicating that the calculated value received did not match the calculated crc of the data. 0x6 unused when the lec bit shows this value, no can bus event was detected since the cpu wrote this value to lec . 0x7 0x0 r/w lec 2:0 september 02, 2007 428 preliminary controller area network (can) module register 3: can error counter (canerr), offset 0x008 this register contains the error counter values, which can be used to analyze the cause of an error . can error counter (canerr) can0 base: 0x4004.0000 of fset 0x008 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 tec rec rp ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 received error passive 0: the receive error counter is below the error passive level (127 or less). 1: the receive error counter has reached the error passive level (128 or greater). 0 ro rp 15 receive error counter state of the receiver error counter (0 to 127). 0x0 ro rec 14:8 t ransmit error counter state of the transmit error counter (0 to 255). 0x0 ro tec 7:0 429 september 02, 2007 preliminary lm3s8962 microcontroller register 4: can bit t iming (canbit), offset 0x00c this register is used to program the bit width and bit quantum. v alues are to be programmed to the system clock frequency . this register is write-enabled by the cce and init bits in the canctl register . with a can module clock ( can_clk ) of 8 mhz, the register reset value of 0x230 configures the can for a bit rate of 500 kbps. can bit t iming (canbit) can0 base: 0x4004.0000 of fset 0x00c t ype r/w , reset 0x0000.2301 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 brp sjw tseg1 tseg2 reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro t ype 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:15 t ime segment after sample point 0x00-0x07: the actual interpretation by the hardware of this value is such that one more than the value programmed here is used. so, for example, a reset value of 0x2 defines that there is 3(2+1) bit time quanta defined for phase_seg2 (see figure 16-2 on page 418 ). the bit time quanta is defined by brp . 0x2 r/w tseg2 14:12 t ime segment before sample point 0x00-0x0f: the actual interpretation by the hardware of this value is such that one more than the value programmed here is used. so, for example, the reset value of 0x3 defines that there is 4(3+1) bit time quanta defined for phase_seg1 (see figure 16-2 on page 418 ). the bit time quanta is define by brp . 0x3 r/w tseg1 1 1:8 (re)synchronization jump width 0x00-0x03: the actual interpretation by the hardware of this value is such that one more than the value programmed here is used. during the start of frame (sof), if the can controller detects a phase error (misalignment), it can adjust the length of tseg2 or tseg1 by the value in sjw . so the reset value of 0 adjusts the length by 1 bit time quanta. 0x0 r/w sjw 7:6 september 02, 2007 430 preliminary controller area network (can) module description reset t ype name bit/field baud rate prescalar 0x00-0x03f: the value by which the oscillator frequency is divided for generating the bit time quanta. the bit time is built up from a multiple of this quantum. the actual interpretation by the hardware of this value is such that one more than the value programmed here is used. brp defines the number of can clock periods that make up 1 bit time quanta, so the reset value is 2 bit time quanta (1+1). the brpre register can be used to further divide the bit time. 0x1 r/w brp 5:0 431 september 02, 2007 preliminary lm3s8962 microcontroller register 5: can interrupt (canint), offset 0x010 this register indicates the source of the interrupt. if several interrupts are pending, the can interrupt (canint) register points to the pending interrupt with the highest priority , disregarding their chronological order . an interrupt remains pending until the cpu has cleared it. if the intid bit is not 0x0000 (the default) and the ie bit in the canctl register is set, the interrupt is active. the interrupt line remains active until the intid bit is set back to 0x0000 when the cause of all interrupts are reset or until ie is reset. can interrupt (canint) can0 base: 0x4004.0000 of fset 0x010 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 intid ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 interrupt identifier the number in this field indicates the source of the interrupt. definition v alue no interrupt pending 0x0000 number of the message object that caused the interrupt 0x0001-0x0020 unused 0x0021-0x7fff status interrupt 0x8000 unused 0x8001-0xffff 0x0000 ro intid 15:0 september 02, 2007 432 preliminary controller area network (can) module register 6: can t est (cantst), offset 0x014 this is the test mode register for self-test and external pin access. it is write-enabled by the test bit in the canctl register . dif ferent test functions may be combined but when the tx bit is not equal to 0x0, it disturbs message transmits. can t est (cantst) can0 base: 0x4004.0000 of fset 0x014 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved basic silent lback tx rx reserved ro ro r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:8 receive observation displays the value on the cannrx pin. 0 ro rx 7 t ransmit control overrides control of the canntx pin. description v alue can_tx is controlled by the can module (default) 00 sample point signal driven on the can_tx pin 01 can_tx drives a low value 10 can_tx drives a high value 1 1 0x0 r/w tx 6:5 loopback mode 0: disabled. 1: enabled. 0 r/w lback 4 silent mode do not transmit data; monitor the bus. also known as bus monitor mode. 0: disabled. 1: enabled. 0 r/w silent 3 basic mode 0: disabled. 1: use canif1 registers as transmit buf fer , and use canif2 registers as receive buf fer . 0 r/w basic 2 433 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 1:0 september 02, 2007 434 preliminary controller area network (can) module register 7: can baud rate prescalar extension (canbrpe), offset 0x018 this register is used to further divide the bit time set with the brp bit in the canbit register . it is write-enabled with the cce bit in the canctl register . can baud rate prescalar extension (canbrpe) can0 base: 0x4004.0000 of fset 0x018 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 brpe reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:4 baud rate prescalar extension. 0x00-0x0f: extend the brp bit to values up to 1023. the actual interpretation by the hardware is one more than the value programmed by brpe (msbs) and brp (lsbs) are used. 0x0 r/w brpe 3:0 435 september 02, 2007 preliminary lm3s8962 microcontroller register 8: can if1 command request (canif1crq), offset 0x020 register 9: can if2 command request (canif2crq), offset 0x080 this register is used to start a transfer when its mnum bit field is updated. its busy bit indicates that the information is transferring from the can interface registers to the internal message ram. a message transfer is started as soon as there is a write of the message object number with the mnum bit. with this write operation, the busy bit is automatically set to 1 to indicate that a transfer is in progress. after a wait time of 3 to 6 can_clk periods, the transfer between the interface register and the message ram completes, which then sets the busy bit back to 0. can if1 command request (canif1crq) can0 base: 0x4004.0000 of fset 0x020 t ype ro, reset 0x0000.0001 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 mnum reserved busy r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 busy flag 0: reset when read/write action has finished. 1: set when a write occurs to the message number in this register . 0x0 ro busy 15 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 14:6 message number selects one of the 32 message objects in the message ram for data transfer . the message objects are numbered from 1 to 32. description v alue 0 is not a valid message number; it is interpreted as 0x20, or object 32. 0x00 indicates specified message object 1 to 32. 0x01-0x20 not a valid message number; values are shifted and it is interpreted as 0x01-0x1f . 0x21-0x3f 0x01 r/w mnum 5:0 september 02, 2007 436 preliminary controller area network (can) module register 10: can if1 command mask (canif1cmsk), offset 0x024 register 1 1: can if2 command mask (canif2cmsk), offset 0x084 the command mask registers specify the transfer direction and select which buf fer registers are the source or target of the data transfer . can if1 command mask (canif1cmsk) can0 base: 0x4004.0000 of fset 0x024 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 datab dataa txrqst/newdat clrintpnd control arb mask wrnrd reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:8 w rite, not read 0: read. t ransfer the message object address specified by the can command request (canifncrq) register to the can message buf fer registers ( canifnmsk1 , canifnmsk2 , canifnarb1 , canifnarb2 , canifnctl , canifnda1 , canifnda2 , canifndb1 , and canifndb2 ). 1: w rite. t ransfer data from the message buf fer registers to the message object address specified by the canifncrq register . 0 r/w wrnrd 7 access mask bits when wrnrd =1 (writes): 0: mask bits unchanged. 1: t ransfer idmask + dir + mxtd to message object. when wrnrd =0 (reads): 0: mask bits unchanged. 1: t ransfer idmask + dir + mxtd of the message object into the interface registers. 0x0 r/w mask 6 access arbitration bits when wrnrd =1 (writes): 0: arbitration bits unchanged. 1: t ransfer id + dir + xtd + msgval to message object. when wrnrd =0 (reads): 0: arbitration bits unchanged. 1: t ransfer id + dir + xtd + msgval to message buf fer register . 0x0 r/w arb 5 437 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field access control bits when wrnrd =1 (writes): 0: control bits unchanged. 1: t ransfer control bits to message object. when wrnrd =0 (reads): 0: control bits unchanged. 1: t ransfer control bits to message buf fer register . 0x0 r/w control 4 clear interrupt pending bit note: this bit is not used when in write ( wrnrd =1). 0: intpnd bit in canifnmctl register remains unchanged. 1: clear intpnd bit in the canifnmctl register in the message object. 0x0 r/w clrintpnd 3 access t ransmission request or new data when wrnrd =1 (writes): access t ransmission request bit 0: txrqst bit unchanged. 1: set txrqst bit note: if a transmission is requested by programming this txrqst bit, the parallel txrqst in the canifnmctl register is ignored. when wrnrd =0 (reads): access new data bit 0: newdat bit unchanged. 1: clear newdat bit in the message object. note: a read access to a message object can be combined with the reset of the control bits intpdn and newdat . the values of these bits that are transferred to the canifnmctl register always reflect the status before resetting these bits. 0x0 r/w txrqst/newdat 2 access data byte 0 to 3 when wrnrd =1 (writes): 0: data bytes 0-3 are unchanged. 1: t ransfer data bytes 0-3 ( canifnda1 and canifnda2 ) to message object. when wrnrd =0 (reads): 0: data bytes 0-3 are unchanged. 1: t ransfer data bytes 0-3 in message object to canifnda1 and canifnda2 . 0x0 r/w dataa 1 september 02, 2007 438 preliminary controller area network (can) module description reset t ype name bit/field access data byte 4 to 7 when wrnrd =1 (writes): 0: data bytes 4-7 unchanged. 1: t ransfer data bytes 4-7 ( canifndb1 and canifndb2 ) to message object. when wrnrd =0 (reads): 0: data bytes 4-7 unchanged. 1: t ransfer data bytes 4-7 in message object to canifndb1 and canifndb2 . 0x0 r/w datab 0 439 september 02, 2007 preliminary lm3s8962 microcontroller register 12: can if1 mask 1 (canif1msk1), offset 0x028 register 13: can if2 mask 1 (canif2msk1), offset 0x088 the mask information provided in this register accompanies the data ( canifndan ), arbitration information ( canifnarbn ), and control information ( canifnmctl ) to the message object in the message ram. the mask is used with the id bit in the canifnarbn register for acceptance filtering. additional mask information is contained in the canifnmsk2 register . can if1 mask 1 (canif1msk1) can0 base: 0x4004.0000 of fset 0x028 t ype ro, reset 0x0000.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 msk r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 identifier mask 0: the corresponding identifier bit (id) in the message object cannot inhibit the match in acceptance filtering. 1: the corresponding identifier bit (id) is used for acceptance filtering. 0xff r/w msk 15:0 september 02, 2007 440 preliminary controller area network (can) module register 14: can if1 mask 2 (canif1msk2), offset 0x02c register 15: can if2 mask 2 (canif2msk2), offset 0x08c this register holds extended mask information that accompanies the canifnmsk1 register . can if1 mask 2 (canif1msk2) can0 base: 0x4004.0000 of fset 0x02c t ype ro, reset 0x0000.ffff 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 msk reserved mdir mxtd r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro r/w r/w t ype 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 mask extended identifier 0: the extended identifier bit ( xtd in the canifnarb2 register) has no ef fect on the acceptance filtering. 1: the extended identifier bit xtd is used for acceptance filtering. 0x1 r/w mxtd 15 mask message direction 0: the message direction bit ( dir in the canifnarb2 register) has no ef fect for acceptance filtering. 1: the message direction bit dir is used for acceptance filtering. 0x1 r/w mdir 14 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x1 ro reserved 13 identifier mask 0: the corresponding identifier bit (id) in the message object cannot inhibit the match in acceptance filtering. 1: the corresponding identifier bit (id) is used for acceptance filtering. 0xff r/w msk 12:0 441 september 02, 2007 preliminary lm3s8962 microcontroller register 16: can if1 arbitration 1 (canif1arb1), offset 0x030 register 17: can if2 arbitration 1 (canif2arb1), offset 0x090 these registers hold the identifiers for acceptance filtering. can if1 arbitration 1 (canif1arb1) can0 base: 0x4004.0000 of fset 0x030 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 id r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 message identifier this bit field is used with the id field in the canifnarb2 register to create the message identifier . id[28:0] is the extended frame and id[28:18] is the standard frame. 0x00 r/w id 15:0 september 02, 2007 442 preliminary controller area network (can) module register 18: can if1 arbitration 2 (canif1arb2), offset 0x034 register 19: can if2 arbitration 2 (canif2arb2), offset 0x094 these registers hold information for acceptance filtering. can if1 arbitration 2 (canif1arb2) can0 base: 0x4004.0000 of fset 0x034 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 id dir xtd msgv al r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 message v alid 0: the message object is ignored by the message handler . 1: the message object is configured and will be considered by the message handler within the can controller . all unused message objects should have this bit cleared during initialization and before clearing the init bit in the canctl register . the msgval bit must also be cleared before any of the following bits are modified or if the message object is no longer required: the id bit fields in the canifnarbn registers, the xtd and dir bits in the canifnarb2 register , or the dlc bits in the canifnmctl register . 0x0 r/w msgv al 15 extended identifier 0: the 1 1-bit standard identifier will be used for this message object. 1: the 29-bit extended identifier will be used for this message object. 0x0 r/w xtd 14 message direction 0: receive. on txrqst , a remote frame with the identifier of this message object is transmitted. on reception of a data frame with matching identifier , that message is stored in this message object. 1: t ransmit. on txrqst , the respective message object is transmitted as a data frame. on reception of a remote frame with matching identifier , txrqst bit of this message object is set (if rmten =1). 0x0 r/w dir 13 message identifier used with the id bit in the canifnarb1 register to create the message identifier . id[28:0] is the extended frame and id[28:18] is the standard frame. 0x0 r/w id 12:0 443 september 02, 2007 preliminary lm3s8962 microcontroller register 20: can if1 message control (canif1mctl), offset 0x038 register 21: can if2 message control (canif2mctl), offset 0x098 this register holds the control information associated with the message object to be sent to the message ram. can if1 message control (canif1mctl) can0 base: 0x4004.0000 of fset 0x038 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 dlc reserved eob txrqst rmten rxie txie umask intpnd msglst newdat r/w r/w r/w r/w ro ro ro r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 new data 0: no new data has been written into the data portion of this message object by the message handler since the last time this flag was cleared by the cpu. 1: the message handler or the cpu has written new data into the data portion of this message object. 0x0 r/w newdat 15 message lost 0 : no message was lost since the last time this bit was reset by the cpu. 1: the message handler stored a new message into this object when newdat was set; the cpu has lost a message. this bit is only valid for message objects with the dir bit in the canifnarb2 register set to 0 (receive). 0x0 r/w msglst 14 interrupt pending 0: this message object is not the source of an interrupt. 1: this message object is the source of an interrupt. the interrupt identifier in the can interrupt (canint) register will point to this message object if there is not another interrupt source with a higher priority . 0x0 r/w intpnd 13 use acceptance mask 0: mask ignored. 1: use mask ( msk , mxtd , and mdir ) for acceptance filtering. 0x0 r/w umask 12 september 02, 2007 444 preliminary controller area network (can) module description reset t ype name bit/field t ransmit interrupt enable 0: the intpnd bit in the canifnmctl register is unchanged after a successful transmission of a frame. 1: the intpnd bit in the canifnmctl register is set after a successful transmission of a frame. 0x0 r/w txie 1 1 receive interrupt enable 0: the intpnd bit in the canifnmctl register is unchanged after a successful reception of a frame. 1: the intpnd bit in the canifnmctl register is set after a successful reception of a frame. 0x0 r/w rxie 10 remote enable 0: at the reception of a remote frame, the txrqst bit in the canifnmctl register is left unchanged. 1: at the reception of a remote frame, the txrqst bit in the canifnmctl register is set. 0x0 r/w rmten 9 t ransmit request 0: this message object is not waiting for transmission. 1: the transmission of this message object is requested and is not yet done. 0x0 r/w txrqst 8 end of buf fer 0: message object belongs to a fifo buf fer and is not the last message object of that fifo buf fer . 1: single message object or last message object of a fifo buf fer . this bit is used to concatenate two or more message objects (up to 32) to build a fifo buf fer . for a single message object (thus not belonging to a fifo buf fer), this bit must be set to 1. 0x0 r/w eob 7 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 6:4 data length code description v alue specifies the number of bytes in the data frame. 0x0-0x8 defaults to a data frame with 8 bytes. 0x9-0xf the dlc bit in the canifnmctl register of a message object must be defined the same as in all the corresponding objects with the same identifier at other nodes. when the message handler stores a data frame, it writes dlc to the value given by the received message. 0x0 r/w dlc 3:0 445 september 02, 2007 preliminary lm3s8962 microcontroller register 22: can if1 data a1 (canif1da1), offset 0x03c register 23: can if1 data a2 (canif1da2), offset 0x040 register 24: can if1 data b1 (canif1db1), offset 0x044 register 25: can if1 data b2 (canif1db2), offset 0x048 register 26: can if2 data a1 (canif2da1), offset 0x09c register 27: can if2 data a2 (canif2da2), offset 0x0a0 register 28: can if2 data b1 (canif2db1), offset 0x0a4 register 29: can if2 data b2 (canif2db2), offset 0x0a8 these registers contain the data to be sent or that has been received. in a can data frame, data byte 0 is the first byte to be transmitted or received and data byte 7 is the last byte to be transmitted or received. in can's serial bit stream, the msb of each byte is transmitted first. can if1 data a1 (canif1da1) can0 base: 0x4004.0000 of fset 0x03c t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 data r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 data the canifnda1 registers contain data bytes 1 and 0; canifnda2 data bytes 3 and 2; canifndb1 data bytes 5 and 4; and canifndb2 data bytes 7 and 6. 0x00 r/w data 15:0 september 02, 2007 446 preliminary controller area network (can) module register 30: can t ransmission request 1 (cantxrq1), offset 0x100 register 31: can t ransmission request 2 (cantxrq2), offset 0x104 the cantxrq1 and cantxrq2 registers hold the txrqst bits of the 32 message objects. by reading out these bits, the cpu can check which message object has a transmission request pending. the txrqst bit of a specific message object can be changed by three sources: (1) the cpu via the can ifn message control (canifnmctl) register , (2) the message handler state machine after the reception of a remote frame, or (3) the message handler state machine after a successful transmission. the cantxrq1 register contains the txrqst bit of the first 16 message objects in the message ram; the cantxrq2 register contains the txrqst bit of the second 16 message objects. can t ransmission request 1 (cantxrq1) can0 base: 0x4004.0000 of fset 0x100 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 txrqst ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 t ransmission request bits (of all message objects) 0: the message object is not waiting for transmission. 1: the transmission of the message object is requested and is not yet done. 0x00 ro txrqst 15:0 447 september 02, 2007 preliminary lm3s8962 microcontroller register 32: can new data 1 (cannwda1), offset 0x120 register 33: can new data 2 (cannwda2), offset 0x124 the cannwda1 and cannwda2 registers hold the newdat bits of the 32 message objects. by reading these bits, the cpu can check which message object has its data portion updated. the newdat bit of a specific message object can be changed by three sources: (1) the cpu via the can ifn message control (canifnmctl) register , (2) the message handler state machine after the reception of a data frame, or (3) the message handler state machine after a successful transmission. the cannwda1 register contains the newdat bit of the first 16 message objects in the message ram; the cannwda2 register contains the newdat bit of the second 16 message objects. can new data 1 (cannwda1) can0 base: 0x4004.0000 of fset 0x120 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 newdat ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 new data bits (of all message objects) 0: no new data has been written into the data portion of this message object by the message handler since the last time this flag was cleared by the cpu. 1: the message handler or the cpu has written new data into the data portion of this message object. 0x00 ro newdat 15:0 september 02, 2007 448 preliminary controller area network (can) module register 34: can message 1 interrupt pending (canmsg1int), offset 0x140 register 35: can message 2 interrupt pending (canmsg2int), offset 0x144 the canmsg1int and canmsg2int registers hold the intpnd bits of the 32 message objects. by reading these bits, the cpu can check which message object has an interrupt pending. the intpnd bit of a specific message object can be changed through two sources: (1) the cpu via the can ifn message control (canifnmctl) register , or (2) the message handler state machine after the reception or transmission of a frame. this field is also encoded in the can interrupt (canint) register . the canmsg1int register contains the intpnd bit of the first 16 message objects in the message ram; the canmsg2int register contains the intpnd bit of the second 16 message objects. can message 1 interrupt pending (canmsg1int) can0 base: 0x4004.0000 of fset 0x140 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 intpnd ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 interrupt pending bits (of all message objects) 0: this message object is not the source of an interrupt. 1: this message object is the source of an interrupt. 0x00 ro intpnd 15:0 449 september 02, 2007 preliminary lm3s8962 microcontroller register 36: can message 1 v alid (canmsg1v al), offset 0x160 register 37: can message 2 v alid (canmsg2v al), offset 0x164 the canmsg1v al and canmsg2v al registers hold the msgval bits of the 32 message objects. by reading these bits, the cpu can check which message object is valid. the message value of a specific message object can be changed with the can ifn message control (canifnmctl) register . the canmsg1v al register contains the msgval bit of the first 16 message objects in the message ram; the canmsg2v al register contains the msgval bit of the second 16 message objects in the message ram. can message 1 v alid (canmsg1v al) can0 base: 0x4004.0000 of fset 0x160 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 msgv al ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0000 ro reserved 31:16 message v alid bits (of all message objects) 0: this message object is not configured and is ignored by the message handler . 1: this message object is configured and should be considered by the message handler . 0x00 ro msgv al 15:0 september 02, 2007 450 preliminary controller area network (can) module 17 ethernet controller the stellaris ? ethernet controller consists of a fully integrated media access controller (mac) and network physical (phy) interface device. the ethernet controller conforms to ieee 802.3 specifications and fully supports 10base-t and 100base-tx standards. the ethernet controller module has the following features: conforms to the ieee 802.3-2002 specification C 10base-t/100base-tx ieee-802.3 compliant. requires only a dual 1:1 isolation transformer interface to the line C 10base-t/100base-tx endec, 100base-tx scrambler/descrambler C full-featured auto-negotiation multiple operational modes C full- and half-duplex 100 mbps C full- and half-duplex 10 mbps C power-saving and power-down modes highly configurable C programmable mac address C led activity selection C promiscuous mode support C crc error-rejection control C user-configurable interrupts physical media manipulation C automatic mdi/mdi-x cross-over correction C register-programmable transmit amplitude C automatic polarity correction and 10base-t signal reception 451 september 02, 2007 preliminary lm3s8962 microcontroller 17.1 block diagram figure 17-1. ethernet controller block diagram 17.2 functional description as shown in figure 17-2 on page 452 , the ethernet controller is functionally divided into two layers or modules: the media access controller (mac) layer and the network physical (phy) layer . these correspond to the osi model layers 2 and 1. the primary interface to the ethernet controller is a simple bus interface to the mac layer . the mac layer provides transmit and receive processing for ethernet frames. the mac layer also provides the interface to the phy module via an internal media independent interface (mii). figure 17-2. ethernet controller 17.2.1 internal mii operation for the mii management interface to function properly , the mdio signal must be connected through a 10k ? pull-up resistor to the +3.3 v supply . failure to connect this pull-up resistor will prevent management transactions on this internal mii to function. note that it is possible for data transmission across the mii to still function since the phy layer will auto-negotiate the link parameters by default. september 02, 2007 452 preliminary ethernet controller cortex m3 media access controller mac ( layer 2) physical layer entity phy ( layer 1) magnetics rj45 ethernet controller macisr maciack macimr interrupt control macrcr macnpr receive control mactcr macithr mactrr t ransmit control t ransmit fifo receive fifo maciar0 maciar1 individual address macmdtx macmcr macmdvr macmar macmdrx mii control macdr data access mactsr t imer support txop txon rxip rxin xtlp xtln mdix clock reference t ransmit encoding pulse shaping receive decoding clock recovery auto negotiation carrier sense mr3 mr0 mr1 mr2 mr4 media independent interface management register set mr5 mr18 mr6 mr16 mr17 mr19 mr23 mr24 collision detect system clock interrupt for the mii management interface to function properly , the internal clock must be divided down from the system clock to a frequency no greater than 2.5 mhz. the macmdv register contains the divider used for scaling down the system clock. see page 472 for more details about the use of this register . 17.2.2 phy configuration/operation the physical layer (phy) in the ethernet controller includes integrated endecs, scrambler/descrambler , dual-speed clock recovery , and full-featured auto-negotiation functions. the transmitter includes an on-chip pulse shaper and a low-power line driver . the receiver has an adaptive equalizer and a baseline restoration circuit required for accurate clock and data recovery . the transceiver interfaces to category-5 unshielded twisted pair (cat-5 utp) cabling for 100base-tx applications, and category-3 unshielded twisted pair (cat-3 utp) for 10base-t applications. the ethernet controller is connected to the line media via dual 1:1 isolation transformers. no external filter is required. 17.2.2.1 clock selection the phy has an on-chip crystal oscillator which can also be driven by an external oscillator . in this mode of operation, a 25-mhz crystal should be connected between the xtalpphy and xtalnphy pins. alternatively , an external 25-mhz clock input can be connected to the xtalpphy pin. in this mode of operation, a crystal is not required and the xtalnphy pin must be tied to ground. 17.2.2.2 auto-negotiation the phy supports the auto-negotiation functions of clause 28 of the ieee 802.3 standard for 10/100 mbps operation over copper wiring. this function can be enabled via register settings. the auto-negotiation function defaults to on and the anegen bit in the mr0 register is high after reset. software can disable the auto-negotiation function by writing to the anegen bit. the contents of the mr4 register are sent to the phy s link partner during auto-negotiation via fast-link pulse coding. once auto-negotiation is complete, the dplx and rate bits in the mr18 register reflect the actual speed and duplex that was chosen. if auto-negotiation fails to establish a link for any reason, the anegf bit in the mr18 register reflects this and auto-negotiation restarts from the beginning. w riting a 1 to the raneg bit in the mr0 register also causes auto-negotiation to restart. 17.2.2.3 polarity correction the phy is capable of either automatic or manual polarity reversal for 10base-t and auto-negotiation functions. bits 4 and 5 ( rvspol and apol ) in the mr16 register control this feature. the default is automatic mode, where apol is low and rvspol indicates if the detection circuitry has inverted the input signal. t o enter manual mode, apol should be set high and rvspol then controls the signal polarity . 17.2.2.4 mdi/mdi-x configuration the phy supports the automatic mdi/mdi-x configuration as defined in ieee 802.3-2002 specification . this eliminates the need for cross-over cables when connecting to another device, such as a hub. the algorithm is controlled via settings in the mr24 register . refer to page 495 for additional details about these settings. 17.2.2.5 led indicators the phy supports two led signals that can be used to indicate various states of operation of the ethernet controller . these signals are mapped to the led0 and led1 pins. by default, these pins are configured as gpio signals ( pf3 and pf2 ). for the phy layer to drive these signals, they must be reconfigured to their hardware function. see general-purpose input/outputs (gpios) on page 453 september 02, 2007 preliminary lm3s8962 microcontroller 164 for additional details. the function of these pins is programmable via the phy layer mr23 register . refer to page 494 for additonal details on how to program these led functions. 17.2.3 mac configuration/operation 17.2.3.1 ethernet frame format ethernet data is carried by ethernet frames. the basic frame format is shown in figure 17-3 on page 454 . figure 17-3. ethernet frame the seven fields of the frame are transmitted from left to right. the bits within the frame are transmitted from least to most significant bit. preamble the preamble field is used by the physical layer signaling circuitry to synchronize with the received frame s timing. the preamble is 7 octets long. start frame delimiter (sfd) the sfd field follows the preamble pattern and indicates the start of the frame. its value is 1010.101 1. destination address (da) this field specifies destination addresses for which the frame is intended. the lsb of the da determines whether the address is an individual (0), or group/multicast (1) address. source address (sa) the source address field identifies the station from which the frame was initiated. length/t ype field the meaning of this field depends on its numeric value. the first of two octets is most significant. this field can be interpreted as length or type code. the maximum length of the data field is 1500 octets. if the value of the length/t ype field is less than or equal to 1500 decimal, it indicates the number of mac client data octets. if the value of this field is greater than or equal to 1536 decimal, then it is type interpretation. the meaning of the length/t ype field when the value is between 1500 and 1536 decimal is unspecified by the standard. the mac module assumes type interpretation if the value of the length/t ype field is greater than 1500 decimal. data the data field is a sequence of 0 to 1500 octets. full data transparency is provided so any values can appear in this field. a minimum frame size is required to properly meet the ieee standard. if necessary , the data field is extended by appending extra bits (a pad). the pad field can have a size of 0 to 46 octets. the sum of the data and pad lengths must be a minimum of 46 octets. the mac module automatically inserts pads if required, though it can be disabled by a register september 02, 2007 454 preliminary ethernet controller preamble sfd destination address source address length/ t ype fcs data 7 bytes 6 bytes 6 bytes 2 bytes 1 byte 4 bytes 46 - 1500 bytes write. for the mac module core, data sent/received can be larger than 1500 bytes, and no frame t oo long error is reported. instead, a fifo overrun error is reported when the frame received is too large to fit into the ethernet controller s ram. frame check sequence (fcs) the frame check sequence carries the cyclic redundancy check (crc) value. the value of this field is computed over destination address, source address, length/type, data, and pad fields using the crc-32 algorithm. the mac module computes the fcs value one nibble at a time. for transmitted frames, this field is automatically inserted by the mac layer , unless disabled by the crc bit in the mactctl register . for received frames, this field is automatically checked. if the fcs does not pass, the frame will not be placed in the rx fifo, unless the fcs check is disabled by the badcrc bit in the macrctl register . 17.2.3.2 mac layer fifos for ethernet frame transmission, a 2 kb tx fifo is provided that can be used to store a single frame. while the ieee 802.3 specification limits the size of an ethernet frame's payload section to 1500 bytes, the ethernet controller places no such limit. the full buf fer can be used, for a payload of up to 2032 bytes. for ethernet frame reception, a 2-kb rx fifo is provided that can be used to store multiple frames, up to a maximum of 31 frames. if a frame is received and there is insuf ficient space in the rx fifo, an overflow error will be indicated. for details regarding the tx and rx fifo layout, refer to t able 17-1 on page 455 . please note the following dif ference between tx and rx fifo layout. for the tx fifo, the data length field in the first fifo word refers to the ethernet frame data payload, as shown in the 5th to nth fifo positions. for the rx fifo, the frame length field is the total length of the received ethernet frame, including the fcs and frame length bytes. also note that if fcs generation is disabled with the crc bit in the mactctl register , the last word in the fifo must be the fcs bytes for the frame that has been written to the fifo. also note that if the length of the data payload section is not a multiple of 4, the fcs field will overlap words in the fifo. however , for the rx fifo, the beginning of the next frame will always be on a word boundary . t able 17-1. tx & rx fifo organization rx fifo (read) tx fifo (w rite) w ord bit fields fifo w ord read/w rite sequence frame length lsb data length lsb 7:0 1st frame length msb data length msb 15:8 da oct 1 23:16 da oct 2 31:24 da oct 3 7:0 2nd da oct 4 15:8 da oct 5 23:16 da oct 6 31:24 sa oct 1 7:0 3rd sa oct 2 15:8 sa oct 3 23:16 sa oct 4 31:24 455 september 02, 2007 preliminary lm3s8962 microcontroller rx fifo (read) tx fifo (w rite) w ord bit fields fifo w ord read/w rite sequence sa oct 5 7:0 4th sa oct 6 15:8 len/t ype msb 23:16 len/t ype lsb 31:24 data oct n 7:0 5th to nth data oct n+1 15:8 data oct n+2 23:16 data oct n+3 31:24 fcs 1 fcs 1 (if the crc bit in macctl is 0) 7:0 last fcs 2 fcs 2 (if the crc bit in macctl is 0) 15:8 fcs 3 fcs 3 (if the crc bit in macctl is 0) 23:16 fcs 4 fcs 4 (if the crc bit in macctl is 0) 31:24 17.2.3.3 ethernet t ransmission options the ethernet controller can automatically generate and insert the frame check sequence (fcs) at the end of the transmit frame. this is controlled by the crc bit in the mactctl register . for test purposes, in order to generate a frame with an invalid crc, this feature can be disabled. the ieee 802.3 specification requires that the ethernet frame payload section be a minimum of 46 bytes. the ethernet controller can be configured to automatically pad the data section if the payload data section loaded into the fifo is less than the minimum 46 bytes. this feature is controlled by the paden bit in the mactctl register . at the mac layer , the transmitter can be configured for both full-duplex and half-duplex operation by using the duplex bit in the mactctl register . 17.2.3.4 ethernet reception options using the badcrc bit in the macrctl register , the ethernet controller can be configured to reject incoming ethernet frames with an invalid fcs field. the ethernet receiver can also be configured for promiscuous and multicast modes using the prms and amul fields in the macrctl register . if these modes are not enabled, only ethernet frames with a broadcast address, or frames matching the mac address programmed into the macia0 and macia1 register will be placed into the rx fifo. 17.2.3.5 packet t imestamps using the tsen bit in the macts register , the mac transmit and receive interrupts can be used to trigger edge capture events on general-purpose t imer 3. the transmit interrupt is routed to the ccp (even) input of general-purpose t imer 3, while the receive interrupt is routed to the ccp (odd) input of general-purpose t imer 3. this timer can then be configured in 16-bit edge capture mode and be used with a third 16-bit free-running timer to capture a more accurate timestamp for the transmit or receive packet. this feature can be used with a protocol such as ieee-1588 to provide more accurate timestamps of the synchronization packets, improving the overall accuracy of the protocol. september 02, 2007 456 preliminary ethernet controller 17.2.4 interrupts the ethernet controller can generate an interrupt for one or more of the following conditions: a frame has been received into an empty rx fifo a frame transmission error has occurred a frame has been transmitted successfully a frame has been received with no room in the rx fifo (overrun) a frame has been received with one or more error conditions (for example, fcs failed) an mii management transaction between the mac and phy layers has completed one or more of the following phy layer conditions occurs: C auto-negotiate complete C remote fault C link status change C link partner acknowledge C parallel detect fault C page received C receive error C jabber event detected 17.3 initialization and configuration t o use the ethernet controller , the peripheral must be enabled by setting the ephy0 and emac0 bits in the rcgc2 register . the following steps can then be used to configure the ethernet controller for basic operation. 1. program the macdiv register to obtain a 2.5 mhz clock (or less) on the internal mii. assuming a 20-mhz system clock, the macdiv value would be 4. 2. program the macia0 and macia1 register for address filtering. 3. program the mactctl register for auto crc generation, padding, and full-duplex operation using a value of 0x16. 4. program the macrctl register to reject frames with bad fcs using a value of 0x08. 5. enable both the t ransmitter and receive by setting the lsb in both the mactctl and macrctl registers. 6. t o transmit a frame, write the frame into the tx fifo using the macda t a register . then set the newtx bit in the mactr register to initiate the transmit process. when the newtx bit has been cleared, the tx fifo will be available for the next transmit frame. 457 september 02, 2007 preliminary lm3s8962 microcontroller 7. t o receive a frame, wait for the npr field in the macnp register to be non-zero. then begin reading the frame from the rx fifo by using the macda t a register . when the frame (including the fcs field) has been read, the npr field should decrement by one. when there are no more frames in the rx fifo, the npr field will read 0. 17.4 ethernet register map t able 17-2 on page 458 lists the ethernet mac registers. all addresses given are relative to the ethernet mac base address of 0x4004.8000. the ieee 802.3 standard specifies a register set for controlling and gathering status from the phy . the registers are collectively known as the mii management registers and are detailed in section 22.2.4 of the ieee 802.3 specification . t able 17-2 on page 458 also lists these mii management registers. all addresses given are absolute and are written directly to the regadr field of the macmctl register . the format of registers 0 to 15 are defined by the ieee specification and are common to all phy implementations. the only variance allowed is for features that may or may not be supported by a specific phy . registers 16 to 31 are vendor-specific registers, used to support features that are specific to a vendors phy implementation. v endor-specific registers not listed are reserved. t able 17-2. ethernet register map see page description reset t ype name offset ethernet mac 460 ethernet mac raw interrupt status 0x0000.0000 ro macris 0x000 462 ethernet mac interrupt acknowledge 0x0000.0000 w1c maciack 0x000 463 ethernet mac interrupt mask 0x0000.007f r/w macim 0x004 464 ethernet mac receive control 0x0000.0008 r/w macrctl 0x008 465 ethernet mac t ransmit control 0x0000.0000 r/w mactctl 0x00c 466 ethernet mac data 0x0000.0000 r/w macda t a 0x010 468 ethernet mac individual address 0 0x0000.0000 r/w macia0 0x014 469 ethernet mac individual address 1 0x0000.0000 r/w macia1 0x018 470 ethernet mac threshold 0x0000.003f r/w macthr 0x01c 471 ethernet mac management control 0x0000.0000 r/w macmctl 0x020 472 ethernet mac management divider 0x0000.0080 r/w macmdv 0x024 473 ethernet mac management t ransmit data 0x0000.0000 r/w macmtxd 0x02c 474 ethernet mac management receive data 0x0000.0000 r/w macmrxd 0x030 475 ethernet mac number of packets 0x0000.0000 ro macnp 0x034 476 ethernet mac t ransmission request 0x0000.0000 r/w mactr 0x038 477 ethernet mac t imer support 0x0000.0000 r/w macts 0x03c mii management 478 ethernet phy management register 0 C control 0x3100 r/w mr0 - september 02, 2007 458 preliminary ethernet controller see page description reset t ype name offset 480 ethernet phy management register 1 C status 0x7849 ro mr1 - 482 ethernet phy management register 2 C phy identifier 1 0x000e ro mr2 - 483 ethernet phy management register 3 C phy identifier 2 0x7237 ro mr3 - 484 ethernet phy management register 4 C auto-negotiation advertisement 0x01e1 r/w mr4 - 486 ethernet phy management register 5 C auto-negotiation link partner base page ability 0x0000 ro mr5 - 487 ethernet phy management register 6 C auto-negotiation expansion 0x0000 ro mr6 - 488 ethernet phy management register 16 C v endor-specific 0x0140 r/w mr16 - 490 ethernet phy management register 17 C interrupt control/status 0x0000 r/w mr17 - 492 ethernet phy management register 18 C diagnostic 0x0000 ro mr18 - 493 ethernet phy management register 19 C t ransceiver control 0x4000 r/w mr19 - 494 ethernet phy management register 23 C led configuration 0x0010 r/w mr23 - 495 ethernet phy management register 24 Cmdi/mdix control 0x00c0 r/w mr24 - 17.5 ethernet mac register descriptions the remainder of this section lists and describes the ethernet mac registers, in numerical order by address of fset. also see mii management register descriptions on page 477 . 459 september 02, 2007 preliminary lm3s8962 microcontroller register 1: ethernet mac raw interrupt status (macris), offset 0x000 the macris register is the interrupt status register . on a read, this register gives the current status value of the corresponding interrupt prior to masking. ethernet mac raw interrupt status (macris) base 0x4004.8000 of fset 0x000 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 rxint txer txemp fov rxer mdint phyint reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:7 phy interrupt when set, indicates that an enabled interrupt in the phy layer has occured. mr17 in the phy must be read to determine the specific phy event that triggered this interrupt. 0x0 ro phyint 6 mii t ransaction complete when set, indicates that a transaction (read or write) on the mii interface has completed successfully . 0x0 ro mdint 5 receive error this bit indicates that an error was encountered on the receiver . the possible errors that can cause this interrupt bit to be set are: a receive error occurs during the reception of a frame (100 mb/s only). the frame is not an integer number of bytes (dribble bits) due to an alignment error . the crc of the frame does not pass the fcs check. the length/type field is inconsistent with the frame data size when interpreted as a length field. 0x0 ro rxer 4 fifo overrrun when set, indicates that an overrun was encountered on the receive fifo. 0x0 ro fov 3 t ransmit fifo empty when set, indicates that the packet was transmitted and that the tx fifo is empty . 0x0 ro txemp 2 september 02, 2007 460 preliminary ethernet controller description reset t ype name bit/field t ransmit error when set, indicates that an error was encountered on the transmitter . the possible errors that can cause this interrupt bit to be set are: the data length field stored in the tx fifo exceeds 2032. the frame is not sent when this error occurs. the retransmission attempts during the backof f process have exceeded the maximum limit of 16. 0x0 ro txer 1 packet received when set, indicates that at least one packet has been received and is stored in the receiver fifo. 0x0 ro rxint 0 461 september 02, 2007 preliminary lm3s8962 microcontroller register 2: ethernet mac interrupt acknowledge (maciack), offset 0x000 a write of a 1 to any bit position of this register clears the corresponding interrupt bit in the ethernet mac raw interrupt status (macris) register . ethernet mac interrupt acknowledge (maciack) base 0x4004.8000 of fset 0x000 t ype w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 rxint txer txemp fov rxer mdint phyint reserved w1c w1c w1c w1c w1c w1c w1c ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:7 clear phy interrupt a write of a 1 clears the phyint interrupt read from the macris register . 0x0 w1c phyint 6 clear mii t ransaction complete a write of a 1 clears the mdint interrupt read from the macris register . 0x0 w1c mdint 5 clear receive error a write of a 1 clears the rxer interrupt read from the macris register . 0x0 w1c rxer 4 clear fifo overrun a write of a 1 clears the fov interrupt read from the macris register . 0x0 w1c fov 3 clear t ransmit fifo empty a write of a 1 clears the txemp interrupt read from the macris register . 0x0 w1c txemp 2 clear t ransmit error a write of a 1 clears the txer interrupt read from the macris register and resets the tx fifo write pointer . 0x0 w1c txer 1 clear packet received a write of a 1 clears the rxint interrupt read from the macris register . 0x0 w1c rxint 0 september 02, 2007 462 preliminary ethernet controller register 3: ethernet mac interrupt mask (macim), offset 0x004 this register allows software to enable/disable ethernet mac interrupts. w riting a 0 disables the interrupt, while writing a 1 enables it. ethernet mac interrupt mask (macim) base 0x4004.8000 of fset 0x004 t ype r/w , reset 0x0000.007f 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 rxintm txerm txempm fovm rxerm mdintm phyintm reserved r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:7 mask phy interrupt this bit masks the phyint bit in the macris register from being asserted. 1 r/w phyintm 6 mask mii t ransaction complete this bit masks the mdint bit in the macris register from being asserted. 1 r/w mdintm 5 mask receive error this bit masks the rxer bit in the macris register from being asserted. 1 r/w rxerm 4 mask fifo overrrun this bit masks the fov bit in the macris register from being asserted. 1 r/w fovm 3 mask t ransmit fifo empty this bit masks the txemp bit in the macris register from being asserted. 1 r/w txempm 2 mask t ransmit error this bit masks the txer bit in the macris register from being asserted. 1 r/w txerm 1 mask packet received this bit masks the rxint bit in the macris register from being asserted. 1 r/w rxintm 0 463 september 02, 2007 preliminary lm3s8962 microcontroller register 4: ethernet mac receive control (macrctl), offset 0x008 this register enables software to configure the receive module and control the types of frames that are received from the physical medium. it is important to note that when the receive module is enabled, all valid frames with a broadcast address of ff-ff-ff-ff-ff-ff in the destination address field will be received and stored in the rx fifo, even if the amul bit is not set. ethernet mac receive control (macrctl) base 0x4004.8000 of fset 0x008 t ype r/w , reset 0x0000.0008 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 rxen amul prms badcrc rstfifo reserved r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:5 clear receive fifo when set, clears the receive fifo. this should be done when software initialization is performed. it is recommended that the receiver be disabled ( rxen = 0), and then the reset initiated ( rstfifo = 1). this sequence will flush and reset the rx fifo. 0x0 r/w rstfifo 4 enable reject bad crc the badcrc bit enables the rejection of frames with an incorrectly calculated crc. 0x1 r/w badcrc 3 enable promiscuous mode the prms bit enables promiscuous mode, which accepts all valid frames, regardless of the destination address. 0x0 r/w prms 2 enable multicast frames the amul bit enables the reception of multicast frames from the physical medium. 0x0 r/w amul 1 enable receiver the rxen bit enables the ethernet receiver . when this bit is low , the receiver is disabled and all frames on the physical medium are ignored. 0x0 r/w rxen 0 september 02, 2007 464 preliminary ethernet controller register 5: ethernet mac t ransmit control (mactctl), offset 0x00c this register enables software to configure the transmit module, and control frames are placed onto the physical medium. ethernet mac t ransmit control (mactctl) base 0x4004.8000 of fset 0x00c t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 txen p aden crc reserved duplex reserved r/w r/w r/w ro r/w ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:5 enable duplex mode when set, enables duplex mode, allowing simultaneous transmission and reception. 0x0 r/w duplex 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 3 enable crc generation when set, enables the automatic generation of the crc and the placement at the end of the packet. if this bit is not set, the frames placed in the tx fifo will be sent exactly as they are written into the fifo. 0x0 r/w crc 2 enable packet padding when set, enables the automatic padding of packets that do not meet the minimum frame size. 0x0 r/w p aden 1 enable t ransmitter when set, enables the transmitter . when this bit is 0, the transmitter is disabled. 0x0 r/w txen 0 465 september 02, 2007 preliminary lm3s8962 microcontroller register 6: ethernet mac data (macda t a), offset 0x010 this register enables software to access the tx and rx fifos. reads from this register return the data stored in the rx fifo from the location indicated by the read pointer . w rites to this register store the data in the tx fifo at the location indicated by the write pointer . the write pointer is then auto-incremented to the next tx fifo location. there is no mechanism for randomly accessing bytes in either the rx or tx fifos. data must be read from the rx fifo sequentially and stored in a buf fer for further processing. once a read has been performed, the data in the fifo cannot be re-read. data must be written to the tx fifo sequentially . if an error is made in placing the frame into the tx fifo, the write pointer can be reset to the start of the tx fifo by writing the txer bit of the maciack register and then the data re-written. read-only register ethernet mac data (macda t a) base 0x4004.8000 of fset 0x010 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 rxda t a ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 rxda t a ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field receive fifo data the rxdata bits represent the next four bytes of data stored in the rx fifo. 0x0 ro rxda t a 31:0 w rite-only register ethernet mac data (macda t a) base 0x4004.8000 of fset 0x010 t ype wo, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 txda t a wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 txda t a wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo wo t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset september 02, 2007 466 preliminary ethernet controller description reset t ype name bit/field t ransmit fifo data the txdata bits represent the next four bytes of data to place in the tx fifo for transmission. 0x0 wo txda t a 31:0 467 september 02, 2007 preliminary lm3s8962 microcontroller register 7: ethernet mac individual address 0 (macia0), offset 0x014 this register enables software to program the first four bytes of the hardware mac address of the network interface card (nic). (the last two bytes are in macia1 ). the 6-byte iar is compared against the incoming destination address fields to determine whether the frame should be received. ethernet mac individual address 0 (macia0) base 0x4004.8000 of fset 0x014 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 macoct3 macoct4 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 macoct1 macoct2 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field mac address octet 4 the macoct4 bits represent the fourth octet of the mac address used to uniquely identify each ethernet controller . 0x0 r/w macoct4 31:24 mac address octet 3 the macoct3 bits represent the third octet of the mac address used to uniquely identify each ethernet controller . 0x0 r/w macoct3 23:16 mac address octet 2 the macoct2 bits represent the second octet of the mac address used to uniquely identify each ethernet controller . 0x0 r/w macoct2 15:8 mac address octet 1 the macoct1 bits represent the first octet of the mac address used to uniquely identify each ethernet controller . 0x0 r/w macoct1 7:0 september 02, 2007 468 preliminary ethernet controller register 8: ethernet mac individual address 1 (macia1), offset 0x018 this register enables software to program the last two bytes of the hardware mac address of the network interface card (nic). (the first four bytes are in macia0 ). the 6-byte iar is compared against the incoming destination address fields to determine whether the frame should be received. ethernet mac individual address 1 (macia1) base 0x4004.8000 of fset 0x018 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 macoct5 macoct6 r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:16 mac address octet 6 the macoct6 bits represent the sixth octet of the mac address used to uniquely identify each ethernet controller . 0x0 r/w macoct6 15:8 mac address octet 5 the macoct5 bits represent the fifth octet of the mac address used to uniquely identify each ethernet controller . 0x0 r/w macoct5 7:0 469 september 02, 2007 preliminary lm3s8962 microcontroller register 9: ethernet mac threshold (macthr), offset 0x01c this register enables software to set the threshold level at which the transmission of the frame begins. if the thresh bits are set to 0x3f , which is the reset value, transmission does not start until the newtx bit is set in the mactr register . this ef fectively disables the early transmission feature. w riting the thresh bits to any value besides all 1s enables the early transmission feature. once the byte count of data in the tx fifo reaches this level, transmission of the frame begins. when thresh is set to all 0s, transmission of the frame begins after 4 bytes (a single write) are stored in the tx fifo. each increment of the thresh bit field waits for an additional 32 bytes of data (eight writes) to be stored in the tx fifo. therefore, a value of 0x01 would wait for 36 bytes of data to be written while a value of 0x02 would wait for 68 bytes to be written. in general, early transmission starts when: number of bytes >= 4 ( thresh x 8 + 1) reaching the threshold level has the same ef fect as setting the newtx bit in the mactr register . t ransmission of the frame begins and then the number of bytes indicated by the data length field is sent out on the physical medium. because under-run checking is not performed, it is possible that the tail pointer may reach and pass the write pointer in the tx fifo. this causes indeterminate values to be written to the physical medium rather than the end of the frame. therefore, suf ficient bus bandwidth for writing to the tx fifo must be guaranteed by the software. if a frame smaller than the threshold level needs to be sent, the newtx bit in the mactr register must be set with an explicit write. this initiates the transmission of the frame even though the threshold limit has not been reached. if the threshold level is set too small, it is possible for the transmitter to underrun. if this occurs, the transmit frame is aborted, and a transmit error occurs. ethernet mac threshold (macthr) base 0x4004.8000 of fset 0x01c t ype r/w , reset 0x0000.003f 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 thresh reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:6 threshold v alue the thresh bits represent the early transmit threshold. once the amount of data in the tx fifo exceeds this value, transmission of the packet begins. 0x3f r/w thresh 5:0 september 02, 2007 470 preliminary ethernet controller register 10: ethernet mac management control (macmctl), offset 0x020 this register enables software to control the transfer of data to and from the mii management registers in the ethernet phy . the address, name, type, reset configuration, and functional description of each of these registers can be found in t able 17-2 on page 458 and in mii management register descriptions on page 477 . in order to initiate a read transaction from the mii management registers, the write bit must be written with a 0 during the same cycle that the start bit is written with a 1. in order to initiate a write transaction to the mii management registers, the write bit must be written with a 1 during the same cycle that the start bit is written with a 1. ethernet mac management control (macmctl) base 0x4004.8000 of fset 0x020 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 st ar t write reserved regadr reserved r/w r/w ro r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:8 mii register address the regadr bit field represents the mii management register address for the next mii management interface transaction. 0x0 r/w regadr 7:3 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 2 mii register t ransaction t ype the write bit represents the operation of the next mii management interface transaction. if write is set, the next operation will be a write; otherwise, it will be a read. 0x0 r/w write 1 mii register t ransaction enable the start bit represents the initiation of the next mii management interface transaction. when a 1 is written to this bit, the mii register located at regadr will be read ( write =0) or written ( write =1). 0x0 r/w st ar t 0 471 september 02, 2007 preliminary lm3s8962 microcontroller register 1 1: ethernet mac management divider (macmdv), offset 0x024 this register enables software to set the clock divider for the management data clock (mdc). this clock is used to synchronize read and write transactions between the system and the mii management registers. the frequency of the mdc clock can be calculated from the following formula: f mdc = f ipclk / (2 * (macmdvr + 1 )) the clock divider must be written with a value that ensures that the mdc clock will not exceed a frequency of 2.5 mhz. ethernet mac management divider (macmdv) base 0x4004.8000 of fset 0x024 t ype r/w , reset 0x0000.0080 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 div reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:8 clock divider the div bits are used to set the clock divider for the mdc clock used to transmit data between the mac and phy over the serial mii interface. 0x80 r/w div 7:0 september 02, 2007 472 preliminary ethernet controller register 12: ethernet mac management t ransmit data (macmtxd), offset 0x02c this register holds the next value to be written to the mii management registers. ethernet mac management t ransmit data (macmtxd) base 0x4004.8000 of fset 0x02c t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 mdtx r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:16 mii register t ransmit data the mdtx bits represent the data that will be written in the next mii management transaction. 0x0 r/w mdtx 15:0 473 september 02, 2007 preliminary lm3s8962 microcontroller register 13: ethernet mac management receive data (macmrxd), offset 0x030 this register holds the last value read from the mii management registers. ethernet mac management receive data (macmrxd) base 0x4004.8000 of fset 0x030 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 mdrx r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:16 mii register receive data the mdrx bits represent the data that was read in the previous mii management transaction. 0x0 r/w mdrx 15:0 september 02, 2007 474 preliminary ethernet controller register 14: ethernet mac number of packets (macnp), offset 0x034 this register holds the number of frames that are currently in the rx fifo. when npr is 0, there are no frames in the rx fifo and the rxint bit is not set. when npr is any other value, there is at least one frame in the rx fifo and the rxint bit in the macris register is set. ethernet mac number of packets (macnp) base 0x4004.8000 of fset 0x034 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 npr reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:6 number of packets in receive fifo the npr bits represent the number of packets stored in the rx fifo. while the npr field is greater than 0, the rxint interrupt in the macris register will be asserted. 0x0 ro npr 5:0 475 september 02, 2007 preliminary lm3s8962 microcontroller register 15: ethernet mac t ransmission request (mactr), offset 0x038 this register enables software to initiate the transmission of the frame currently located in the tx fifo to the physical medium. once the frame has been transmitted to the medium from the tx fifo or a transmission error has been encountered, the newtx bit is auto-cleared by the hardware. ethernet mac t ransmission request (mactr) base 0x4004.8000 of fset 0x038 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 newtx reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:1 new t ransmission when set, the newtx bit initiates an ethernet transmission once the packet has been placed in the tx fifo. this bit is cleared once the transmission has been completed. if early transmission is being used (see the macthr register), this bit does not need to be set. 0x0 r/w newtx 0 september 02, 2007 476 preliminary ethernet controller register 16: ethernet mac t imer support (macts), offset 0x03c this register enables software to enable timer support on the transmission and reception of frames. this register is only applicable for devices that have 1588 hardware support; for all others, a read returns 0s. ethernet mac t imer support (macts) base 0x4004.8000 of fset 0x03c t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 tsen reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 31:1 t ime stamp enable when set, the tsen bit multiplexes the tx and rx interrupts to the ccp inputs of general-purpose t imer 3. 0x0 r/w tsen 0 17.6 mii management register descriptions the ieee 802.3 standard specifies a register set for controlling and gathering status from the phy . the registers are collectively known as the mii management registers. all addresses given are absolute. addresses not listed are reserved. also see ethernet mac register descriptions on page 459 . 477 september 02, 2007 preliminary lm3s8962 microcontroller register 17: ethernet phy management register 0 C control (mr0), address 0x00 this register enables software to configure the operation of the phy . the default settings of these registers are designed to initialize the phy to a normal operational mode without configuration. ethernet phy management register 0 C control (mr0) base 0x4004.8000 address 0x00 t ype r/w , reset 0x3100 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved col t duplex raneg iso pwrdn anegen speedsl loopbk reset r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 reset description reset t ype name bit/field reset registers when set, resets the registers to their default state and reinitializes internal state machines. once the reset operation has completed, this bit is cleared by hardware. 0 r/w reset 15 loopback mode when set, enables the loopback mode of operation. the receive circuitry is isolated from the physical medium and transmissions are sent back through the receive circuitry instead of the medium. 0 r/w loopbk 14 speed select 1: enables the 100 mb/s mode of operation (100base-tx). 0: enables the 10 mb/s mode of operation (10base-t). 1 r/w speedsl 13 auto-negotiation enable when set, enables the auto-negotiation process. 1 r/w anegen 12 power down when set, places the phy into a low-power consuming state. 0 r/w pwrdn 1 1 isolate when set, isolates transmit and receive data paths and ignores all signaling on these buses. 0 r/w iso 10 restart auto-negotiation when set, restarts the auto-negotiation process. once the restart has initiated, this bit is cleared by hardware. 0 r/w raneg 9 set duplex mode 1: enables the full-duplex mode of operation. this bit can be set by software in a manual configuration process or by the auto-negotiation process. 0: enables the half-duplex mode of operation. 1 r/w duplex 8 september 02, 2007 478 preliminary ethernet controller description reset t ype name bit/field collision t est when set, enables the collision t est mode of operation. the colt bit asserts after the initiation of a transmission and de-asserts once the transmission is halted. 0 r/w col t 7 w rite as 0, ignore on read. 0x00 r/w reserved 6:0 479 september 02, 2007 preliminary lm3s8962 microcontroller register 18: ethernet phy management register 1 C status (mr1), address 0x01 this register enables software to determine the capabilities of the phy and perform its initialization and operation appropriately . ethernet phy management register 1 C status (mr1) base 0x4004.8000 address 0x01 t ype ro, reset 0x7849 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 extd jab link anega rf aul t anegc mfps reserved 10t_h 10t_f 100x_h 100x_f reserved ro rc ro ro rc ro ro ro ro ro ro ro ro ro ro ro t ype 1 0 0 1 0 0 1 0 0 0 0 1 1 1 1 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15 100base-tx full-duplex mode when set, indicates that the phy is capable of supporting 100base-tx full-duplex mode. 1 ro 100x_f 14 100base-tx half-duplex mode when set, indicates that the phy is capable of supporting 100base-tx half-duplex mode. 1 ro 100x_h 13 10base-t full-duplex mode when set, indicates that the phy is capable of 10base-t full-duplex mode. 1 ro 10t_f 12 10base-t half-duplex mode when set, indicates that the phy is capable of supporting 10base-t half-duplex mode. 1 ro 10t_h 1 1 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 10:7 management frames with preamble suppressed when set, indicates that the management interface is capable of receiving management frames with the preamble suppressed. 1 ro mfps 6 auto-negotiation complete when set, indicates that the auto-negotiation process has been completed and that the extended registers defined by the auto-negotiation protocol are valid. 0 ro anegc 5 remote fault when set, indicates that a remote fault condition has been detected. this bit remains set until it is read, even if the condition no longer exists. 0 rc rf aul t 4 september 02, 2007 480 preliminary ethernet controller description reset t ype name bit/field auto-negotiation when set, indicates that the phy has the ability to perform auto-negotiation. 1 ro anega 3 link made when set, indicates that a valid link has been established by the phy . 0 ro link 2 jabber condition when set, indicates that a jabber condition has been detected by the phy . this bit remains set until it is read, even if the jabber condition no longer exists. 0 rc jab 1 extended capabilities when set, indicates that the phy provides an extended set of capabilities that can be accessed through the extended register set. 1 ro extd 0 481 september 02, 2007 preliminary lm3s8962 microcontroller register 19: ethernet phy management register 2 C phy identifier 1 (mr2), address 0x02 this register , along with mr3 , provides a 32-bit value indicating the manufacturer , model, and revision information. ethernet phy management register 2 C phy identifier 1 (mr2) base 0x4004.8000 address 0x02 t ype ro, reset 0x000e 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 oui[21:6] ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field organizationally unique identifier[21:6] this field, along with the oui[5:0] field in mr3 , makes up the organizationally unique identifier indicating the phy manufacturer . 0x000e ro oui[21:6] 15:0 september 02, 2007 482 preliminary ethernet controller register 20: ethernet phy management register 3 C phy identifier 2 (mr3), address 0x03 this register , along with mr2 , provides a 32-bit value indicating the manufacturer , model, and revision information. ethernet phy management register 3 C phy identifier 2 (mr3) base 0x4004.8000 address 0x03 t ype ro, reset 0x7237 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 rn mn oui[5:0] ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 1 1 1 0 1 1 0 0 0 1 0 0 1 1 1 0 reset description reset t ype name bit/field organizationally unique identifier[5:0] this field, along with the oui[21:6] field in mr2 , makes up the organizationally unique identifier indicating the phy manufacturer . 0x1c ro oui[5:0] 15:10 model number the mn field represents the model number of the phy . 0x23 ro mn 9:4 revision number the rn field represents the revision number of the phy . 0x7 ro rn 3:0 483 september 02, 2007 preliminary lm3s8962 microcontroller register 21: ethernet phy management register 4 C auto-negotiation advertisement (mr4), address 0x04 this register provides the advertised abilities of the phy used during auto-negotiation. bits 8:5 represent the t echnology ability field bits. this field can be overwritten by software to auto-negotiate to an alternate common technology . w riting to this register has no ef fect until auto-negotiation is re-initiated. ethernet phy management register 4 C auto-negotiation advertisement (mr4) base 0x4004.8000 address 0x04 t ype r/w , reset 0x01e1 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 s[4:0] a0 a1 a2 a3 reserved rf reserved np ro ro ro ro ro r/w r/w r/w r/w ro ro ro ro r/w ro ro t ype 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 reset description reset t ype name bit/field next page when set, indicates the phy is capable of next page exchanges to provide more detailed information on the phy s capabilities. 0 ro np 15 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 14 remote fault when set, indicates to the link partner that a remote fault condition has been encountered. 0 r/w rf 13 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 12:9 t echnology ability field[3] when set, indicates that the phy supports the 100base-tx full-duplex signaling protocol. if software wants to ensure that this mode is not used, this bit can be written to 0 and auto-negotiation re-initiated with the raneg bit in the mr0 register . 1 r/w a3 8 t echnology ability field[2] when set, indicates that the phy supports the 100base-t half-duplex signaling protocol. if software wants to ensure that this mode is not used, this bit can be written to 0 and auto-negotiation re-initiated. 1 r/w a2 7 t echnology ability field[1] when set, indicates that the phy supports the 10base-t full-duplex signaling protocol. if software wants to ensure that this mode is not used, this bit can be written to 0 and auto-negotiation re-initiated. 1 r/w a1 6 t echnology ability field[0] when set, indicates that the phy supports the 10base-t half-duplex signaling protocol. if software wants to ensure that this mode is not used, this bit can be written to 0 and auto-negotiation re-initiated. 1 r/w a0 5 september 02, 2007 484 preliminary ethernet controller description reset t ype name bit/field selector field the s[4:0] field encodes 32 possible messages for communicating between phys. this field is hard-coded to 0x01, indicating that the stellaris ? phy is ieee 802.3 compliant. 0x01 ro s[4:0] 4:0 485 september 02, 2007 preliminary lm3s8962 microcontroller register 22: ethernet phy management register 5 C auto-negotiation link partner base page ability (mr5), address 0x05 this register provides the advertised abilities of the link partner s phy that are received and stored during auto-negotiation. ethernet phy management register 5 C auto-negotiation link partner base page ability (mr5) base 0x4004.8000 address 0x05 t ype ro, reset 0x0000 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 s[4:0] a[7:0] rf ack np ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field next page when set, indicates that the link partner s phy is capable of next page exchanges to provide more detailed information on the phy s capabilities. 0 ro np 15 acknowledge when set, indicates that the device has successfully received the link partner s advertised abilities during auto-negotiation. 0 ro ack 14 remote fault used as a standard transport mechanism for transmitting simple fault information. 0 ro rf 13 t echnology ability field the a[7:0] field encodes individual technologies that are supported by the phy . see the mr4 register . 0x00 ro a[7:0] 12:5 selector field the s[4:0] field encodes possible messages for communicating between phys. description v alue reserved 0x00 ieee std 802.3 0x01 ieee std 802.9 islan-16t 0x02 ieee std 802.5 0x03 ieee std 1394 0x04 reserved 0x05C0x1f 0x00 ro s[4:0] 4:0 september 02, 2007 486 preliminary ethernet controller register 23: ethernet phy management register 6 C auto-negotiation expansion (mr6), address 0x06 this register enables software to determine the auto-negotiation and next page capabilities of the phy and the link partner after auto-negotiation. ethernet phy management register 6 C auto-negotiation expansion (mr6) base 0x4004.8000 address 0x06 t ype ro, reset 0x0000 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 lp anega prx reserved lpnp a pdf reserved ro rc ro ro rc ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 15:5 parallel detection fault when set, indicates that more than one technology has been detected at link up. this bit is cleared when read. 0 rc pdf 4 link partner is next page able when set, indicates that the link partner is next page able. 0 ro lpnp a 3 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x000 ro reserved 2 new page received when set, indicates that a new page has been received from the link partner and stored in the appropriate location. this bit remains set until the register is read. 0 rc prx 1 link partner is auto-negotiation able when set, indicates that the link partner is auto-negotiation able. 0 ro lp anega 0 487 september 02, 2007 preliminary lm3s8962 microcontroller register 24: ethernet phy management register 16 C v endor-specific (mr16), address 0x10 this register enables software to configure the operation of vendor-specific modes of the phy . ethernet phy management register 16 C v endor-specific (mr16) base 0x4004.8000 address 0x10 t ype r/w , reset 0x0140 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 rxcc pcsbp reserved r vspol apol reserved nl10 sqei txhim reserved inpol rptr r/w r/w ro ro r/w r/w ro ro ro ro r/w r/w r/w ro r/w r/w t ype 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 reset description reset t ype name bit/field repeater mode when set, enables the repeater mode of operation. in this mode, full-duplex is not allowed and the carrier sense signal only responds to receive activity . if the phy is configured to 10base-t mode, the sqe test function is disabled. 0 r/w rptr 15 interrupt polarity 1: sets the polarity of the phy interrupt to be active high. 0: sets the polarity of the phy interrupt to active low . important: because the media access controller expects active low interrupts from the phy , this bit must always be written with a 0 to ensure proper operation. 0 r/w inpol 14 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 13 t ransmit high impedance mode when set, enables the transmitter high impedance mode. in this mode, the txop and txon transmitter pins are put into a high impedance state. the rxip and rxin pins remain fully functional. 0 r/w txhim 12 sqe inhibit t esting when set, prohibits 10base-t sqe testing. when 0, the sqe testing is performed by generating a collision pulse following the completion of the transmission of a frame. 0 r/w sqei 1 1 natural loopback mode when set, enables the 10base-t natural loopback mode. this causes the transmission data received by the phy to be looped back onto the receive data path when 10base-t mode is enabled. 0 r/w nl10 10 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x05 ro reserved 9:6 september 02, 2007 488 preliminary ethernet controller description reset t ype name bit/field auto-polarity disable when set, disables the phy s auto-polarity function. if this bit is 0, the phy automatically inverts the received signal due to a wrong polarity connection during auto-negotiation if the phy is in 10base-t mode. 0 r/w apol 5 receive data polarity this bit indicates whether the receive data pulses are being inverted. if the apol bit is 0, then the rvspol bit is read-only and indicates whether the auto-polarity circuitry is reversing the polarity . in this case, a 1 in the rvspol bit indicates that the receive data is inverted while a 0 indicates that the receive data is not inverted. if the apol bit is 1, then the rvspol bit is writable and software can force the receive data to be inverted. setting rvspol to 1 forces the receive data to be inverted while a 0 does not invert the receive data. 0 r/w r vspol 4 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 3:2 pcs bypass when set, enables the bypass of the pcs and scrambling/descrambling functions in 100base-tx mode. this mode is only valid when auto-negotiation is disabled and 100base-t mode is enabled. 0 r/w pcsbp 1 receive clock control when set, enables the receive clock control power saving mode if the phy is configured in 100base-tx mode. this mode shuts down the receive clock when no data is being received from the physical medium to save power . this mode should not be used when pcsbp is enabled and is automatically disabled when the loopbk bit in the mr0 register is set. 0 r/w rxcc 0 489 september 02, 2007 preliminary lm3s8962 microcontroller register 25: ethernet phy management register 17 C interrupt control/status (mr17), address 0x1 1 this register provides the means for controlling and observing the events, which trigger a phy interrupt in the macris register . this register can also be used in a polling mode via the mii serial interface as a means to observe key events within the phy via one register address. bits 0 through 7 are status bits, which are each set to logic 1 based on an event. these bits are cleared after the register is read. bits 8 through 15 of this register , when set to logic 1, enable their corresponding bit in the lower byte to signal a phy interrupt in the macris register . ethernet phy management register 17 C interrupt control/status (mr17) base 0x4004.8000 address 0x1 1 t ype r/w , reset 0x0000 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 anegcomp_int rf aul t_int lschg_int lp ack_int pdf_int prx_int rxer_int jabber_int anegcomp_ie rf aul t_ie lschg_ie lp ack_ie pdf_ie prx_ie rxer_ie jabber_ie rc rc rc rc rc rc rc rc r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field jabber interrupt enable when set, enables system interrupts when a jabber condition is detected by the phy . 0 r/w jabber_ie 15 receive error interrupt enable when set, enables system interrupts when a receive error is detected by the phy . 0 r/w rxer_ie 14 page received interrupt enable when set, enables system interrupts when a new page is received by the phy . 0 r/w prx_ie 13 parallel detection fault interrupt enable when set, enables system interrupts when a parallel detection fault is detected by the phy . 0 r/w pdf_ie 12 lp acknowledge interrupt enable when set, enables system interrupts when flp bursts are received with the acknowledge bit during auto-negotiation. 0 r/w lp ack_ie 1 1 link status change interrupt enable when set, enables system interrupts when the link status changes from ok to f ail. 0 r/w lschg_ie 10 remote fault interrupt enable when set, enables system interrupts when a remote fault condition is signaled by the link partner . 0 r/w rf aul t_ie 9 auto-negotiation complete interrupt enable when set, enables system interrupts when the auto-negotiation sequence has completed successfully . 0 r/w anegcomp_ie 8 september 02, 2007 490 preliminary ethernet controller description reset t ype name bit/field jabber event interrupt when set, indicates that a jabber event has been detected by the 10base-t circuitry . 0 rc jabber_int 7 receive error interrupt when set, indicates that a receive error has been detected by the phy . 0 rc rxer_int 6 page receive interrupt when set, indicates that a new page has been received from the link partner during auto-negotiation. 0 rc prx_int 5 parallel detection fault interrupt when set, indicates that a parallel detection fault has been detected by the phy during the auto-negotiation process. 0 rc pdf_int 4 lp acknowledge interrupt when set, indicates that an flp burst has been received with the acknowledge bit set during auto-negotiation. 0 rc lp ack_int 3 link status change interrupt when set, indicates that the link status has changed from ok to f ail. 0 rc lschg_int 2 remote fault interrupt when set, indicates that a remote fault condition has been signaled by the link partner . 0 rc rf aul t_int 1 auto-negotiation complete interrupt when set, indicates that the auto-negotiation sequence has completed successfully . 0 rc anegcomp_int 0 491 september 02, 2007 preliminary lm3s8962 microcontroller register 26: ethernet phy management register 18 C diagnostic (mr18), address 0x12 this register enables software to diagnose the results of the previous auto-negotiation. ethernet phy management register 18 C diagnostic (mr18) base 0x4004.8000 address 0x12 t ype ro, reset 0x0000 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved rx_lock rxsd ra te dplx anegf reserved ro ro ro ro ro ro ro ro ro ro ro ro rc ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 15:13 auto-negotiation failure when set, indicates that no common technology was found during auto-negotiation and has failed. this bit remains set until read. 0 rc anegf 12 duplex mode when set, indicates that full-duplex was the highest common denominator found during the auto-negotiation process. otherwise, half-duplex was the highest common denominator found. 0 ro dplx 1 1 rate when set, indicates that 100base-tx was the highest common denominator found during the auto-negotiation process. otherwise, 10base-tx was the highest common denominator found. 0 ro ra te 10 receive detection when set, indicates that receive signal detection has occurred (in 100base-tx mode) or that manchester-encoded data has been detected (in 10base-t mode). 0 ro rxsd 9 receive pll lock when set, indicates that the receive pll has locked onto the receive signal for the selected speed of operation (10base-t or 100base-tx). 0 ro rx_lock 8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 00 ro reserved 7:0 september 02, 2007 492 preliminary ethernet controller register 27: ethernet phy management register 19 C t ransceiver control (mr19), address 0x13 this register enables software to set the gain of the transmit output to compensate for transformer loss. ethernet phy management register 19 C t ransceiver control (mr19) base 0x4004.8000 address 0x13 t ype r/w , reset 0x4000 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved txo[1:0] ro ro ro ro ro ro ro ro ro ro ro ro ro ro r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 reset description reset t ype name bit/field t ransmit amplitude selection the txo[1:0] field sets the transmit output amplitude to account for transmit transformer insertion loss. description v alue gain set for 0.0db of insertion loss 0x0 gain set for 0.4db of insertion loss 0x1 gain set for 0.8db of insertion loss 0x2 gain set for 1.2db of insertion loss 0x3 1 r/w txo[1:0] 15:14 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 13:0 493 september 02, 2007 preliminary lm3s8962 microcontroller register 28: ethernet phy management register 23 C led configuration (mr23), address 0x17 this register enables software to select the source that will cause the leds to toggle. ethernet phy management register 23 C led configuration (mr23) base 0x4004.8000 address 0x17 t ype r/w , reset 0x0010 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 led0[3:0] led1[3:0] reserved r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 15:8 led1 source the led1 field selects the source that will toggle the led1 signal. description v alue link ok 0x0 rx or tx activity (default led1) 0x1 tx activity 0x2 rx activity 0x3 collision 0x4 100base-tx mode 0x5 10base-t mode 0x6 full-duplex 0x7 link ok & blink=rx or tx activity 0x8 1 r/w led1[3:0] 7:4 led0 source the led0 field selects the source that will toggle the led0 signal. description v alue link ok (default led0) 0x0 rx or tx activity 0x1 tx activity 0x2 rx activity 0x3 collision 0x4 100base-tx mode 0x5 10base-t mode 0x6 full-duplex 0x7 link ok & blink=rx or tx activity 0x8 0 r/w led0[3:0] 3:0 september 02, 2007 494 preliminary ethernet controller register 29: ethernet phy management register 24 Cmdi/mdix control (mr24), address 0x18 this register enables software to control the behavior of the mdi/mdix mux and its switching capabilities. ethernet phy management register 24 Cmdi/mdix control (mr24) base 0x4004.8000 address 0x18 t ype r/w , reset 0x00c0 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 mdix_sd mdix_cm mdix aut o_sw pd_mode reserved r/w r/w r/w r/w ro r/w r/w r/w ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 15:8 parallel detection mode when set, enables the parallel detection mode and allows auto-switching to work when auto-negotiation is not enabled. 0 r/w pd_mode 7 auto-switching enable when set, enables auto-switching of the mdi/mdix mux. 0 r/w aut o_sw 6 auto-switching configuration when set, indicates that the mdi/mdix mux is in the crossover (mdix) configuration. when 0, it indicates that the mux is in the pass-through (mdi) configuration. when the auto_sw bit is 1, the mdix bit is read-only . when the auto_sw bit is 0, the mdix bit is read/write and can be configured manually . 0 r/w mdix 5 auto-switching complete when set, indicates that the auto-switching sequence has completed. if 0, it indicates that the sequence has not completed or that auto-switching is disabled. 0 ro mdix_cm 4 auto-switching seed this field provides the initial seed for the switching algorithm. this seed directly af fects the number of attempts [5,4] respectively to write bits [3:0]. a 0 sets the seed to 0x5. 0 r/w mdix_sd 3:0 495 september 02, 2007 preliminary lm3s8962 microcontroller 18 analog comparator an analog comparator is a peripheral that compares two analog voltages, and provides a logical output that signals the comparison result. the lm3s8962 controller provides one analog comparator that can be configured to drive an output or generate an interrupt or adc event. note: not all comparators have the option to drive an output pin. see the comparator operating mode tables for more information. a comparator can compare a test voltage against any one of these voltages: an individual external reference voltage a shared single external reference voltage a shared internal reference voltage the comparator can provide its output to a device pin, acting as a replacement for an analog comparator on the board, or it can be used to signal the application via interrupts or triggers to the adc to cause it to start capturing a sample sequence. the interrupt generation and adc triggering logic is separate. this means, for example, that an interrupt can be generated on a rising edge and the adc triggered on a falling edge. 18.1 block diagram figure 18-1. analog comparator module block diagram 18.2 functional description important: it is recommended that the digital-input enable (the gpioden bit in the gpio module) for the analog input pin be disabled to prevent excessive current draw from the i/o pads. the comparator compares the vin- and vin+ inputs to produce an output, vout . vin- < vin+, vout = 1 vin- > vin+, vout = 0 september 02, 2007 496 preliminary analog comparator v oltage ref a crefctl output +v e input (alter nate) +v e input interr upt tr igger -v e input ref erence input compar ator 0 a cst a t0 a cctl0 c0+ inter nal b us tr igger interr upt c0- c0o as shown in figure 18-2 on page 497 , the input source for vin- is an external input. in addition to an external input, input sources for vin+ can be the +ve input of comparator 0 or an internal reference. figure 18-2. structure of comparator unit a comparator is configured through two status/control registers ( acctl and acst a t ). the internal reference is configured through one control register ( acrefctl ). interrupt status and control is configured through three registers ( acmis , acris , and acinten ). the operating modes of the comparators are shown in the comparator operating mode tables. t ypically , the comparator output is used internally to generate controller interrupts. it may also be used to drive an external pin or generate an analog-to-digital converter (adc) trigger . important: certain register bit values must be set before using the analog comparators. the proper pad configuration for the comparator input and output pins are described in the comparator operating mode tables. t able 18-1. comparator 0 operating modes comparator 0 accntl0 adc t rigger interrupt output vin+ vin- asrcp yes yes c0o c0+ c0- 00 yes yes c0o c0+ c0- 01 yes yes c0o v ref c0- 10 yes yes c0o reserved c0- 1 1 18.2.1 internal reference programming the structure of the internal reference is shown in figure 18-3 on page 498 . this is controlled by a single configuration register ( acrefctl ). t able 18-2 on page 498 shows the programming options to develop specific internal reference values, to compare an external voltage against a particular voltage generated internally . 497 september 02, 2007 preliminary lm3s8962 microcontroller a cst a t a cctl intgen t r iggen 2 1 0 cinv output -v e input +v e input interr upt inter nal b us tr igger +v e input (alter nate) ref erence input figure 18-3. comparator internal reference structure t able 18-2. internal reference v oltage and acrefctl field v alues output reference v oltage based on vref field v alue acrefctl register rng bit v alue en bit v alue 0 v (gnd) for any value of vref; however , it is recommended that rng=1 and vref=0 for the least noisy ground reference. rng=x en=0 t otal resistance in ladder is 32 r. the range of internal reference in this mode is 0.825-2.37 v . rng=0 en=1 t otal resistance in ladder is 24 r. v ref = 0.1375 x v ref the range of internal reference for this mode is 0.0-2.0625 v . rng=1 18.3 initialization and configuration the following example shows how to configure an analog comparator to read back its output value from an internal register . 1. enable the analog comparator 0 clock by writing a value of 0x0010.0000 to the rcgc1 register in the system control module. 2. in the gpio module, enable the gpio port/pin associated with c0- as a gpio input. september 02, 2007 498 preliminary analog comparator v r e f a v d d r v r e f r t - - - - - - - - - - - - - - - - - = 8r r r 8r r r ??? ??? 0 decoder 1 15 14 a vdd en inter nal ref erence vref rng v r e f a v d d v re f ( ) 2 4 - - - - - - - - - - - - - - - - - - - - - = v r e f a v d d r v r e f r t - - - - - - - - - - - - - - - - - = v r e f 0 . 8 2 5 0 . 1 0 3 v r e f + = v r e f a v d d v re f 8 + ( ) 3 2 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - = 3. configure the internal voltage reference to 1.65 v by writing the acrefctl register with the value 0x0000.030c. 4. configure comparator 0 to use the internal voltage reference and to not invert the output on the c0o pin by writing the acctl0 register with the value of 0x0000.040c. 5. delay for some time. 6. read the comparator output value by reading the acst a t0 register s oval value. change the level of the signal input on c0- to see the oval value change. 18.4 register map t able 18-3 on page 499 lists the comparator registers. the of fset listed is a hexadecimal increment to the register s address, relative to the analog comparator base address of 0x4003.c000. t able 18-3. analog comparators register map see page description reset t ype name offset 500 analog comparator masked interrupt status 0x0000.0000 r/w1c acmis 0x00 501 analog comparator raw interrupt status 0x0000.0000 ro acris 0x04 502 analog comparator interrupt enable 0x0000.0000 r/w acinten 0x08 503 analog comparator reference v oltage control 0x0000.0000 r/w acrefctl 0x10 504 analog comparator status 0 0x0000.0000 ro acst a t0 0x20 505 analog comparator control 0 0x0000.0000 r/w acctl0 0x24 18.5 register descriptions the remainder of this section lists and describes the analog comparator registers, in numerical order by address of fset. 499 september 02, 2007 preliminary lm3s8962 microcontroller register 1: analog comparator masked interrupt status (acmis), offset 0x00 this register provides a summary of the interrupt status (masked) of the comparator . analog comparator masked interrupt status (acmis) base 0x4003.c000 of fset 0x00 t ype r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 in0 reserved r/w1c ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 comparator 0 masked interrupt status gives the masked interrupt state of this interrupt. w rite 1 to this bit to clear the pending interrupt. 0 r/w1c in0 0 september 02, 2007 500 preliminary analog comparator register 2: analog comparator raw interrupt status (acris), offset 0x04 this register provides a summary of the interrupt status (raw) of the comparator . analog comparator raw interrupt status (acris) base 0x4003.c000 of fset 0x04 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 in0 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 comparator 0 interrupt status when set, indicates that an interrupt has been generated by comparator 0. 0 ro in0 0 501 september 02, 2007 preliminary lm3s8962 microcontroller register 3: analog comparator interrupt enable (acinten), offset 0x08 this register provides the interrupt enable for the comparator . analog comparator interrupt enable (acinten) base 0x4003.c000 of fset 0x08 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 in0 reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 comparator 0 interrupt enable when set, enables the controller interrupt from the comparator 0 output. 0 r/w in0 0 september 02, 2007 502 preliminary analog comparator register 4: analog comparator reference v oltage control (acrefctl), offset 0x10 this register specifies whether the resistor ladder is powered on as well as the range and tap. analog comparator reference v oltage control (acrefctl) base 0x4003.c000 of fset 0x10 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 vref reserved rng en reserved r/w r/w r/w r/w ro ro ro ro r/w r/w ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:10 resistor ladder enable the en bit specifies whether the resistor ladder is powered on. if 0, the resistor ladder is unpowered. if 1, the resistor ladder is connected to the analog v dd . this bit is reset to 0 so that the internal reference consumes the least amount of power if not used and programmed. 0 r/w en 9 resistor ladder range the rng bit specifies the range of the resistor ladder . if 0, the resistor ladder has a total resistance of 32 r. if 1, the resistor ladder has a total resistance of 24 r. 0 r/w rng 8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 7:4 resistor ladder v oltage ref the vref bit field specifies the resistor ladder tap that is passed through an analog multiplexer . the voltage corresponding to the tap position is the internal reference voltage available for comparison. see t able 18-2 on page 498 for some output reference voltage examples. 0x00 r/w vref 3:0 503 september 02, 2007 preliminary lm3s8962 microcontroller register 5: analog comparator status 0 (acst a t0), offset 0x20 this register specifies the current output value of the comparator . analog comparator status 0 (acst a t0) base 0x4003.c000 of fset 0x20 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved ov al reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:2 comparator output v alue the oval bit specifies the current output value of the comparator . 0 ro ov al 1 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 september 02, 2007 504 preliminary analog comparator register 6: analog comparator control 0 (acctl0), offset 0x24 this register configures the comparator s input and output. analog comparator control 0 (acctl0) base 0x4003.c000 of fset 0x24 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 reserved cinv isen isl v al tsen tsl v al reserved asrcp t oen reserved ro r/w r/w r/w r/w r/w r/w r/w ro r/w r/w r/w ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:12 t rigger output enable the toen bit enables the adc event transmission to the adc. if 0, the event is suppressed and not sent to the adc. if 1, the event is transmitted to the adc. 0 r/w t oen 1 1 analog source positive the asrcp field specifies the source of input voltage to the vin+ terminal of the comparator . the encodings for this field are as follows: function v alue pin value 0x0 pin value of c0+ 0x1 internal voltage reference 0x2 reserved 0x3 0x00 r/w asrcp 10:9 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 8 t rigger sense level v alue the tslval bit specifies the sense value of the input that generates an adc event if in level sense mode. if 0, an adc event is generated if the comparator output is low . otherwise, an adc event is generated if the comparator output is high. 0 r/w tsl v al 7 505 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field t rigger sense the tsen field specifies the sense of the comparator output that generates an adc event. the sense conditioning is as follows: function v alue level sense, see tslval 0x0 falling edge 0x1 rising edge 0x2 either edge 0x3 0x0 r/w tsen 6:5 interrupt sense level v alue the islval bit specifies the sense value of the input that generates an interrupt if in level sense mode. if 0, an interrupt is generated if the comparator output is low . otherwise, an interrupt is generated if the comparator output is high. 0 r/w isl v al 4 interrupt sense the isen field specifies the sense of the comparator output that generates an interrupt. the sense conditioning is as follows: function v alue level sense, see islval 0x0 falling edge 0x1 rising edge 0x2 either edge 0x3 0x0 r/w isen 3:2 comparator output invert the cinv bit conditionally inverts the output of the comparator . if 0, the output of the comparator is unchanged. if 1, the output of the comparator is inverted prior to being processed by hardware. 0 r/w cinv 1 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0 ro reserved 0 september 02, 2007 506 preliminary analog comparator 19 pulse w idth modulator (pwm) pulse width modulation (pwm) is a powerful technique for digitally encoding analog signal levels. high-resolution counters are used to generate a square wave, and the duty cycle of the square wave is modulated to encode an analog signal. t ypical applications include switching power supplies and motor control. the stellaris ? pwm module consists of three pwm generator blocks and a control block. each pwm generator block contains one timer (16-bit down or up/down counter), two pwm comparators, a pwm signal generator , a dead-band generator , and an interrupt/adc-trigger selector . the control block determines the polarity of the pwm signals, and which signals are passed through to the pins. each pwm generator block produces two pwm signals that can either be independent signals (other than being based on the same timer and therefore having the same frequency) or a single pair of complementary signals with dead-band delays inserted. the output of the pwm generation blocks are managed by the output control block before being passed to the device pins. the stellaris ? pwm module provides a great deal of flexibility . it can generate simple pwm signals, such as those required by a simple charge pump. it can also generate paired pwm signals with dead-band delays, such as those required by a half-h bridge driver . it can also generate the full six channels of gate controls required by a 3-phase inverter bridge. 19.1 block diagram figure 19-1 on page 507 provides a block diagram of a stellaris ? pwm module. the lm3s8962 controller contains three generator blocks (pwm0, pwm1, and pwm2) and generates six independent pwm signals or three paired pwm signals with dead-band delays inserted. figure 19-1. pwm module block diagram 19.2 functional description 19.2.1 pwm t imer the timer in each pwm generator runs in one of two modes: count-down mode or count-up/down mode. in count-down mode, the timer counts from the load value to zero, goes back to the load value, and continues counting down. in count-up/down mode, the timer counts from zero up to the 507 september 02, 2007 preliminary lm3s8962 microcontroller interrupt and t rigger generate pwmninten pwmnris pwmnisc pwm clock interrupt dead-band generator pwmndbctl pwmndbrise pwmndbf all pwm output control pwmenable pwminver t pwmf aul t pwm generator pwmngena pwmngenb pwma pwmb t imer pwmnload pwmncount comparator a pwmncmp a comparator b pwmncmpb zero load dir 16 cmpa cmpb fault pwm generator block load value, back down to zero, back up to the load value, and so on. generally , count-down mode is used for generating left- or right-aligned pwm signals, while the count-up/down mode is used for generating center-aligned pwm signals. the timers output three signals that are used in the pwm generation process: the direction signal (this is always low in count-down mode, but alternates between low and high in count-up/down mode), a single-clock-cycle-width high pulse when the counter is zero, and a single-clock-cycle-width high pulse when the counter is equal to the load value. note that in count-down mode, the zero pulse is immediately followed by the load pulse. 19.2.2 pwm comparators there are two comparators in each pwm generator that monitor the value of the counter; when either match the counter , they output a single-clock-cycle-width high pulse. when in count-up/down mode, these comparators match both when counting up and when counting down; they are therefore qualified by the counter direction signal. these qualified pulses are used in the pwm generation process. if either comparator match value is greater than the counter load value, then that comparator never outputs a high pulse. figure 19-2 on page 508 shows the behavior of the counter and the relationship of these pulses when the counter is in count-down mode. figure 19-3 on page 509 shows the behavior of the counter and the relationship of these pulses when the counter is in count-up/down mode. figure 19-2. pwm count-down mode september 02, 2007 508 preliminary pulse w idth modulator (pwm) load zero compb compa load zero b a dir ado wn bdo wn figure 19-3. pwm count-up/down mode 19.2.3 pwm signal generator the pwm generator takes these pulses (qualified by the direction signal), and generates two pwm signals. in count-down mode, there are four events that can af fect the pwm signal: zero, load, match a down, and match b down. in count-up/down mode, there are six events that can af fect the pwm signal: zero, load, match a down, match a up, match b down, and match b up. the match a or match b events are ignored when they coincide with the zero or load events. if the match a and match b events coincide, the first signal, pwma , is generated based only on the match a event, and the second signal, pwmb , is generated based only on the match b event. for each event, the ef fect on each output pwm signal is programmable: it can be left alone (ignoring the event), it can be toggled, it can be driven low , or it can be driven high. these actions can be used to generate a pair of pwm signals of various positions and duty cycles, which do or do not overlap. figure 19-4 on page 509 shows the use of count-up/down mode to generate a pair of center-aligned, overlapped pwm signals that have dif ferent duty cycles. figure 19-4. pwm generation example in count-up/down mode in this example, the first generator is set to drive high on match a up, drive low on match a down, and ignore the other four events. the second generator is set to drive high on match b up, drive low on match b down, and ignore the other four events. changing the value of comparator a 509 september 02, 2007 preliminary lm3s8962 microcontroller load zero compb compa load zero b a dir b up a up ado wn bdo wn load zero compb compa pwmb pwma changes the duty cycle of the pwma signal, and changing the value of comparator b changes the duty cycle of the pwmb signal. 19.2.4 dead-band generator the two pwm signals produced by the pwm generator are passed to the dead-band generator . if disabled, the pwm signals simply pass through unmodified. if enabled, the second pwm signal is lost and two pwm signals are generated based on the first pwm signal. the first output pwm signal is the input signal with the rising edge delayed by a programmable amount. the second output pwm signal is the inversion of the input signal with a programmable delay added between the falling edge of the input signal and the rising edge of this new signal. this is therefore a pair of active high signals where one is always high, except for a programmable amount of time at transitions where both are low . these signals are therefore suitable for driving a half-h bridge, with the dead-band delays preventing shoot-through current from damaging the power electronics. figure 19-5 on page 510 shows the ef fect of the dead-band generator on an input pwm signal. figure 19-5. pwm dead-band generator 19.2.5 interrupt/adc-t rigger selector the pwm generator also takes the same four (or six) counter events and uses them to generate an interrupt or an adc trigger . any of these events or a set of these events can be selected as a source for an interrupt; when any of the selected events occur , an interrupt is generated. additionally , the same event, a dif ferent event, the same set of events, or a dif ferent set of events can be selected as a source for an adc trigger; when any of these selected events occur , an adc trigger pulse is generated. the selection of events allows the interrupt or adc trigger to occur at a specific position within the pwm signal. note that interrupts and adc triggers are based on the raw events; delays in the pwm signal edges caused by the dead-band generator are not taken into account. 19.2.6 synchronization methods there is a global reset capability that can synchronously reset any or all of the counters in the pwm generators. if multiple pwm generators are configured with the same counter load value, this can be used to guarantee that they also have the same count value (this does imply that the pwm generators must be configured before they are synchronized). with this, more than two pwm signals can be produced with a known relationship between the edges of those signals since the counters always have the same values. the counter load values and comparator match values of the pwm generator can be updated in two ways. the first is immediate update mode, where a new value is used as soon as the counter reaches zero. by waiting for the counter to reach zero, a guaranteed behavior is defined, and overly short or overly long output pwm pulses are prevented. the other update method is synchronous, where the new value is not used until a global synchronized update signal is asserted, at which point the new value is used as soon as the counter reaches zero. this second mode allows multiple items in multiple pwm generators to be updated september 02, 2007 510 preliminary pulse w idth modulator (pwm) input pwma pwmb rising edge dela y f alling edge dela y simultaneously without odd ef fects during the update; everything runs from the old values until a point at which they all run from the new values. the update mode of the load and comparator match values can be individually configured in each pwm generator block. it typically makes sense to use the synchronous update mechanism across pwm generator blocks when the timers in those blocks are synchronized, though this is not required in order for this mechanism to function properly . 19.2.7 fault conditions there are two external conditions that af fect the pwm block; the signal input on the fault pin and the stalling of the controller by a debugger . there are two mechanisms available to handle such conditions: the output signals can be forced into an inactive state and/or the pwm timers can be stopped. each output signal has a fault bit. if set, a fault input signal causes the corresponding output signal to go into the inactive state. if the inactive state is a safe condition for the signal to be in for an extended period of time, this keeps the output signal from driving the outside world in a dangerous manner during the fault condition. a fault condition can also generate a controller interrupt. each pwm generator can also be configured to stop counting during a stall condition. the user can select for the counters to run until they reach zero then stop, or to continue counting and reloading. a stall condition does not generate a controller interrupt. 19.2.8 output control block with each pwm generator block producing two raw pwm signals, the output control block takes care of the final conditioning of the pwm signals before they go to the pins. v ia a single register , the set of pwm signals that are actually enabled to the pins can be modified; this can be used, for example, to perform commutation of a brushless dc motor with a single register write (and without modifying the individual pwm generators, which are modified by the feedback control loop). similarly , fault control can disable any of the pwm signals as well. a final inversion can be applied to any of the pwm signals, making them active low instead of the default active high. 19.3 initialization and configuration the following example shows how to initialize the pwm generator 0 with a 25-khz frequency , and with a 25% duty cycle on the pwm0 pin and a 75% duty cycle on the pwm1 pin. this example assumes the system clock is 20 mhz. 1. enable the pwm clock by writing a value of 0x0010.0000 to the rcgc0 register in the system control module. 2. enable the clock to the appropriate gpio module via the rcgc2 register in the system control module. 3. in the gpio module, enable the appropriate pins for their alternate function using the gpioafsel register . 4. configure the run-mode clock configuration (rcc) register in the system control module to use the pwm divide ( usepwmdiv ) and set the divider ( pwmdiv ) to divide by 2 (000). 5. configure the pwm generator for countdown mode with immediate updates to the parameters. w rite the pwm0ctl register with a value of 0x0000.0000. w rite the pwm0gena register with a value of 0x0000.008c. 51 1 september 02, 2007 preliminary lm3s8962 microcontroller w rite the pwm0genb register with a value of 0x0000.080c. 6. set the period. for a 25-khz frequency , the period = 1/25,000, or 40 microseconds. the pwm clock source is 10 mhz; the system clock divided by 2. this translates to 400 clock ticks per period. use this value to set the pwm0load register . in count-down mode, set the load field in the pwm0load register to the requested period minus one. w rite the pwm0load register with a value of 0x0000.018f . 7. set the pulse width of the pwm0 pin for a 25% duty cycle. w rite the pwm0cmp a register with a value of 0x0000.012b. 8. set the pulse width of the pwm1 pin for a 75% duty cycle. w rite the pwm0cmpb register with a value of 0x0000.0063. 9. start the timers in pwm generator 0. w rite the pwm0ctl register with a value of 0x0000.0001. 10. enable pwm outputs. w rite the pwmenable register with a value of 0x0000.0003. 19.4 register map t able 19-1 on page 512 lists the pwm registers. the of fset listed is a hexadecimal increment to the register s address, relative to the pwm base address of 0x4002.8000. t able 19-1. pwm register map see page description reset t ype name offset 515 pwm master control 0x0000.0000 r/w pwmctl 0x000 516 pwm t ime base sync 0x0000.0000 r/w pwmsync 0x004 517 pwm output enable 0x0000.0000 r/w pwmenable 0x008 518 pwm output inversion 0x0000.0000 r/w pwminver t 0x00c 519 pwm output fault 0x0000.0000 r/w pwmf aul t 0x010 520 pwm interrupt enable 0x0000.0000 r/w pwminten 0x014 521 pwm raw interrupt status 0x0000.0000 ro pwmris 0x018 522 pwm interrupt status and clear 0x0000.0000 r/w1c pwmisc 0x01c 523 pwm status 0x0000.0000 ro pwmst a tus 0x020 524 pwm0 control 0x0000.0000 r/w pwm0ctl 0x040 526 pwm0 interrupt and t rigger enable 0x0000.0000 r/w pwm0inten 0x044 528 pwm0 raw interrupt status 0x0000.0000 ro pwm0ris 0x048 529 pwm0 interrupt status and clear 0x0000.0000 r/w1c pwm0isc 0x04c september 02, 2007 512 preliminary pulse w idth modulator (pwm) see page description reset t ype name offset 530 pwm0 load 0x0000.0000 r/w pwm0load 0x050 531 pwm0 counter 0x0000.0000 ro pwm0count 0x054 532 pwm0 compare a 0x0000.0000 r/w pwm0cmp a 0x058 533 pwm0 compare b 0x0000.0000 r/w pwm0cmpb 0x05c 534 pwm0 generator a control 0x0000.0000 r/w pwm0gena 0x060 537 pwm0 generator b control 0x0000.0000 r/w pwm0genb 0x064 540 pwm0 dead-band control 0x0000.0000 r/w pwm0dbctl 0x068 541 pwm0 dead-band rising-edge delay 0x0000.0000 r/w pwm0dbrise 0x06c 542 pwm0 dead-band falling-edge-delay 0x0000.0000 r/w pwm0dbf all 0x070 524 pwm1 control 0x0000.0000 r/w pwm1ctl 0x080 526 pwm1 interrupt and t rigger enable 0x0000.0000 r/w pwm1inten 0x084 528 pwm1 raw interrupt status 0x0000.0000 ro pwm1ris 0x088 529 pwm1 interrupt status and clear 0x0000.0000 r/w1c pwm1isc 0x08c 530 pwm1 load 0x0000.0000 r/w pwm1load 0x090 531 pwm1 counter 0x0000.0000 ro pwm1count 0x094 532 pwm1 compare a 0x0000.0000 r/w pwm1cmp a 0x098 533 pwm1 compare b 0x0000.0000 r/w pwm1cmpb 0x09c 534 pwm1 generator a control 0x0000.0000 r/w pwm1gena 0x0a0 537 pwm1 generator b control 0x0000.0000 r/w pwm1genb 0x0a4 540 pwm1 dead-band control 0x0000.0000 r/w pwm1dbctl 0x0a8 541 pwm1 dead-band rising-edge delay 0x0000.0000 r/w pwm1dbrise 0x0ac 542 pwm1 dead-band falling-edge-delay 0x0000.0000 r/w pwm1dbf all 0x0b0 524 pwm2 control 0x0000.0000 r/w pwm2ctl 0x0c0 526 pwm2 interrupt and t rigger enable 0x0000.0000 r/w pwm2inten 0x0c4 528 pwm2 raw interrupt status 0x0000.0000 ro pwm2ris 0x0c8 529 pwm2 interrupt status and clear 0x0000.0000 r/w1c pwm2isc 0x0cc 530 pwm2 load 0x0000.0000 r/w pwm2load 0x0d0 531 pwm2 counter 0x0000.0000 ro pwm2count 0x0d4 532 pwm2 compare a 0x0000.0000 r/w pwm2cmp a 0x0d8 533 pwm2 compare b 0x0000.0000 r/w pwm2cmpb 0x0dc 534 pwm2 generator a control 0x0000.0000 r/w pwm2gena 0x0e0 537 pwm2 generator b control 0x0000.0000 r/w pwm2genb 0x0e4 540 pwm2 dead-band control 0x0000.0000 r/w pwm2dbctl 0x0e8 513 september 02, 2007 preliminary lm3s8962 microcontroller see page description reset t ype name offset 541 pwm2 dead-band rising-edge delay 0x0000.0000 r/w pwm2dbrise 0x0ec 542 pwm2 dead-band falling-edge-delay 0x0000.0000 r/w pwm2dbf all 0x0f0 19.5 register descriptions the remainder of this section lists and describes the pwm registers, in numerical order by address of fset. september 02, 2007 514 preliminary pulse w idth modulator (pwm) register 1: pwm master control (pwmctl), offset 0x000 this register provides master control over the pwm generation blocks. pwm master control (pwmctl) base 0x4002.8000 of fset 0x000 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 globalsync0 globalsync1 globalsync2 reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:3 update pwm generator 2 same as globalsync0 but for pwm generator 2. 0 r/w globalsync2 2 update pwm generator 1 same as globalsync0 but for pwm generator 1. 0 r/w globalsync1 1 update pwm generator 0 setting this bit causes any queued update to a load or comparator register in pwm generator 0 to be applied the next time the corresponding counter becomes zero. this bit automatically clears when the updates have completed; it cannot be cleared by software. 0 r/w globalsync0 0 515 september 02, 2007 preliminary lm3s8962 microcontroller register 2: pwm t ime base sync (pwmsync), offset 0x004 this register provides a method to perform synchronization of the counters in the pwm generation blocks. w riting a bit in this register to 1 causes the specified counter to reset back to 0; writing multiple bits resets multiple counters simultaneously . the bits auto-clear after the reset has occurred; reading them back as zero indicates that the synchronization has completed. pwm t ime base sync (pwmsync) base 0x4002.8000 of fset 0x004 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 sync0 sync1 sync2 reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:3 reset generator 2 counter performs a reset of the pwm generator 2 counter . 0 r/w sync2 2 reset generator 1 counter performs a reset of the pwm generator 1 counter . 0 r/w sync1 1 reset generator 0 counter performs a reset of the pwm generator 0 counter . 0 r/w sync0 0 september 02, 2007 516 preliminary pulse w idth modulator (pwm) register 3: pwm output enable (pwmenable), offset 0x008 this register provides a master control of which generated pwm signals are output to device pins. by disabling a pwm output, the generation process can continue (for example, when the time bases are synchronized) without driving pwm signals to the pins. when bits in this register are set, the corresponding pwm signal is passed through to the output stage, which is controlled by the pwminvert register . when bits are not set, the pwm signal is replaced by a zero value which is also passed to the output stage. pwm output enable (pwmenable) base 0x4002.8000 of fset 0x008 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pwm0en pwm1en pwm2en pwm3en pwm4en pwm5en reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:6 pwm5 output enable when set, allows the generated pwm5 signal to be passed to the device pin. 0 r/w pwm5en 5 pwm4 output enable when set, allows the generated pwm4 signal to be passed to the device pin. 0 r/w pwm4en 4 pwm3 output enable when set, allows the generated pwm3 signal to be passed to the device pin. 0 r/w pwm3en 3 pwm2 output enable when set, allows the generated pwm2 signal to be passed to the device pin. 0 r/w pwm2en 2 pwm1 output enable when set, allows the generated pwm1 signal to be passed to the device pin. 0 r/w pwm1en 1 pwm0 output enable when set, allows the generated pwm0 signal to be passed to the device pin. 0 r/w pwm0en 0 517 september 02, 2007 preliminary lm3s8962 microcontroller register 4: pwm output inversion (pwminvert), offset 0x00c this register provides a master control of the polarity of the pwm signals on the device pins. the pwm signals generated by the pwm generator are active high; they can optionally be made active low via this register . disabled pwm channels are also passed through the output inverter (if so configured) so that inactive channels maintain the correct polarity . pwm output inversion (pwminver t) base 0x4002.8000 of fset 0x00c t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pwm0inv pwm1inv pwm2inv pwm3inv pwm4inv pwm5inv reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:6 invert pwm5 signal when set, the generated pwm5 signal is inverted. 0 r/w pwm5inv 5 invert pwm4 signal when set, the generated pwm4 signal is inverted. 0 r/w pwm4inv 4 invert pwm3 signal when set, the generated pwm3 signal is inverted. 0 r/w pwm3inv 3 invert pwm2 signal when set, the generated pwm2 signal is inverted. 0 r/w pwm2inv 2 invert pwm1 signal when set, the generated pwm1 signal is inverted. 0 r/w pwm1inv 1 invert pwm0 signal when set, the generated pwm0 signal is inverted. 0 r/w pwm0inv 0 september 02, 2007 518 preliminary pulse w idth modulator (pwm) register 5: pwm output fault (pwmf aul t), offset 0x010 this register controls the behavior of the pwm outputs in the presence of fault conditions. both the fault input and debug events are considered fault conditions. on a fault condition, each pwm signal can either be passed through unmodified or driven low . for outputs that are configured for pass-through, the debug event handling on the corresponding pwm generator also determines if the pwm signal continues to be generated. fault condition control happens before the output inverter , so pwm signals driven low on fault are inverted if the channel is configured for inversion (therefore, the pin is driven high on a fault condition). pwm output fault (pwmf aul t) base 0x4002.8000 of fset 0x010 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 fault0 fault1 fault2 fault3 fault4 fault5 reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:6 pwm5 driven low on fault when set, the pwm5 output signal is driven low on a fault condition. 0 r/w fault5 5 pwm4 driven low on fault when set, the pwm4 output signal is driven low on a fault condition. 0 r/w fault4 4 pwm3 driven low on fault when set, the pwm3 output signal is driven low on a fault condition. 0 r/w fault3 3 pwm2 driven low on fault when set, the pwm2 output signal is driven low on a fault condition. 0 r/w fault2 2 pwm1 driven low on fault when set, the pwm1 output signal is driven low on a fault condition. 0 r/w fault1 1 pwm0 driven low on fault when set, the pwm0 output signal is driven low on a fault condition. 0 r/w fault0 0 519 september 02, 2007 preliminary lm3s8962 microcontroller register 6: pwm interrupt enable (pwminten), offset 0x014 this register controls the global interrupt generation capabilities of the pwm module. the events that can cause an interrupt are the fault input and the individual interrupts from the pwm generators. pwm interrupt enable (pwminten) base 0x4002.8000 of fset 0x014 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 intfault reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 intpwm0 intpwm1 intpwm2 reserved r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:17 fault interrupt enable when 1, an interrupt occurs when the fault input is asserted. 0 r/w intfault 16 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 15:3 pwm2 interrupt enable when 1, an interrupt occurs when the pwm generator 2 block asserts an interrupt. 0 r/w intpwm2 2 pwm1 interrupt enable when 1, an interrupt occurs when the pwm generator 1 block asserts an interrupt. 0 r/w intpwm1 1 pwm0 interrupt enable when 1, an interrupt occurs when the pwm generator 0 block asserts an interrupt. 0 r/w intpwm0 0 september 02, 2007 520 preliminary pulse w idth modulator (pwm) register 7: pwm raw interrupt status (pwmris), offset 0x018 this register provides the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller . the fault interrupt is latched on detection; it must be cleared through the pwm interrupt status and clear (pwmisc) register (see page 522 ). the pwm generator interrupts simply reflect the status of the pwm generators; they are cleared via the interrupt status register in the pwm generator blocks. bits set to 1 indicate the events that are active; a zero bit indicates that the event in question is not active. pwm raw interrupt status (pwmris) base 0x4002.8000 of fset 0x018 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 intfault reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 intpwm0 intpwm1 intpwm2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:17 fault interrupt asserted indicates that the fault input has been asserted. 0 ro intfault 16 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 15:3 pwm2 interrupt asserted indicates that the pwm generator 2 block is asserting its interrupt. 0 ro intpwm2 2 pwm1 interrupt asserted indicates that the pwm generator 1 block is asserting its interrupt. 0 ro intpwm1 1 pwm0 interrupt asserted indicates that the pwm generator 0 block is asserting its interrupt. 0 ro intpwm0 0 521 september 02, 2007 preliminary lm3s8962 microcontroller register 8: pwm interrupt status and clear (pwmisc), offset 0x01c this register provides a summary of the interrupt status of the individual pwm generator blocks. a bit set to 1 indicates that the corresponding generator block is asserting an interrupt. the individual interrupt status registers in each block must be consulted to determine the reason for the interrupt, and used to clear the interrupt. for the fault interrupt, a write of 1 to that bit position clears the latched interrupt status. pwm interrupt status and clear (pwmisc) base 0x4002.8000 of fset 0x01c t ype r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 intfault reserved r/w1c ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 intpwm0 intpwm1 intpwm2 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:17 fault interrupt asserted indicates if the fault input is asserting an interrupt. 0 r/w1c intfault 16 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 15:3 pwm2 interrupt status indicates if the pwm generator 2 block is asserting an interrupt. 0 ro intpwm2 2 pwm1 interrupt status indicates if the pwm generator 1 block is asserting an interrupt. 0 ro intpwm1 1 pwm0 interrupt status indicates if the pwm generator 0 block is asserting an interrupt. 0 ro intpwm0 0 september 02, 2007 522 preliminary pulse w idth modulator (pwm) register 9: pwm status (pwmst a tus), offset 0x020 this register provides the status of the fault input signal. pwm status (pwmst a tus) base 0x4002.8000 of fset 0x020 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 fault reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 fault interrupt status when set to 1, indicates the fault input is asserted. 0 ro fault 0 523 september 02, 2007 preliminary lm3s8962 microcontroller register 10: pwm0 control (pwm0ctl), offset 0x040 register 1 1: pwm1 control (pwm1ctl), offset 0x080 register 12: pwm2 control (pwm2ctl), offset 0x0c0 these registers configure the pwm signal generation blocks (pwm0ctl controls the pwm generator 0 block, and so on). the register update mode, debug mode, counting mode, and block enable mode are all controlled via these registers. the blocks produce the pwm signals, which can be either two independent pwm signals (from the same counter), or a paired set of pwm signals with dead-band delays added. the pwm0 block produces the pwm0 and pwm1 outputs, the pwm1 block produces the pwm2 and pwm3 outputs, and the pwm2 block produces the pwm4 and pwm5 outputs. pwm0 control (pwm0ctl) base 0x4002.8000 of fset 0x040 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 enable mode debug loadupd cmpaupd cmpbupd reserved r/w r/w r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:6 comparator b update mode same as cmpaupd but for the comparator b register . 0 r/w cmpbupd 5 comparator a update mode the update mode for the comparator a register . if 0, updates to the register are reflected to the comparator the next time the counter is 0. if 1, updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 515 ). 0 r/w cmpaupd 4 load register update mode the update mode for the load register . if 0, updates to the register are reflected to the counter the next time the counter is 0. if 1, updates to the register are delayed until the next time the counter is 0 after a synchronous update has been requested through the pwm master control (pwmctl) register . 0 r/w loadupd 3 debug mode the behavior of the counter in debug mode. if 0, the counter stops running when it next reaches 0, and continues running again when no longer in debug mode. if 1, the counter always runs. 0 r/w debug 2 september 02, 2007 524 preliminary pulse w idth modulator (pwm) description reset t ype name bit/field counter mode the mode for the counter . if 0, the counter counts down from the load value to 0 and then wraps back to the load value (count-down mode). if 1, the counter counts up from 0 to the load value, back down to 0, and then repeats (count-up/down mode). 0 r/w mode 1 pwm block enable master enable for the pwm generation block. if 0, the entire block is disabled and not clocked. if 1, the block is enabled and produces pwm signals. 0 r/w enable 0 525 september 02, 2007 preliminary lm3s8962 microcontroller register 13: pwm0 interrupt and t rigger enable (pwm0inten), offset 0x044 register 14: pwm1 interrupt and t rigger enable (pwm1inten), offset 0x084 register 15: pwm2 interrupt and t rigger enable (pwm2inten), offset 0x0c4 these registers control the interrupt and adc trigger generation capabilities of the pwm generators ( pwm0inten controls the pwm generator 0 block, and so on). the events that can cause an interrupt or an adc trigger are: the counter being equal to the load register the counter being equal to zero the counter being equal to the comparator a register while counting up the counter being equal to the comparator a register while counting down the counter being equal to the comparator b register while counting up the counter being equal to the comparator b register while counting down any combination of these events can generate either an interruptor an adc trigger , though no determination can be made as to the actual event that caused an adc trigger if more than one is specified. pwm0 interrupt and t rigger enable (pwm0inten) base 0x4002.8000 of fset 0x044 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd reserved t rcntzero t rcntload t rcmpau t rcmpad t rcmpbu t rcmpbd reserved r/w r/w r/w r/w r/w r/w ro ro r/w r/w r/w r/w r/w r/w ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:14 t rigger for counter=comparator b down when 1, a trigger pulse is output when the counter matches the comparator b value and the counter is counting down. 0 r/w t rcmpbd 13 t rigger for counter=comparator b up when 1, a trigger pulse is output when the counter matches the comparator b value and the counter is counting up. 0 r/w t rcmpbu 12 t rigger for counter=comparator a down when 1, a trigger pulse is output when the counter matches the comparator a value and the counter is counting down. 0 r/w t rcmpad 1 1 september 02, 2007 526 preliminary pulse w idth modulator (pwm) description reset t ype name bit/field t rigger for counter=comparator a up when 1, a trigger pulse is output when the counter matches the comparator a value and the counter is counting up. 0 r/w t rcmpau 10 t rigger for counter=load when 1, a trigger pulse is output when the counter matches the pwmnload register . 0 r/w t rcntload 9 t rigger for counter=0 when 1, a trigger pulse is output when the counter is 0. 0 r/w t rcntzero 8 software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x0 ro reserved 7:6 interrupt for counter=comparator b down when 1, an interrupt occurs when the counter matches the comparator b value and the counter is counting down. 0 r/w intcmpbd 5 interrupt for counter=comparator b up when 1, an interrupt occurs when the counter matches the comparator b value and the counter is counting up. 0 r/w intcmpbu 4 interrupt for counter=comparator a down when 1, an interrupt occurs when the counter matches the comparator a value and the counter is counting down. 0 r/w intcmpad 3 interrupt for counter=comparator a up when 1, an interrupt occurs when the counter matches the comparator a value and the counter is counting up. 0 r/w intcmpau 2 interrupt for counter=load when 1, an interrupt occurs when the counter matches the pwmnload register . 0 r/w intcntload 1 interrupt for counter=0 when 1, an interrupt occurs when the counter is 0. 0 r/w intcntzero 0 527 september 02, 2007 preliminary lm3s8962 microcontroller register 16: pwm0 raw interrupt status (pwm0ris), offset 0x048 register 17: pwm1 raw interrupt status (pwm1ris), offset 0x088 register 18: pwm2 raw interrupt status (pwm2ris), offset 0x0c8 these registers provide the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller ( pwm0ris controls the pwm generator 0 block, and so on). bits set to 1 indicate the latched events that have occurred; a 0 bit indicates that the event in question has not occurred. pwm0 raw interrupt status (pwm0ris) base 0x4002.8000 of fset 0x048 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:6 comparator b down interrupt status indicates that the counter has matched the comparator b value while counting down. 0 ro intcmpbd 5 comparator b up interrupt status indicates that the counter has matched the comparator b value while counting up. 0 ro intcmpbu 4 comparator a down interrupt status indicates that the counter has matched the comparator a value while counting down. 0 ro intcmpad 3 comparator a up interrupt status indicates that the counter has matched the comparator a value while counting up. 0 ro intcmpau 2 counter=load interrupt status indicates that the counter has matched the pwmnload register . 0 ro intcntload 1 counter=0 interrupt status indicates that the counter has matched 0. 0 ro intcntzero 0 september 02, 2007 528 preliminary pulse w idth modulator (pwm) register 19: pwm0 interrupt status and clear (pwm0isc), offset 0x04c register 20: pwm1 interrupt status and clear (pwm1isc), offset 0x08c register 21: pwm2 interrupt status and clear (pwm2isc), offset 0x0cc these registers provide the current set of interrupt sources that are asserted to the controller ( pwm0isc controls the pwm generator 0 block, and so on). bits set to 1 indicate the latched events that have occurred; a 0 bit indicates that the event in question has not occurred. these are r/w1c registers; writing a 1 to a bit position clears the corresponding interrupt reason. pwm0 interrupt status and clear (pwm0isc) base 0x4002.8000 of fset 0x04c t ype r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd reserved r/w1c r/w1c r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:6 comparator b down interrupt indicates that the counter has matched the comparator b value while counting down. 0 r/w1c intcmpbd 5 comparator b up interrupt indicates that the counter has matched the comparator b value while counting up. 0 r/w1c intcmpbu 4 comparator a down interrupt indicates that the counter has matched the comparator a value while counting down. 0 r/w1c intcmpad 3 comparator a up interrupt indicates that the counter has matched the comparator a value while counting up. 0 r/w1c intcmpau 2 counter=load interrupt indicates that the counter has matched the pwmnload register . 0 r/w1c intcntload 1 counter=0 interrupt indicates that the counter has matched 0. 0 r/w1c intcntzero 0 529 september 02, 2007 preliminary lm3s8962 microcontroller register 22: pwm0 load (pwm0load), offset 0x050 register 23: pwm1 load (pwm1load), offset 0x090 register 24: pwm2 load (pwm2load), offset 0x0d0 these registers contain the load value for the pwm counter ( pwm0load controls the pwm generator 0 block, and so on). based on the counter mode, either this value is loaded into the counter after it reaches zero, or it is the limit of up-counting after which the counter decrements back to zero. if the load v alue update mode is immediate, this value is used the next time the counter reaches zero; if the mode is synchronous, it is used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 515 ). if this register is re-written before the actual update occurs, the previous value is never used and is lost. pwm0 load (pwm0load) base 0x4002.8000 of fset 0x050 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 load r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:16 counter load v alue the counter load value. 0 r/w load 15:0 september 02, 2007 530 preliminary pulse w idth modulator (pwm) register 25: pwm0 counter (pwm0count), offset 0x054 register 26: pwm1 counter (pwm1count), offset 0x094 register 27: pwm2 counter (pwm2count), offset 0x0d4 these registers contain the current value of the pwm counter ( pwm0count is the value of the pwm generator 0 block, and so on). when this value matches the load register , a pulse is output; this can drive the generation of a pwm signal (via the pwmngena/pwmngenb registers, see page 534 and page 537 ) or drive an interrupt or adc trigger (via the pwmninten register , see page 526 ). a pulse with the same capabilities is generated when this value is zero. pwm0 counter (pwm0count) base 0x4002.8000 of fset 0x054 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 count ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:16 counter v alue the current value of the counter . 0x00 ro count 15:0 531 september 02, 2007 preliminary lm3s8962 microcontroller register 28: pwm0 compare a (pwm0cmp a), offset 0x058 register 29: pwm1 compare a (pwm1cmp a), offset 0x098 register 30: pwm2 compare a (pwm2cmp a), offset 0x0d8 these registers contain a value to be compared against the counter ( pwm0cmp a controls the pwm generator 0 block, and so on). when this value matches the counter , a pulse is output; this can drive the generation of a pwm signal (via the pwmngena/pwmngenb registers) or drive an interrupt or adc trigger (via the pwmninten register). if the value of this register is greater than the pwmnload register (see page 530 ), then no pulse is ever output. if the comparator a update mode is immediate (based on the cmpaupd bit in the pwmnctl register), then this 16-bit compa value is used the next time the counter reaches zero. if the update mode is synchronous, it is used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 515 ). if this register is rewritten before the actual update occurs, the previous value is never used and is lost. pwm0 compare a (pwm0cmp a) base 0x4002.8000 of fset 0x058 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 compa r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:16 comparator a v alue the value to be compared against the counter . 0x00 r/w compa 15:0 september 02, 2007 532 preliminary pulse w idth modulator (pwm) register 31: pwm0 compare b (pwm0cmpb), offset 0x05c register 32: pwm1 compare b (pwm1cmpb), offset 0x09c register 33: pwm2 compare b (pwm2cmpb), offset 0x0dc these registers contain a value to be compared against the counter ( pwm0cmpb controls the pwm generator 0 block, and so on). when this value matches the counter , a pulse is output; this can drive the generation of a pwm signal (via the pwmngena/pwmngenb registers) or drive an interrupt or adc trigger (via the pwmninten register). if the value of this register is greater than the pwmnload register , then no pulse is ever output. if the comparator b update mode is immediate (based on the cmpbupd bit in the pwmnctl register), then this 16-bit compb value is used the next time the counter reaches zero. if the update mode is synchronous, it is used the next time the counter reaches zero after a synchronous update has been requested through the pwm master control (pwmctl) register (see page 515 ). if this register is rewritten before the actual update occurs, the previous value is never used and is lost. pwm0 compare b (pwm0cmpb) base 0x4002.8000 of fset 0x05c t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 compb r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:16 comparator b v alue the value to be compared against the counter . 0x00 r/w compb 15:0 533 september 02, 2007 preliminary lm3s8962 microcontroller register 34: pwm0 generator a control (pwm0gena), offset 0x060 register 35: pwm1 generator a control (pwm1gena), offset 0x0a0 register 36: pwm2 generator a control (pwm2gena), offset 0x0e0 these registers control the generation of the pwmna signal based on the load and zero output pulses from the counter , as well as the compare a and compare b pulses from the comparators ( pwm0gena controls the pwm generator 0 block, and so on). when the counter is running in count-down mode, only four of these events occur; when running in count-up/down mode, all six occur . these events provide great flexibility in the positioning and duty cycle of the pwm signal that is produced. the pwm0gena register controls generation of the pwm0a signal; pwm1gena , the pwm1a signal; and pwm2gena , the pwm2a signal. if a zero or load event coincides with a compare a or compare b event, the zero or load action is taken and the compare a or compare b action is ignored. if a compare a event coincides with a compare b event, the compare a action is taken and the compare b action is ignored. pwm0 generator a control (pwm0gena) base 0x4002.8000 of fset 0x060 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 actzero actload actcmpau actcmpad actcmpbu actcmpbd reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:12 action for comparator b down the action to be taken when the counter matches comparator b while counting down. the table below defines the ef fect of the event on the output signal. description v alue do nothing. 0x0 invert the output signal. 0x1 set the output signal to 0. 0x2 set the output signal to 1. 0x3 0x0 r/w actcmpbd 1 1:10 september 02, 2007 534 preliminary pulse w idth modulator (pwm) description reset t ype name bit/field action for comparator b up the action to be taken when the counter matches comparator b while counting up. occurs only when the mode bit in the pwmnctl register (see page 524 ) is set to 1. the table below defines the ef fect of the event on the output signal. description v alue do nothing. 0x0 invert the output signal. 0x1 set the output signal to 0. 0x2 set the output signal to 1. 0x3 0x0 r/w actcmpbu 9:8 action for comparator a down the action to be taken when the counter matches comparator a while counting down. the table below defines the ef fect of the event on the output signal. description v alue do nothing. 0x0 invert the output signal. 0x1 set the output signal to 0. 0x2 set the output signal to 1. 0x3 0x0 r/w actcmpad 7:6 action for comparator a up the action to be taken when the counter matches comparator a while counting up. occurs only when the mode bit in the pwmnctl register is set to 1. the table below defines the ef fect of the event on the output signal. description v alue do nothing. 0x0 invert the output signal. 0x1 set the output signal to 0. 0x2 set the output signal to 1. 0x3 0x0 r/w actcmpau 5:4 action for counter=load the action to be taken when the counter matches the load value. the table below defines the ef fect of the event on the output signal. description v alue do nothing. 0x0 invert the output signal. 0x1 set the output signal to 0. 0x2 set the output signal to 1. 0x3 0x0 r/w actload 3:2 535 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field action for counter=0 the action to be taken when the counter is zero. the table below defines the ef fect of the event on the output signal. description v alue do nothing. 0x0 invert the output signal. 0x1 set the output signal to 0. 0x2 set the output signal to 1. 0x3 0x0 r/w actzero 1:0 september 02, 2007 536 preliminary pulse w idth modulator (pwm) register 37: pwm0 generator b control (pwm0genb), offset 0x064 register 38: pwm1 generator b control (pwm1genb), offset 0x0a4 register 39: pwm2 generator b control (pwm2genb), offset 0x0e4 these registers control the generation of the pwmnb signal based on the load and zero output pulses from the counter , as well as the compare a and compare b pulses from the comparators ( pwm0genb controls the pwm generator 0 block, and so on). when the counter is running in down mode, only four of these events occur; when running in up/down mode, all six occur . these events provide great flexibility in the positioning and duty cycle of the pwm signal that is produced. the pwm0genb register controls generation of the pwm0b signal; pwm1genb , the pwm1b signal; and pwm2genb , the pwm2b signal. if a zero or load event coincides with a compare a or compare b event, the zero or load action is taken and the compare a or compare b action is ignored. if a compare a event coincides with a compare b event, the compare b action is taken and the compare a action is ignored. pwm0 generator b control (pwm0genb) base 0x4002.8000 of fset 0x064 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 actzero actload actcmpau actcmpad actcmpbu actcmpbd reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:12 action for comparator b down the action to be taken when the counter matches comparator b while counting down. the table below defines the ef fect of the event on the output signal. description v alue do nothing. 0x0 invert the output signal. 0x1 set the output signal to 0. 0x2 set the output signal to 1. 0x3 0x0 r/w actcmpbd 1 1:10 537 september 02, 2007 preliminary lm3s8962 microcontroller description reset t ype name bit/field action for comparator b up the action to be taken when the counter matches comparator b while counting up. occurs only when the mode bit in the pwmnctl register is set to 1. the table below defines the ef fect of the event on the output signal. description v alue do nothing. 0x0 invert the output signal. 0x1 set the output signal to 0. 0x2 set the output signal to 1. 0x3 0x0 r/w actcmpbu 9:8 action for comparator a down the action to be taken when the counter matches comparator a while counting down. the table below defines the ef fect of the event on the output signal. description v alue do nothing. 0x0 invert the output signal. 0x1 set the output signal to 0. 0x2 set the output signal to 1. 0x3 0x0 r/w actcmpad 7:6 action for comparator a up the action to be taken when the counter matches comparator a while counting up. occurs only when the mode bit in the pwmnctl register is set to 1. the table below defines the ef fect of the event on the output signal. description v alue do nothing. 0x0 invert the output signal. 0x1 set the output signal to 0. 0x2 set the output signal to 1. 0x3 0x0 r/w actcmpau 5:4 action for counter=load the action to be taken when the counter matches the load value. the table below defines the ef fect of the event on the output signal. description v alue do nothing. 0x0 invert the output signal. 0x1 set the output signal to 0. 0x2 set the output signal to 1. 0x3 0x0 r/w actload 3:2 september 02, 2007 538 preliminary pulse w idth modulator (pwm) description reset t ype name bit/field action for counter=0 the action to be taken when the counter is 0. the table below defines the ef fect of the event on the output signal. description v alue do nothing. 0x0 invert the output signal. 0x1 set the output signal to 0. 0x2 set the output signal to 1. 0x3 0x0 r/w actzero 1:0 539 september 02, 2007 preliminary lm3s8962 microcontroller register 40: pwm0 dead-band control (pwm0dbctl), offset 0x068 register 41: pwm1 dead-band control (pwm1dbctl), offset 0x0a8 register 42: pwm2 dead-band control (pwm2dbctl), offset 0x0e8 the pwm0dbctl register controls the dead-band generator , which produces the pwm0 and pwm1 signals based on the pwm0a and pwm0b signals. when disabled, the pwm0a signal passes through to the pwm0 signal and the pwm0b signal passes through to the pwm1 signal. when enabled and inverting the resulting waveform, the pwm0b signal is ignored; the pwm0 signal is generated by delaying the rising edge(s) of the pwm0a signal by the value in the pwm0dbrise register (see page 541 ), and the pwm1 signal is generated by delaying the falling edge(s) of the pwm0a signal by the value in the pwm0dbf all register (see page 542 ). in a similar manner , pwm2 and pwm3 are produced from the pwm1a and pwm1b signals, and pwm4 and pwm5 are produced from the pwm2a and pwm2b signals. pwm0 dead-band control (pwm0dbctl) base 0x4002.8000 of fset 0x068 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 enable reserved r/w ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:1 dead-band generator enable when set, the dead-band generator inserts dead bands into the output signals; when clear , it simply passes the pwm signals through. 0 r/w enable 0 september 02, 2007 540 preliminary pulse w idth modulator (pwm) register 43: pwm0 dead-band rising-edge delay (pwm0dbrise), offset 0x06c register 44: pwm1 dead-band rising-edge delay (pwm1dbrise), offset 0x0ac register 45: pwm2 dead-band rising-edge delay (pwm2dbrise), offset 0x0ec the pwm0dbrise register contains the number of clock ticks to delay the rising edge of the pwm0a signal when generating the pwm0 signal. if the dead-band generator is disabled through the pwmndbctl register , the pwm0dbrise register is ignored. if the value of this register is larger than the width of a high pulse on the input pwm signal, the rising-edge delay consumes the entire high time of the signal, resulting in no high time on the output. care must be taken to ensure that the input high time always exceeds the rising-edge delay . in a similar manner , pwm2 is generated from pwm1a with its rising edge delayed and pwm4 is produced from pwm2a with its rising edge delayed. pwm0 dead-band rising-edge delay (pwm0dbrise) base 0x4002.8000 of fset 0x06c t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 risedelay reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:12 dead-band rise delay the number of clock ticks to delay the rising edge. 0 r/w risedelay 1 1:0 541 september 02, 2007 preliminary lm3s8962 microcontroller register 46: pwm0 dead-band falling-edge-delay (pwm0dbf all), offset 0x070 register 47: pwm1 dead-band falling-edge-delay (pwm1dbf all), offset 0x0b0 register 48: pwm2 dead-band falling-edge-delay (pwm2dbf all), offset 0x0f0 the pwm0dbf all register contains the number of clock ticks to delay the falling edge of the pwm0a signal when generating the pwm1 signal. if the dead-band generator is disabled, this register is ignored. if the value of this register is larger than the width of a low pulse on the input pwm signal, the falling-edge delay consumes the entire low time of the signal, resulting in no low time on the output. care must be taken to ensure that the input low time always exceeds the falling-edge delay . in a similar manner , pwm3 is generated from pwm1a with its falling edge delayed and pwm5 is produced from pwm2a with its falling edge delayed. pwm0 dead-band falling-edge-delay (pwm0dbf all) base 0x4002.8000 of fset 0x070 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 falldelay reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:12 dead-band fall delay the number of clock ticks to delay the falling edge. 0x00 r/w falldelay 1 1:0 september 02, 2007 542 preliminary pulse w idth modulator (pwm) 20 quadrature encoder interface (qei) a quadrature encoder , also known as a 2-channel incremental encoder , converts linear displacement into a pulse signal. by monitoring both the number of pulses and the relative phase of the two signals, you can track the position, direction of rotation, and speed. in addition, a third channel, or index signal, can be used to reset the position counter . the lm3s8962 microcontroller includes two quadrature encoder interface (qei) modules. each qei module interprets the code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. in addition, it can capture a running estimate of the velocity of the encoder wheel. each stellaris ? quadrature encoder has the following features: position integrator that tracks the encoder position v elocity capture using built-in timer interrupt generation on: C index pulse C v elocity-timer expiration C direction change C quadrature error detection 20.1 block diagram figure 20-1 on page 544 provides a block diagram of a stellaris ? qei module. 543 september 02, 2007 preliminary lm3s8962 microcontroller figure 20-1. qei block diagram 20.2 functional description the qei module interprets the two-bit gray code produced by a quadrature encoder wheel to integrate position over time and determine direction of rotation. in addition, it can capture a running estimate of the velocity of the encoder wheel. the position integrator and velocity capture can be independently enabled, though the position integrator must be enabled before the velocity capture can be enabled. the two phase signals, pha and phb , can be swapped before being interpreted by the qei module to change the meaning of forward and backward, and to correct for miswiring of the system. alternatively , the phase signals can be interpreted as a clock and direction signal as output by some encoders. the qei module supports two modes of signal operation: quadrature phase mode and clock/direction mode. in quadrature phase mode, the encoder produces two clocks that are 90 degrees out of phase; the edge relationship is used to determine the direction of rotation. in clock/direction mode, the encoder produces a clock signal to indicate steps and a direction signal to indicate the direction of rotation. this mode is determined by the sigmode bit of the qei control (qeictl) register (see page 548 ). when the qei module is set to use the quadrature phase mode ( sigmode bit equals zero), the capture mode for the position integrator can be set to update the position counter on every edge of the pha signal or to update on every edge of both pha and phb . updating the position counter on every pha and phb provides more positional resolution at the cost of less range in the positional counter . when edges on pha lead edges on phb , the position counter is incremented. when edges on phb lead edges on pha , the position counter is decremented. when a rising and falling edge pair is seen on one of the phases without any edges on the other , the direction of rotation has changed. september 02, 2007 544 preliminary quadrature encoder interface (qei) q u a d r a t u r e encoder v elocity predivider interr upt control qeiinten qeiris qeiisc p osition integ r ator qeimaxpos qeipos v e l o c i t y a c c u m u l a t o r qeicount qeispeed v elocity t imer qeilo ad qeitime pha phb idx clk dir interr upt control & status qeictl qeist a t the positional counter is automatically reset on one of two conditions: sensing the index pulse or reaching the maximum position value. which mode is determined by the resmode bit of the qei control (qeictl) register . when resmode is 0, the positional counter is reset when the index pulse is sensed. this limits the positional counter to the values [0:n-1], where n is the number of phase edges in a full revolution of the encoder wheel. the qeimaxpos register must be programmed with n-1 so that the reverse direction from position 0 can move the position counter to n-1. in this mode, the position register contains the absolute position of the encoder relative to the index (or home) position once an index pulse has been seen. when resmode is 1, the positional counter is constrained to the range [0:m], where m is the programmable maximum value. the index pulse is ignored by the positional counter in this mode. the velocity capture has a configurable timer and a count register . it counts the number of phase edges (using the same configuration as for the position integrator) in a given time period. the edge count from the previous time period is available to the controller via the qeispeed register , while the edge count for the current time period is being accumulated in the qeicount register . as soon as the current time period is complete, the total number of edges counted in that time period is made available in the qeispeed register (losing the previous value), the qeicount is reset to 0, and counting commences on a new time period. the number of edges counted in a given time period is directly proportional to the velocity of the encoder . figure 20-2 on page 545 shows how the stellaris ? quadrature encoder converts the phase input signals into clock pulses, the direction signal, and how the velocity predivider operates (in divide by 4 mode). figure 20-2. quadrature encoder and v elocity predivider operation the period of the timer is configurable by specifying the load value for the timer in the qeiload register . when the timer reaches zero, an interrupt can be triggered, and the hardware reloads the timer with the qeiload value and continues to count down. at lower encoder speeds, a longer timer period is needed to be able to capture enough edges to have a meaningful result. at higher encoder speeds, both a shorter timer period and/or the velocity predivider can be used. the following equation converts the velocity counter value into an rpm value: rpm = (clock * (2 ^ veldiv) * speed * 60) (load * ppr * edges) where: clock is the controller clock rate ppr is the number of pulses per revolution of the physical encoder edges is 2 or 4, based on the capture mode set in the qeictl register (2 for capmode set to 0 and 4 for capmode set to 1) for example, consider a motor running at 600 rpm. a 2048 pulse per revolution quadrature encoder is attached to the motor , producing 8192 phase edges per revolution. with a velocity predivider of 545 september 02, 2007 preliminary lm3s8962 microcontroller -1 -1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 +1 +1 +1 +1 +1 +1 +1 +1 ph a phb clk clkdiv dir pos rel 1 ( veldiv set to 0) and clocking on both pha and phb edges, this results in 81,920 pulses per second (the motor turns 10 times per second). if the timer were clocked at 10,000 hz, and the load value was 2,500 (? of a second), it would count 20,480 pulses per update. using the above equation: rpm = (10000 * 1 * 20480 * 60) (2500 * 2048 * 4) = 600 rpm now , consider that the motor is sped up to 3000 rpm. this results in 409,600 pulses per second, or 102,400 every ? of a second. again, the above equation gives: rpm = (10000 * 1 * 102400 * 60) (2500 * 2048 * 4) = 3000 rpm care must be taken when evaluating this equation since intermediate values may exceed the capacity of a 32-bit integer . in the above examples, the clock is 10,000 and the divider is 2,500; both could be predivided by 100 (at compile time if they are constants) and therefore be 100 and 25. in fact, if they were compile-time constants, they could also be reduced to a simple multiply by 4, cancelled by the 4 for the edge-count factor . important: reducing constant factors at compile time is the best way to control the intermediate values of this equation, as well as reducing the processing requirement of computing this equation. the division can be avoided by selecting a timer load value such that the divisor is a power of 2; a simple shift can therefore be done in place of the division. for encoders with a power of 2 pulses per revolution, this is a simple matter of selecting a power of 2 load value. for other encoders, a load value must be selected such that the product is very close to a power of two. for example, a 100 pulse per revolution encoder could use a load value of 82, resulting in 32,800 as the divisor , which is 0.09% above 2 14 ; in this case a shift by 15 would be an adequate approximation of the divide in most cases. if absolute accuracy were required, the controller s divide instruction could be used. the qei module can produce a controller interrupt on several events: phase error , direction change, reception of the index pulse, and expiration of the velocity timer . standard masking, raw interrupt status, interrupt status, and interrupt clear capabilities are provided. 20.3 initialization and configuration the following example shows how to configure the quadrature encoder module to read back an absolute position: 1. enable the qei clock by writing a value of 0x0000.0100 to the rcgc1 register in the system control module. 2. enable the clock to the appropriate gpio module via the rcgc2 register in the system control module. 3. in the gpio module, enable the appropriate pins for their alternate function using the gpioafsel register . 4. configure the quadrature encoder to capture edges on both signals and maintain an absolute position by resetting on index pulses. using a 1000-line encoder at four edges per line, there are 4000 pulses per revolution; therefore, set the maximum position to 3999 (0xf9f) since the count is zero-based. w rite the qeictl register with the value of 0x0000.0018. september 02, 2007 546 preliminary quadrature encoder interface (qei) w rite the qeimaxpos register with the value of 0x0000.0f9f . 5. enable the quadrature encoder by setting bit 0 of the qeictl register . 6. delay for some time. 7. read the encoder position by reading the qeipos register value. 20.4 register map t able 20-1 on page 547 lists the qei registers. the of fset listed is a hexadecimal increment to the register s address, relative to the module s base address: qei0: 0x4002.c000 qei1: 0x4002.d000 t able 20-1. qei register map see page description reset t ype name offset 548 qei control 0x0000.0000 r/w qeictl 0x000 550 qei status 0x0000.0000 ro qeist a t 0x004 551 qei position 0x0000.0000 r/w qeipos 0x008 552 qei maximum position 0x0000.0000 r/w qeimaxpos 0x00c 553 qei t imer load 0x0000.0000 r/w qeiload 0x010 554 qei t imer 0x0000.0000 ro qeitime 0x014 555 qei v elocity counter 0x0000.0000 ro qeicount 0x018 556 qei v elocity 0x0000.0000 ro qeispeed 0x01c 557 qei interrupt enable 0x0000.0000 r/w qeiinten 0x020 558 qei raw interrupt status 0x0000.0000 ro qeiris 0x024 559 qei interrupt status and clear 0x0000.0000 r/w1c qeiisc 0x028 20.5 register descriptions the remainder of this section lists and describes the qei registers, in numerical order by address of fset. 547 september 02, 2007 preliminary lm3s8962 microcontroller register 1: qei control (qeictl), offset 0x000 this register contains the configuration of the qei module. separate enables are provided for the quadrature encoder and the velocity capture blocks; the quadrature encoder must be enabled in order to capture the velocity , but the velocity does not need to be captured in applications that do not need it. the phase signal interpretation, phase swap, position update mode, position reset mode, and velocity predivider are all set via this register . qei control (qeictl) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 of fset 0x000 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 enable swap sigmode capmode resmode v elen v eldiv inv a invb invi st allen reserved r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:13 stall qei when set, the qei stalls when the microcontroller asserts halt. 0 r/w st allen 12 invert index pulse when set , the input index pulse is inverted. 0 r/w invi 1 1 invert phb when set, the phb input is inverted. 0 r/w invb 10 invert pha when set, the pha input is inverted. 0 r/w inv a 9 predivide v elocity a predivider of the input quadrature pulses before being applied to the qeicount accumulator . this field can be set to the following values: predivider v alue 1 0x0 2 0x1 4 0x2 8 0x3 16 0x4 32 0x5 64 0x6 128 0x7 0x0 r/w v eldiv 8:6 september 02, 2007 548 preliminary quadrature encoder interface (qei) description reset t ype name bit/field capture v elocity when set, enables capture of the velocity of the quadrature encoder . 0 r/w v elen 5 reset mode the reset mode for the position counter . when 0, the position counter is reset when it reaches the maximum; when 1, the position counter is reset when the index pulse is captured. 0 r/w resmode 4 capture mode the capture mode defines the phase edges that are counted in the position. when 0, only the pha edges are counted; when 1, the pha and phb edges are counted, providing twice the positional resolution but half the range. 0 r/w capmode 3 signal mode when 1, the pha and phb signals are clock and direction; when 0, they are quadrature phase signals. 0 r/w sigmode 2 swap signals swaps the pha and phb signals. 0 r/w swap 1 enable qei enables the quadrature encoder module. 0 r/w enable 0 549 september 02, 2007 preliminary lm3s8962 microcontroller register 2: qei status (qeist a t), offset 0x004 this register provides status about the operation of the qei module. qei status (qeist a t) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 of fset 0x004 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 error direction reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:2 direction of rotation indicates the direction the encoder is rotating. the direction values are defined as follows: description v alue forward rotation 0 reverse rotation 1 0 ro direction 1 error detected indicates that an error was detected in the gray code sequence (that is, both signals changing at the same time). 0 ro error 0 september 02, 2007 550 preliminary quadrature encoder interface (qei) register 3: qei position (qeipos), offset 0x008 this register contains the current value of the position integrator . its value is updated by inputs on the qei phase inputs, and can be set to a specific value by writing to it. qei position (qeipos) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 of fset 0x008 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 position r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 position r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field current position integrator v alue the current value of the position integrator . 0x00 r/w position 31:0 551 september 02, 2007 preliminary lm3s8962 microcontroller register 4: qei maximum position (qeimaxpos), offset 0x00c this register contains the maximum value of the position integrator . when moving forward, the position register resets to zero when it increments past this value. when moving backward, the position register resets to this value when it decrements from zero. qei maximum position (qeimaxpos) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 of fset 0x00c t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 maxpos r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 maxpos r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field maximum position integrator v alue the maximum value of the position integrator . 0x00 r/w maxpos 31:0 september 02, 2007 552 preliminary quadrature encoder interface (qei) register 5: qei t imer load (qeiload), offset 0x010 this register contains the load value for the velocity timer . since this value is loaded into the timer the clock cycle after the timer is zero, this value should be one less than the number of clocks in the desired period. so, for example, to have 2000 clocks per timer period, this register should contain 1999. qei t imer load (qeiload) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 of fset 0x010 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 load r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 load r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field v elocity t imer load v alue the load value for the velocity timer . 0x00 r/w load 31:0 553 september 02, 2007 preliminary lm3s8962 microcontroller register 6: qei t imer (qeitime), offset 0x014 this register contains the current value of the velocity timer . this counter does not increment when velen in qeictl is 0. qei t imer (qeitime) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 of fset 0x014 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 t ime ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 t ime ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field v elocity t imer current v alue the current value of the velocity timer . 0x00 ro t ime 31:0 september 02, 2007 554 preliminary quadrature encoder interface (qei) register 7: qei v elocity counter (qeicount), offset 0x018 this register contains the running count of velocity pulses for the current time period. since this is a running total, the time period to which it applies cannot be known with precision (that is, a read of this register does not necessarily correspond to the time returned by the qeitime register since there is a small window of time between the two reads, during which time either value may have changed). the qeispeed register should be used to determine the actual encoder velocity; this register is provided for information purposes only . this counter does not increment when velen in qeictl is 0. qei v elocity counter (qeicount) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 of fset 0x018 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 count ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 count ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field v elocity pulse count the running total of encoder pulses during this velocity timer period. 0x00 ro count 31:0 555 september 02, 2007 preliminary lm3s8962 microcontroller register 8: qei v elocity (qeispeed), offset 0x01c this register contains the most recently measured velocity of the quadrature encoder . this corresponds to the number of velocity pulses counted in the previous velocity timer period. this register does not update when velen in qeictl is 0. qei v elocity (qeispeed) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 of fset 0x01c t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 speed ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 speed ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field v elocity the measured speed of the quadrature encoder in pulses per period. 0x00 ro speed 31:0 september 02, 2007 556 preliminary quadrature encoder interface (qei) register 9: qei interrupt enable (qeiinten), offset 0x020 this register contains enables for each of the qei module s interrupts. an interrupt is asserted to the controller if its corresponding bit in this register is set to 1. qei interrupt enable (qeiinten) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 of fset 0x020 t ype r/w , reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 intindex intt imer intdir interror reserved r/w r/w r/w r/w ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:4 phase error interrupt enable when 1, an interrupt occurs when a phase error is detected. 0 r/w interror 3 direction change interrupt enable when 1, an interrupt occurs when the direction changes. 0 r/w intdir 2 t imer expires interrupt enable when 1, an interrupt occurs when the velocity timer expires. 0 r/w intt imer 1 index pulse detected interrupt enable when 1, an interrupt occurs when the index pulse is detected. 0 r/w intindex 0 557 september 02, 2007 preliminary lm3s8962 microcontroller register 10: qei raw interrupt status (qeiris), offset 0x024 this register provides the current set of interrupt sources that are asserted, regardless of whether they cause an interrupt to be asserted to the controller (this is set through the qeiinten register). bits set to 1 indicate the latched events that have occurred; a zero bit indicates that the event in question has not occurred. qei raw interrupt status (qeiris) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 of fset 0x024 t ype ro, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 intindex intt imer intdir interror reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:4 phase error detected indicates that a phase error was detected. 0 ro interror 3 direction change detected indicates that the direction has changed. 0 ro intdir 2 v elocity t imer expired indicates that the velocity timer has expired. 0 ro intt imer 1 index pulse asserted indicates that the index pulse has occurred. 0 ro intindex 0 september 02, 2007 558 preliminary quadrature encoder interface (qei) register 1 1: qei interrupt status and clear (qeiisc), offset 0x028 this register provides the current set of interrupt sources that are asserted to the controller . bits set to 1 indicate the latched events that have occurred; a zero bit indicates that the event in question has not occurred. this is a r/w1c register; writing a 1 to a bit position clears the corresponding interrupt reason. qei interrupt status and clear (qeiisc) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 of fset 0x028 t ype r/w1c, reset 0x0000.0000 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 reserved ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 intindex intt imer intdir interror reserved r/w1c r/w1c r/w1c r/w1c ro ro ro ro ro ro ro ro ro ro ro ro t ype 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 reset description reset t ype name bit/field software should not rely on the value of a reserved bit. t o provide compatibility with future products, the value of a reserved bit should be preserved across a read-modify-write operation. 0x00 ro reserved 31:4 phase error interrupt indicates that a phase error was detected. 0 r/w1c interror 3 direction change interrupt indicates that the direction has changed. 0 r/w1c intdir 2 v elocity t imer expired interrupt indicates that the velocity timer has expired. 0 r/w1c intt imer 1 index pulse interrupt indicates that the index pulse has occurred. 0 r/w1c intindex 0 559 september 02, 2007 preliminary lm3s8962 microcontroller 21 pin diagram figure 21-1 on page 560 shows the pin diagram and pin-to-signal-name mapping. figure 21-1. pin connection diagram september 02, 2007 560 preliminary pin diagram 22 signal t ables the following tables list the signals available for each pin. functionality is enabled by software with the gpioafsel register . important: all multiplexed pins are gpios by default, with the exception of the five jt ag pins ( pb7 and pc[3:0] ) which default to the jt ag functionality . t able 22-1 on page 561 shows the pin-to-signal-name mapping, including functional characteristics of the signals. t able 22-2 on page 565 lists the signals in alphabetical order by signal name. t able 22-3 on page 569 groups the signals by functionality , except for gpios. t able 22-4 on page 573 lists the gpio pins and their alternate functionality . t able 22-1. signals by pin number description buffer t ype pin t ype pin name pin number analog-to-digital converter input 0. analog i adc0 1 analog-to-digital converter input 1. analog i adc1 2 the positive supply (3.3 v) for the analog circuits (adc, analog comparators, etc.). these are separated from vdd to minimize the electrical noise contained on vdd from af fecting the analog functions. power - vdda 3 the ground reference for the analog circuits (adc, analog comparators, etc.). these are separated from gnd to minimize the electrical noise contained on vdd from af fecting the analog functions. power - gnda 4 analog-to-digital converter input 2. analog i adc2 5 analog-to-digital converter input 3. analog i adc3 6 low drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater . when the on-chip ldo is used to provide power to the logic, the ldo pin must also be connected to the vdd25 pins at the board level in addition to the decoupling capacitor(s). power - ldo 7 positive supply for i/o and some logic. power - vdd 8 ground reference for logic and i/o pins. power - gnd 9 gpio port d bit 0 ttl i/o pd0 10 can module 0 receive ttl i can0rx gpio port d bit 1 ttl i/o pd1 1 1 can module 0 transmit ttl o can0tx gpio port d bit 2 ttl i/o pd2 12 uar t module 1 receive. when in irda mode, this signal has irda modulation. ttl i u1rx gpio port d bit 3 ttl i/o pd3 13 uar t module 1 transmit. when in irda mode, this signal has irda modulation. ttl o u1tx 561 september 02, 2007 preliminary lm3s8962 microcontroller description buffer t ype pin t ype pin name pin number positive supply for most of the logic function, including the processor core and most peripherals. power - vdd25 14 ground reference for logic and i/o pins. power - gnd 15 xt alp of the ethernet phy ttl o xtalpphy 16 xt aln of the ethernet phy ttl i xtalnphy 17 gpio port g bit 1 ttl i/o pg1 18 pwm 1 ttl o pwm1 gpio port g bit 0 ttl i/o pg0 19 positive supply for i/o and some logic. power - vdd 20 ground reference for logic and i/o pins. power - gnd 21 gpio port c bit 7 ttl i/o pc7 22 gpio port c bit 6 ttl i/o pc6 23 qei module 0 phase b ttl i phb0 gpio port c bit 5 ttl i/o pc5 24 gpio port c bit 4 ttl i/o pc4 25 qei module 0 phase a ttl i pha0 gpio port a bit 0 ttl i/o pa0 26 uar t module 0 receive. when in irda mode, this signal has irda modulation. ttl i u0rx gpio port a bit 1 ttl i/o pa1 27 uar t module 0 transmit. when in irda mode, this signal has irda modulation. ttl o u0tx gpio port a bit 2 ttl i/o pa2 28 ssi module 0 clock ttl i/o ssi0clk gpio port a bit 3 ttl i/o pa3 29 ssi module 0 frame ttl i/o ssi0fss gpio port a bit 4 ttl i/o pa4 30 ssi module 0 receive ttl i ssi0rx gpio port a bit 5 ttl i/o pa5 31 ssi module 0 transmit ttl o ssi0tx positive supply for i/o and some logic. power - vdd 32 ground reference for logic and i/o pins. power - gnd 33 gpio port a bit 6 ttl i/o pa6 34 capture/compare/pwm 1 ttl i/o ccp1 gpio port a bit 7 ttl i/o pa7 35 vcc of the ethernet phy ttl i vccphy 36 rxin of the ethernet phy analog i rxin 37 positive supply for most of the logic function, including the processor core and most peripherals. power - vdd25 38 ground reference for logic and i/o pins. power - gnd 39 rxip of the ethernet phy analog i rxip 40 gnd of the ethernet phy ttl i gndphy 41 september 02, 2007 562 preliminary signal t ables description buffer t ype pin t ype pin name pin number gnd of the ethernet phy ttl i gndphy 42 txop of the ethernet phy analog o txop 43 positive supply for i/o and some logic. power - vdd 44 ground reference for logic and i/o pins. power - gnd 45 txon of the ethernet phy analog o txon 46 gpio port f bit 0 ttl i/o pf0 47 pwm 0 ttl o pwm0 main oscillator crystal input or an external clock reference input. analog i osc0 48 main oscillator crystal output. analog o osc1 49 an external input that brings the processor out of hibernate mode when asserted. od i wake 50 an output that indicates the processor is in hibernate mode. ttl o hib 51 hibernation module oscillator crystal input or an external clock reference input. note that this is either a 4.19-mhz crystal or a 32.768-khz oscillator for the hibernation module r tc. see the clksel bit in the hibctl register . analog i xosc0 52 hibernation module oscillator crystal output. analog o xosc1 53 ground reference for logic and i/o pins. power - gnd 54 power source for the hibernation module. it is normally connected to the positive terminal of a battery and serves as the battery backup/hibernation module power-source supply . power - vbat 55 positive supply for i/o and some logic. power - vdd 56 ground reference for logic and i/o pins. power - gnd 57 mdio of the ethernet phy ttl i/o mdio 58 gpio port f bit 3 ttl i/o pf3 59 mii led 0 ttl o led0 gpio port f bit 2 ttl i/o pf2 60 mii led 1 ttl o led1 gpio port f bit 1 ttl i/o pf1 61 qei module 1 index ttl i idx1 positive supply for most of the logic function, including the processor core and most peripherals. power - vdd25 62 ground reference for logic and i/o pins. power - gnd 63 system reset input. ttl i rst 64 cpu mode bit 0. input must be set to logic 0 (grounded); other encodings reserved. ttl i/o cmod0 65 gpio port b bit 0 ttl i/o pb0 66 pwm 2 ttl o pwm2 gpio port b bit 1 ttl i/o pb1 67 pwm 3 ttl o pwm3 563 september 02, 2007 preliminary lm3s8962 microcontroller description buffer t ype pin t ype pin name pin number positive supply for i/o and some logic. power - vdd 68 ground reference for logic and i/o pins. power - gnd 69 gpio port b bit 2 ttl i/o pb2 70 i2c module 0 clock od i/o i2c0scl gpio port b bit 3 ttl i/o pb3 71 i2c module 0 data od i/o i2c0sda gpio port e bit 0 ttl i/o pe0 72 pwm 4 ttl o pwm4 gpio port e bit 1 ttl i/o pe1 73 pwm 5 ttl o pwm5 gpio port e bit 2 ttl i/o pe2 74 qei module 1 phase b ttl i phb1 gpio port e bit 3 ttl i/o pe3 75 qei module 1 phase a ttl i pha1 cpu mode bit 1. input must be set to logic 0 (grounded); other encodings reserved. ttl i/o cmod1 76 gpio port c bit 3 ttl i/o pc3 77 jt ag tdo and swo ttl o tdo jt ag tdo and swo ttl o swo gpio port c bit 2 ttl i/o pc2 78 jt ag tdi ttl i tdi gpio port c bit 1 ttl i/o pc1 79 jt ag tms and swdio ttl i/o tms jt ag tms and swdio ttl i/o swdio gpio port c bit 0 ttl i/o pc0 80 jt ag/swd clk ttl i tck jt ag/swd clk ttl i swclk positive supply for i/o and some logic. power - vdd 81 ground reference for logic and i/o pins. power - gnd 82 vcc of the ethernet phy ttl i vccphy 83 vcc of the ethernet phy ttl i vccphy 84 gnd of the ethernet phy ttl i gndphy 85 gnd of the ethernet phy ttl i gndphy 86 ground reference for logic and i/o pins. power - gnd 87 positive supply for most of the logic function, including the processor core and most peripherals. power - vdd25 88 gpio port b bit 7 ttl i/o pb7 89 jt ag trstn ttl i trst gpio port b bit 6 ttl i/o pb6 90 analog comparator 0 positive input analog i c0+ gpio port b bit 5 ttl i/o pb5 91 analog comparator 0 output ttl o c0o september 02, 2007 564 preliminary signal t ables description buffer t ype pin t ype pin name pin number gpio port b bit 4 ttl i/o pb4 92 analog comparator 0 negative input analog i c0- positive supply for i/o and some logic. power - vdd 93 ground reference for logic and i/o pins. power - gnd 94 gpio port d bit 4 ttl i/o pd4 95 capture/compare/pwm 0 ttl i/o ccp0 gpio port d bit 5 ttl i/o pd5 96 the ground reference for the analog circuits (adc, analog comparators, etc.). these are separated from gnd to minimize the electrical noise contained on vdd from af fecting the analog functions. power - gnda 97 the positive supply (3.3 v) for the analog circuits (adc, analog comparators, etc.). these are separated from vdd to minimize the electrical noise contained on vdd from af fecting the analog functions. power - vdda 98 gpio port d bit 6 ttl i/o pd6 99 pwm fault ttl i fault gpio port d bit 7 ttl i/o pd7 100 qei module 0 index ttl i idx0 t able 22-2. signals by signal name description buffer t ype pin t ype pin number pin name analog-to-digital converter input 0. analog i 1 adc0 analog-to-digital converter input 1. analog i 2 adc1 analog-to-digital converter input 2. analog i 5 adc2 analog-to-digital converter input 3. analog i 6 adc3 analog comparator 0 positive input analog i 90 c0+ analog comparator 0 negative input analog i 92 c0- analog comparator 0 output ttl o 91 c0o can module 0 receive ttl i 10 can0rx can module 0 transmit ttl o 1 1 can0tx capture/compare/pwm 0 ttl i/o 95 ccp0 capture/compare/pwm 1 ttl i/o 34 ccp1 cpu mode bit 0. input must be set to logic 0 (grounded); other encodings reserved. ttl i/o 65 cmod0 cpu mode bit 1. input must be set to logic 0 (grounded); other encodings reserved. ttl i/o 76 cmod1 pwm fault ttl i 99 fault ground reference for logic and i/o pins. power - 9 gnd ground reference for logic and i/o pins. power - 15 gnd ground reference for logic and i/o pins. power - 21 gnd ground reference for logic and i/o pins. power - 33 gnd ground reference for logic and i/o pins. power - 39 gnd 565 september 02, 2007 preliminary lm3s8962 microcontroller description buffer t ype pin t ype pin number pin name ground reference for logic and i/o pins. power - 45 gnd ground reference for logic and i/o pins. power - 54 gnd ground reference for logic and i/o pins. power - 57 gnd ground reference for logic and i/o pins. power - 63 gnd ground reference for logic and i/o pins. power - 69 gnd ground reference for logic and i/o pins. power - 82 gnd ground reference for logic and i/o pins. power - 87 gnd ground reference for logic and i/o pins. power - 94 gnd the ground reference for the analog circuits (adc, analog comparators, etc.). these are separated from gnd to minimize the electrical noise contained on vdd from af fecting the analog functions. power - 4 gnda the ground reference for the analog circuits (adc, analog comparators, etc.). these are separated from gnd to minimize the electrical noise contained on vdd from af fecting the analog functions. power - 97 gnda gnd of the ethernet phy ttl i 41 gndphy gnd of the ethernet phy ttl i 42 gndphy gnd of the ethernet phy ttl i 85 gndphy gnd of the ethernet phy ttl i 86 gndphy an output that indicates the processor is in hibernate mode. ttl o 51 hib i2c module 0 clock od i/o 70 i2c0scl i2c module 0 data od i/o 71 i2c0sda qei module 0 index ttl i 100 idx0 qei module 1 index ttl i 61 idx1 low drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater . when the on-chip ldo is used to provide power to the logic, the ldo pin must also be connected to the vdd25 pins at the board level in addition to the decoupling capacitor(s). power - 7 ldo mii led 0 ttl o 59 led0 mii led 1 ttl o 60 led1 mdio of the ethernet phy ttl i/o 58 mdio main oscillator crystal input or an external clock reference input. analog i 48 osc0 main oscillator crystal output. analog o 49 osc1 gpio port a bit 0 ttl i/o 26 pa0 gpio port a bit 1 ttl i/o 27 pa1 gpio port a bit 2 ttl i/o 28 pa2 gpio port a bit 3 ttl i/o 29 pa3 gpio port a bit 4 ttl i/o 30 pa4 gpio port a bit 5 ttl i/o 31 pa5 september 02, 2007 566 preliminary signal t ables description buffer t ype pin t ype pin number pin name gpio port a bit 6 ttl i/o 34 pa6 gpio port a bit 7 ttl i/o 35 pa7 gpio port b bit 0 ttl i/o 66 pb0 gpio port b bit 1 ttl i/o 67 pb1 gpio port b bit 2 ttl i/o 70 pb2 gpio port b bit 3 ttl i/o 71 pb3 gpio port b bit 4 ttl i/o 92 pb4 gpio port b bit 5 ttl i/o 91 pb5 gpio port b bit 6 ttl i/o 90 pb6 gpio port b bit 7 ttl i/o 89 pb7 gpio port c bit 0 ttl i/o 80 pc0 gpio port c bit 1 ttl i/o 79 pc1 gpio port c bit 2 ttl i/o 78 pc2 gpio port c bit 3 ttl i/o 77 pc3 gpio port c bit 4 ttl i/o 25 pc4 gpio port c bit 5 ttl i/o 24 pc5 gpio port c bit 6 ttl i/o 23 pc6 gpio port c bit 7 ttl i/o 22 pc7 gpio port d bit 0 ttl i/o 10 pd0 gpio port d bit 1 ttl i/o 1 1 pd1 gpio port d bit 2 ttl i/o 12 pd2 gpio port d bit 3 ttl i/o 13 pd3 gpio port d bit 4 ttl i/o 95 pd4 gpio port d bit 5 ttl i/o 96 pd5 gpio port d bit 6 ttl i/o 99 pd6 gpio port d bit 7 ttl i/o 100 pd7 gpio port e bit 0 ttl i/o 72 pe0 gpio port e bit 1 ttl i/o 73 pe1 gpio port e bit 2 ttl i/o 74 pe2 gpio port e bit 3 ttl i/o 75 pe3 gpio port f bit 0 ttl i/o 47 pf0 gpio port f bit 1 ttl i/o 61 pf1 gpio port f bit 2 ttl i/o 60 pf2 gpio port f bit 3 ttl i/o 59 pf3 gpio port g bit 0 ttl i/o 19 pg0 gpio port g bit 1 ttl i/o 18 pg1 qei module 0 phase a ttl i 25 pha0 qei module 1 phase a ttl i 75 pha1 qei module 0 phase b ttl i 23 phb0 qei module 1 phase b ttl i 74 phb1 pwm 0 ttl o 47 pwm0 pwm 1 ttl o 18 pwm1 567 september 02, 2007 preliminary lm3s8962 microcontroller description buffer t ype pin t ype pin number pin name pwm 2 ttl o 66 pwm2 pwm 3 ttl o 67 pwm3 pwm 4 ttl o 72 pwm4 pwm 5 ttl o 73 pwm5 system reset input. ttl i 64 rst rxin of the ethernet phy analog i 37 rxin rxip of the ethernet phy analog i 40 rxip ssi module 0 clock ttl i/o 28 ssi0clk ssi module 0 frame ttl i/o 29 ssi0fss ssi module 0 receive ttl i 30 ssi0rx ssi module 0 transmit ttl o 31 ssi0tx jt ag/swd clk ttl i 80 swclk jt ag tms and swdio ttl i/o 79 swdio jt ag tdo and swo ttl o 77 swo jt ag/swd clk ttl i 80 tck jt ag tdi ttl i 78 tdi jt ag tdo and swo ttl o 77 tdo jt ag tms and swdio ttl i/o 79 tms jt ag trstn ttl i 89 trst txon of the ethernet phy analog o 46 txon txop of the ethernet phy analog o 43 txop uar t module 0 receive. when in irda mode, this signal has irda modulation. ttl i 26 u0rx uar t module 0 transmit. when in irda mode, this signal has irda modulation. ttl o 27 u0tx uar t module 1 receive. when in irda mode, this signal has irda modulation. ttl i 12 u1rx uar t module 1 transmit. when in irda mode, this signal has irda modulation. ttl o 13 u1tx power source for the hibernation module. it is normally connected to the positive terminal of a battery and serves as the battery backup/hibernation module power-source supply . power - 55 vbat vcc of the ethernet phy ttl i 36 vccphy vcc of the ethernet phy ttl i 83 vccphy vcc of the ethernet phy ttl i 84 vccphy positive supply for i/o and some logic. power - 8 vdd positive supply for i/o and some logic. power - 20 vdd positive supply for i/o and some logic. power - 32 vdd positive supply for i/o and some logic. power - 44 vdd positive supply for i/o and some logic. power - 56 vdd positive supply for i/o and some logic. power - 68 vdd positive supply for i/o and some logic. power - 81 vdd positive supply for i/o and some logic. power - 93 vdd september 02, 2007 568 preliminary signal t ables description buffer t ype pin t ype pin number pin name positive supply for most of the logic function, including the processor core and most peripherals. power - 14 vdd25 positive supply for most of the logic function, including the processor core and most peripherals. power - 38 vdd25 positive supply for most of the logic function, including the processor core and most peripherals. power - 62 vdd25 positive supply for most of the logic function, including the processor core and most peripherals. power - 88 vdd25 the positive supply (3.3 v) for the analog circuits (adc, analog comparators, etc.). these are separated from vdd to minimize the electrical noise contained on vdd from af fecting the analog functions. power - 3 vdda the positive supply (3.3 v) for the analog circuits (adc, analog comparators, etc.). these are separated from vdd to minimize the electrical noise contained on vdd from af fecting the analog functions. power - 98 vdda an external input that brings the processor out of hibernate mode when asserted. od i 50 wake hibernation module oscillator crystal input or an external clock reference input. note that this is either a 4.19-mhz crystal or a 32.768-khz oscillator for the hibernation module r tc. see the clksel bit in the hibctl register . analog i 52 xosc0 hibernation module oscillator crystal output. analog o 53 xosc1 xt aln of the ethernet phy ttl i 17 xtalnphy xt alp of the ethernet phy ttl o 16 xtalpphy t able 22-3. signals by function, except for gpio description buffer t ype pin t ype pin number pin name function analog-to-digital converter input 0. analog i 1 adc0 adc analog-to-digital converter input 1. analog i 2 adc1 analog-to-digital converter input 2. analog i 5 adc2 analog-to-digital converter input 3. analog i 6 adc3 analog comparator 0 positive input analog i 90 c0+ analog comparators analog comparator 0 negative input analog i 92 c0- analog comparator 0 output ttl o 91 c0o can module 0 receive ttl i 10 can0rx controller area network can module 0 transmit ttl o 1 1 can0tx 569 september 02, 2007 preliminary lm3s8962 microcontroller description buffer t ype pin t ype pin number pin name function gnd of the ethernet phy ttl i 41 gndphy ethernet phy gnd of the ethernet phy ttl i 42 gndphy gnd of the ethernet phy ttl i 85 gndphy gnd of the ethernet phy ttl i 86 gndphy mii led 0 ttl o 59 led0 mii led 1 ttl o 60 led1 mdio of the ethernet phy ttl i/o 58 mdio rxin of the ethernet phy analog i 37 rxin rxip of the ethernet phy analog i 40 rxip txon of the ethernet phy analog o 46 txon txop of the ethernet phy analog o 43 txop vcc of the ethernet phy ttl i 36 vccphy vcc of the ethernet phy ttl i 83 vccphy vcc of the ethernet phy ttl i 84 vccphy xt aln of the ethernet phy ttl i 17 xtalnphy xt alp of the ethernet phy ttl o 16 xtalpphy capture/compare/pwm 0 ttl i/o 95 ccp0 general-purpose t imers capture/compare/pwm 1 ttl i/o 34 ccp1 i2c module 0 clock od i/o 70 i2c0scl i2c i2c module 0 data od i/o 71 i2c0sda jt ag/swd clk ttl i 80 swclk jt ag/swd/swo jt ag tms and swdio ttl i/o 79 swdio jt ag tdo and swo ttl o 77 swo jt ag/swd clk ttl i 80 tck jt ag tdi ttl i 78 tdi jt ag tdo and swo ttl o 77 tdo jt ag tms and swdio ttl i/o 79 tms pwm fault ttl i 99 fault pwm pwm 0 ttl o 47 pwm0 pwm 1 ttl o 18 pwm1 pwm 2 ttl o 66 pwm2 pwm 3 ttl o 67 pwm3 pwm 4 ttl o 72 pwm4 pwm 5 ttl o 73 pwm5 september 02, 2007 570 preliminary signal t ables description buffer t ype pin t ype pin number pin name function ground reference for logic and i/o pins. power - 9 gnd power ground reference for logic and i/o pins. power - 15 gnd ground reference for logic and i/o pins. power - 21 gnd ground reference for logic and i/o pins. power - 33 gnd ground reference for logic and i/o pins. power - 39 gnd ground reference for logic and i/o pins. power - 45 gnd ground reference for logic and i/o pins. power - 54 gnd ground reference for logic and i/o pins. power - 57 gnd ground reference for logic and i/o pins. power - 63 gnd ground reference for logic and i/o pins. power - 69 gnd ground reference for logic and i/o pins. power - 82 gnd ground reference for logic and i/o pins. power - 87 gnd ground reference for logic and i/o pins. power - 94 gnd the ground reference for the analog circuits (adc, analog comparators, etc.). these are separated from gnd to minimize the electrical noise contained on vdd from af fecting the analog functions. power - 4 gnda the ground reference for the analog circuits (adc, analog comparators, etc.). these are separated from gnd to minimize the electrical noise contained on vdd from af fecting the analog functions. power - 97 gnda an output that indicates the processor is in hibernate mode. ttl o 51 hib low drop-out regulator output voltage. this pin requires an external capacitor between the pin and gnd of 1 f or greater . when the on-chip ldo is used to provide power to the logic, the ldo pin must also be connected to the vdd25 pins at the board level in addition to the decoupling capacitor(s). power - 7 ldo power source for the hibernation module. it is normally connected to the positive terminal of a battery and serves as the battery backup/hibernation module power-source supply . power - 55 vbat positive supply for i/o and some logic. power - 8 vdd positive supply for i/o and some logic. power - 20 vdd positive supply for i/o and some logic. power - 32 vdd positive supply for i/o and some logic. power - 44 vdd positive supply for i/o and some logic. power - 56 vdd positive supply for i/o and some logic. power - 68 vdd positive supply for i/o and some logic. power - 81 vdd positive supply for i/o and some logic. power - 93 vdd positive supply for most of the logic function, including the processor core and most peripherals. power - 14 vdd25 positive supply for most of the logic function, including the processor core and most peripherals. power - 38 vdd25 positive supply for most of the logic function, including the processor core and most peripherals. power - 62 vdd25 571 september 02, 2007 preliminary lm3s8962 microcontroller description buffer t ype pin t ype pin number pin name function vdd25 positive supply for most of the logic function, including the processor core and most peripherals. power - 88 the positive supply (3.3 v) for the analog circuits (adc, analog comparators, etc.). these are separated from vdd to minimize the electrical noise contained on vdd from af fecting the analog functions. power - 3 vdda the positive supply (3.3 v) for the analog circuits (adc, analog comparators, etc.). these are separated from vdd to minimize the electrical noise contained on vdd from af fecting the analog functions. power - 98 vdda an external input that brings the processor out of hibernate mode when asserted. od i 50 wake qei module 0 index ttl i 100 idx0 qei qei module 1 index ttl i 61 idx1 qei module 0 phase a ttl i 25 pha0 qei module 1 phase a ttl i 75 pha1 qei module 0 phase b ttl i 23 phb0 qei module 1 phase b ttl i 74 phb1 ssi module 0 clock ttl i/o 28 ssi0clk ssi ssi module 0 frame ttl i/o 29 ssi0fss ssi module 0 receive ttl i 30 ssi0rx ssi module 0 transmit ttl o 31 ssi0tx cpu mode bit 0. input must be set to logic 0 (grounded); other encodings reserved. ttl i/o 65 cmod0 system control & clocks cpu mode bit 1. input must be set to logic 0 (grounded); other encodings reserved. ttl i/o 76 cmod1 main oscillator crystal input or an external clock reference input. analog i 48 osc0 main oscillator crystal output. analog o 49 osc1 system reset input. ttl i 64 rst jt ag trstn ttl i 89 trst hibernation module oscillator crystal input or an external clock reference input. note that this is either a 4.19-mhz crystal or a 32.768-khz oscillator for the hibernation module r tc. see the clksel bit in the hibctl register . analog i 52 xosc0 hibernation module oscillator crystal output. analog o 53 xosc1 uar t module 0 receive. when in irda mode, this signal has irda modulation. ttl i 26 u0rx uar t uar t module 0 transmit. when in irda mode, this signal has irda modulation. ttl o 27 u0tx uar t module 1 receive. when in irda mode, this signal has irda modulation. ttl i 12 u1rx uar t module 1 transmit. when in irda mode, this signal has irda modulation. ttl o 13 u1tx september 02, 2007 572 preliminary signal t ables t able 22-4. gpio pins and alternate functions multiplexed function multiplexed function pin number gpio pin u0rx 26 pa0 u0tx 27 pa1 ssi0clk 28 pa2 ssi0fss 29 pa3 ssi0rx 30 pa4 ssi0tx 31 pa5 ccp1 34 pa6 35 pa7 pwm2 66 pb0 pwm3 67 pb1 i2c0scl 70 pb2 i2c0sda 71 pb3 c0- 92 pb4 c0o 91 pb5 c0+ 90 pb6 trst 89 pb7 swclk tck 80 pc0 swdio tms 79 pc1 tdi 78 pc2 swo tdo 77 pc3 pha0 25 pc4 24 pc5 phb0 23 pc6 22 pc7 can0rx 10 pd0 can0tx 1 1 pd1 u1rx 12 pd2 u1tx 13 pd3 ccp0 95 pd4 96 pd5 fault 99 pd6 idx0 100 pd7 pwm4 72 pe0 pwm5 73 pe1 phb1 74 pe2 pha1 75 pe3 pwm0 47 pf0 idx1 61 pf1 led1 60 pf2 led0 59 pf3 19 pg0 573 september 02, 2007 preliminary lm3s8962 microcontroller multiplexed function multiplexed function pin number gpio pin pwm1 18 pg1 september 02, 2007 574 preliminary signal t ables 23 operating characteristics t able 23-1. t emperature characteristics unit v alue symbol characteristic c -40 to +85 t a operating temperature range a a. maximum storage temperature is 150c. t able 23-2. thermal characteristics unit v alue symbol characteristic c/w 55.3 ja thermal resistance (junction to ambient) a c t a + (p a vg ? ja ) t j a verage junction temperature b a. junction to ambient thermal resistance ja numbers are determined by a package simulator . b. power dissipation is a function of temperature. 575 september 02, 2007 preliminary lm3s8962 microcontroller 24 electrical characteristics 24.1 dc characteristics 24.1.1 maximum ratings the maximum ratings are the limits to which the device can be subjected without permanently damaging the device. note: the device is not guaranteed to operate properly at the maximum ratings. t able 24-1. maximum ratings unit v alue symbol characteristic a max min v 4 0 v dd i/o supply voltage (v dd ) v 4 0 v dd25 core supply voltage (v dd25 ) v 4 0 v dda analog supply voltage (v dda ) v 4 0 v ba t battery supply voltage (v ba t ) v 4 0 v ccphy ethernet phy supply voltage (v ccphy ) v 5.5 -0.3 v in input voltage ma 25 - i maximum current per output pins a. v oltages are measured with respect to gnd. important: this device contains circuitry to protect the inputs against damage due to high-static voltages or electric fields; however , it is advised that normal precautions be taken to avoid application of any voltage higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are connected to an appropriate logic voltage level (for example, either gnd or v dd ). 24.1.2 recommended dc operating conditions t able 24-2. recommended dc operating conditions unit max nom min parameter name parameter v 3.6 3.3 3.0 i/o supply voltage v dd v 2.75 2.5 2.25 core supply voltage v dd25 v 3.6 3.3 3.0 analog supply voltage v dda v 3.6 3.0 2.3 battery supply voltage v ba t v 3.6 3.3 3.0 ethernet phy supply voltage v ccphy v 5.0 - 2.0 high-level input voltage v ih v 1.3 - -0.3 low-level input voltage v il v v dd - 0.8 * v dd high-level input voltage for schmitt trigger inputs v sih v 0.2 * v dd - 0 low-level input voltage for schmitt trigger inputs v sil v - - 2.4 high-level output voltage v oh v 0.4 - - low-level output voltage v ol september 02, 2007 576 preliminary electrical characteristics unit max nom min parameter name parameter high-level source current, v oh =2.4 v i oh ma - - 2.0 2-ma drive ma - - 4.0 4-ma drive ma - - 8.0 8-ma drive low-level sink current, v ol =0.4 v i ol ma - - 2.0 2-ma drive ma - - 4.0 4-ma drive ma - - 8.0 8-ma drive 24.1.3 on-chip low drop-out (ldo) regulator characteristics t able 24-3. ldo regulator characteristics unit max nom min parameter name parameter v 2.75 2.5 2.25 programmable internal (logic) power supply output value v ldoout % - 2% - output voltage accuracy s 100 - - power-on time t pon s 200 - - t ime on t on s 100 - - t ime of f t off mv - 50 - step programming incremental voltage v step f 3.0 - 1.0 external filter capacitor size for internal power supply c ldo 24.1.4 power specifications the power measurements specified in the tables that follow are run on the core processor using sram with the following specifications (except as noted): v dd = 3.3 v v dd25 = 2.50 v v ba t = 3.0 v v dda = 3.3 v v ddphy = 3.3 v t emperature = 25c clock source (mosc) =3.579545 mhz crystal oscillator main oscillator (mosc) = enabled internal oscillator (iosc) = disabled 577 september 02, 2007 preliminary lm3s8962 microcontroller t able 24-4. detailed power specifications unit 3.0 v v ba t 2.5 v v dd25 3.3 v v dd , v dda , v ddphy conditions parameter name parameter max nom max nom max nom ma pending a 0 pending a 108 pending a 48 v dd25 = 2.50 v code= while(1){} executed in flash peripherals = all on system clock = 50 mhz (with pll) run mode 1 (flash loop) i dd_run ma pending a 0 pending a 52 pending a 5 v dd25 = 2.50 v code= while(1){} executed in flash peripherals = all off system clock = 50 mhz (with pll) run mode 2 (flash loop) ma pending a 0 pending a 100 pending a 48 v dd25 = 2.50 v code= while(1){} executed in sram peripherals = all on system clock = 50 mhz (with pll) run mode 1 (sram loop) ma pending a 0 pending a 45 pending a 5 v dd25 = 2.50 v code= while(1){} executed in sram peripherals = all off system clock = 50 mhz (with pll) run mode 2 (sram loop) ma pending a 0 pending a 16 pending a 5 v dd25 = 2.50 v peripherals = all off system clock = 50 mhz (with pll) sleep mode i dd_sleep ma pending a 0 pending a 0.21 pending a 4.6 ldo = 2.25 v peripherals = all off system clock = iosc30khz/64 deep-sleep mode i dd_deepsleep a pending a 16 pending a 0 pending a 0 v ba t = 3.0 v v dd = 0 v v dd25 = 0 v v dda = 0 v v ddphy = 0 v peripherals = all off system clock = off hibernate module = 32 khz hibernate mode i dd_hiberna te a. pending characterization completion. september 02, 2007 578 preliminary electrical characteristics 24.1.5 flash memory characteristics t able 24-5. flash memory characteristics unit max nom min parameter name parameter cycles - 100,000 10,000 number of guaranteed program/erase cycles before failure a pe cyc years - - 10 data retention at average operating temperature of 85?c t ret s - - 20 w ord program time t prog ms - - 20 page erase time t erase ms - - 200 mass erase time t me a. a program/erase cycle is defined as switching the bits from 1-> 0 -> 1. 24.2 ac characteristics 24.2.1 load conditions unless otherwise specified, the following conditions are true for all timing measurements. t iming measurements are for 4-ma drive strength. figure 24-1. load conditions 24.2.2 clocks t able 24-6. phase locked loop (pll) characteristics unit max nom min parameter name parameter mhz 8.192 - 3.579545 crystal reference a f ref_crystal mhz 8.192 - 3.579545 external clock reference a f ref_ext mhz - 400 - pll frequency b f pll ms 0.5 - - pll lock time t ready a. the exact value is determined by the crystal value programmed into the xtal field of the run-mode clock configuration (rcc) register . b. pll frequency is automatically calculated by the hardware based on the xtal field of the rcc register . t able 24-7. clock characteristics unit max nom min parameter name parameter mhz 15.6 12 8.4 internal 12 mhz oscillator frequency f iosc khz 39 30 21 internal 30 khz oscillator frequency f iosc30khz mhz - 4.194304 - hibernation module oscillator frequency f xosc mhz - 4.194304 - crystal reference for hibernation oscillator f xosc_xt al khz - 32.768 - external clock reference for hibernation module f xosc_ext 579 september 02, 2007 preliminary lm3s8962 microcontroller c l = 50 pf gnd pin unit max nom min parameter name parameter mhz 8 - 1 main oscillator frequency f mosc ns 1000 - 125 main oscillator period t mosc_per mhz 8 - 1 crystal reference using the main oscillator (pll in byp ass mode) a f ref_crystal_bypass mhz 50 - 0 external clock reference (pll in byp ass mode) a f ref_ext_bypass mhz 50 - 0 system clock f system_clock a. the adc must be clocked from the pll or directly from a 14-mhz to 18-mhz clock source to operate properly . t able 24-8. crystal characteristics units v alue parameter name mhz 3.5 4 6 8 frequency ppm 50 50 50 50 frequency tolerance ppm/yr 5 5 5 5 aging parallel parallel parallel parallel oscillation mode ppm 25 25 25 25 t emperature stability (0 - 85 c) pf 63.5 55.6 37.0 27.8 motional capacitance (typ) mh 32.7 28.6 19.1 14.3 motional inductance (typ) ? 220 200 160 120 equivalent series resistance (max) pf 10 10 10 10 shunt capacitance (max) pf 16 16 16 16 load capacitance (typ) w 100 100 100 100 drive level (typ) 24.2.3 analog-to-digital converter t able 24-9. adc characteristics unit max nom min parameter name parameter v 3.0 - - maximum single-ended, full-scale analog input voltage v adcin v 0 - - minimum single-ended, full-scale analog input voltage v 1.5 - - maximum dif ferential, full-scale analog input voltage v -1.5 - - minimum dif ferential, full-scale analog input voltage pf - 1 - equivalent input capacitance c adcin bits - 10 - resolution n mhz 9 8 7 adc internal clock frequency f adc t adc cycles a 16 - - conversion time t adcconv k samples/s 563 500 438 conversion rate f adcconv lsb 1 - - integral nonlinearity inl lsb 1 - - dif ferential nonlinearity dnl lsb 1 - - of fset off lsb 1 - - gain gain a. t adc = 1/f adc clock september 02, 2007 580 preliminary electrical characteristics 24.2.4 analog comparator t able 24-10. analog comparator characteristics unit max nom min parameter name parameter mv 25 10 - input of fset voltage v os v v dd -1.5 - 0 input common mode voltage range v cm db - - 50 common mode rejection ratio c mrr s 1 - - response time t r t s 10 - - comparator mode change to output v alid t mc t able 24-1 1. analog comparator v oltage reference characteristics unit max nom min parameter name parameter lsb - v dd /32 - resolution high range r hr lsb - v dd /24 - resolution low range r lr lsb 1/2 - - absolute accuracy high range a hr lsb 1/4 - - absolute accuracy low range a lr 24.2.5 i 2 c t able 24-12. i 2 c characteristics unit max nom min parameter name parameter parameter no. system clocks - - 36 start condition hold time t sch i1 a system clocks - - 36 clock low period t lp i2 a ns (see note b) - - i2cscl / i2csda rise time (v il =0.5 v to v ih =2.4 v) t sr t i3 b system clocks - - 2 data hold time t dh i4 a ns 10 9 - i2cscl / i2csda fall time (v ih =2.4 v to v il =0.5 v) t sft i5 c system clocks - - 24 clock high time t ht i6 a system clocks - - 18 data setup time t ds i7 a system clocks - - 36 start condition setup time (for repeated start condition only) t scsr i8 a system clocks - - 24 stop condition setup time t scs i9 a a. v alues depend on the value programmed into the tpr bit in the i 2 c master t imer period (i2cmtpr) register; a tpr programmed for the maximum i2cscl frequency (tpr=0x2) results in a minimum output timing as shown in the table above. the i 2 c interface is designed to scale the actual data transition time to move it to the middle of the i2cscl low period. the actual position is af fected by the value programmed into the tpr ; however , the numbers given in the above values are minimum values. b. because i2cscl and i2csda are open-drain-type outputs, which the controller can only actively drive low , the time i2cscl or i2csda takes to reach a high level depends on external signal capacitance and pull-up resistor values. c. specified at a nominal 50 pf load. 581 september 02, 2007 preliminary lm3s8962 microcontroller figure 24-2. i 2 c t iming 24.2.6 ethernet controller t able 24-13. 100base-tx t ransmitter characteristics a unit max nom min parameter name mvpk 1050 - 950 peak output amplitude mvpk 1.02 - 0.98 output amplitude symmetry % 5 - - output overshoot ns 5 - 3 rise/fall time ps 500 - - rise/fall time imbalance ps - - - duty cycle distortion ns 1.4 - - jitter a. measured at the line side of the transformer . t able 24-14. 100base-tx t ransmitter characteristics (informative) a unit max nom min parameter name db - - 16 return loss s - - 350 open-circuit inductance a. the specifications in this table are included for information only . they are mainly a function of the external transformer and termination resistors used for measurements. t able 24-15. 100base-tx receiver characteristics unit max nom min parameter name mvppd 700 600 signal detect assertion threshold mvppd - 425 350 signal detect de-assertion threshold k? - - 20 dif ferential input resistance ns - - 4 jitter tolerance (pk-pk) % +75 - -75 baseline wander tracking s 1000 - - signal detect assertion time s 4 - - signal detect de-assertion time t able 24-16. 10base-t t ransmitter characteristics a unit max nom min parameter name v 2.8 - 2.2 peak dif ferential output signal db - - 27 harmonic content ns - 100 - link pulse width september 02, 2007 582 preliminary electrical characteristics i2cscl i2csda i1 i2 i4 i6 i7 i8 i5 i3 i9 unit max nom min parameter name ns - 300 350 - start-of-idle pulse width a. the manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against the templates and using the procedures found in clause 14 of ieee 802.3 . t able 24-17. 10base-t t ransmitter characteristics (informative) a unit max nom min parameter name db - - 15 output return loss db - - 29-17log(f/10) output impedance balance mv 50 - - peak common-mode output voltage mv 100 - - common-mode rejection ns 1 - - common-mode rejection jitter a. the specifications in this table are included for information only . they are mainly a function of the external transformer and termination resistors used for measurements. t able 24-18. 10base-t receiver characteristics unit max nom min parameter name bt - 10 - dll phase acquisition time ns - - 30 jitter tolerance (pk-pk) mvppd 700 600 500 input squelched threshold mvppd 425 350 275 input unsquelched threshold k? - 20 - dif ferential input resistance - - 10 -10 - bit error ratio v - - 25 common-mode rejection t able 24-19. isolation t ransformers a condition v alue name +/- 5% 1 ct : 1 ct t urns ratio @ 10 mv , 10 khz 350 uh (min) open-circuit inductance @ 1 mhz (min) 0.40 uh (max) leakage inductance 25 pf (max) inter-winding capacitance 0.9 ohm (max) dc resistance 0-65 mhz 0.4 db (typ) insertion loss v rms 1500 hipot a. t wo simple 1:1 isolation transformers are required at the line interface. t ransformers with integrated common-mode chokes are recommended for exceeding fcc requirements. this table gives the recommended line transformer characteristics. note: the 100base-tx amplitude specifications assume a transformer loss of 0.4 db. for the transmit line transformer with higher insertion losses, up to 1.2 db of insertion loss can be compensated by selecting the appropriate setting in the t ransmit amplitude selection ( txo ) bits in the mr19 register . 583 september 02, 2007 preliminary lm3s8962 microcontroller t able 24-20. ethernet reference crystal a condition v alue name mhz 25.00000 frequency pf 4 c load capacitance b ppm 50 frequency tolerance ppm/yr 2 aging ppm 5 t emperature stability (0 to 70) parallel resonance, fundamental mode oscillation mode parameters at 25 c 2 c; drive level = 0.5 mw w 50-100 drive level (typ) pf 10 shunt capacitance (max) ff 10 motional capacitance (min) ? 60 serious resistance (max) > 5 db below main within 500 khz spurious response (max) a. if the internal crystal oscillator is used, select a crystal with the following characteristics. b. equivalent dif ferential capacitance across xtlp/xtln. c. if crystal with a larger load is used, external shunt capacitors to ground should be added to make up the equivalent capacitance dif ference. figure 24-3. external xtlp oscillator characteristics t able 24-21. external xtlp oscillator characteristics unit max nom min symbol parameter name - 0.8 - - xtln il v xtln input low v oltage - - 25.0 - xtlp f xtlp frequency a - - 40 - t clkper xtlp period b % 60 60 - 40 40 xtlp dc xtlp duty cycle ns 4.0 - - t r , t f rise/fall t ime ns 0.1 - - absolute jitter a. ieee 802.3 frequency tolerance 50 ppm. september 02, 2007 584 preliminary electrical characteristics t clkper t r t clkhi t clklo t f b. ieee 802.3 frequency tolerance 50 ppm. 24.2.7 hibernation module the hibernation module requires special system implementation considerations since it is intended to power-down all other sections of its host device. the system power-supply distribution and interfaces of the system must be driven to 0 v dc or powered down with the same regulator controlled by hib . the regulators controlled by hib are expected to have a settling time of 250 s or less. t able 24-22. hibernation module characteristics unit max nom min parameter name parameter parameter no s - 200 - internal 32.768 khz clock reference rising edge to /hib asserted t hib_low h1 s - 30 - internal 32.768 khz clock reference rising edge to /hib deasserted t hib_high h2 s - - 62 /w ake assertion time t w ake_asser t h3 s 124 - 62 /w ake assert to /hib desassert t w aket ohib h4 ms - - 20 xosc settling time a t xosc_settle h5 s - - 92 t ime for a write to non-volatile registers in hib module to complete t hib_reg_write h6 s 250 - - hib deassert to vdd and vdd25 at minimum operational level t hib_t o_vdd h7 a. this parameter is highly sensitive to pcb layout and trace lengths, which may make this parameter time longer . care must be taken in pcb design to minimize trace lengths and rlc (resistance, inductance, capacitance). figure 24-4. hibernation module t iming 24.2.8 synchronous serial interface (ssi) t able 24-23. ssi characteristics unit max nom min parameter name parameter parameter no. system clocks 65024 - 2 ssiclk cycle time t clk_per s1 t clk_per - 1/2 - ssiclk high time t clk_high s2 t clk_per - 1/2 - ssiclk low time t clk_low s3 ns 26 7.4 - ssiclk rise/fall time t clkrf s4 ns 20 - 0 data from master valid delay time t dmd s5 ns - - 20 data from master setup time t dms s6 ns - - 40 data from master hold time t dmh s7 585 september 02, 2007 preliminary lm3s8962 microcontroller 32.768 khz ( internal) /hib h4 h1 /w ake h2 h3 unit max nom min parameter name parameter parameter no. ns - - 20 data from slave setup time t dss s8 ns - - 40 data from slave hold time t dsh s9 figure 24-5. ssi t iming for ti frame format (frf=01), single t ransfer t iming measurement figure 24-6. ssi t iming for microwire frame format (frf=10), single t ransfer september 02, 2007 586 preliminary electrical characteristics ssiclk ssifss ssitx ssirx msb lsb s2 s3 s1 s4 4 to 16 bits 0 ssiclk ssifss ssitx ssirx msb lsb msb lsb s2 s3 s1 8-bit control 4 to 16 bits output data figure 24-7. ssi t iming for spi frame format (frf=00), with sph=1 24.2.9 jt ag and boundary scan t able 24-24. jt ag characteristics unit max nom min parameter name parameter parameter no. mhz 10 - 0 tck operational clock frequency f tck j1 ns - - 100 tck operational clock period t tck j2 ns - t tck - tck clock low time t tck_low j3 ns - t tck - tck clock high time t tck_high j4 ns 10 - 0 tck rise time t tck_r j5 ns 10 - 0 tck fall time t tck_f j6 ns - - 20 tms setup time to tck rise t tms_su j7 ns - - 20 tms hold time from tck rise t tms_hld j8 ns - - 25 tdi setup time to tck rise t tdi_su j9 ns - - 25 tdi hold time from tck rise t tdi_hld j10 ns 35 23 - 2-ma drive tck fall to data v alid from high-z j1 1 t tdo_zdv ns 26 15 4-ma drive ns 25 14 8-ma drive ns 29 18 8-ma drive with slew rate control ns 35 21 - 2-ma drive tck fall to data v alid from data v alid j12 t tdo_dv ns 25 14 4-ma drive ns 24 13 8-ma drive ns 28 18 8-ma drive with slew rate control 587 september 02, 2007 preliminary lm3s8962 microcontroller ssiclk ( spo=1) ssitx ( master) ssirx ( slave) lsb ssiclk ( spo=0) s2 s1 s4 ssifss lsb s3 msb s5 s6 s7 s9 s8 msb unit max nom min parameter name parameter parameter no. ns 1 1 9 - 2-ma drive tck fall to high-z from data v alid j13 t tdo_dvz ns 9 7 4-ma drive ns 8 6 8-ma drive ns 9 7 8-ma drive with slew rate control ns - - 100 trst assertion time t trst j14 ns - - 10 trst setup time to tck rise t trst_su j15 figure 24-8. jt ag t est clock input t iming figure 24-9. jt ag t est access port (t ap) t iming figure 24-10. jt ag trst t iming 24.2.10 general-purpose i/o note: all gpios are 5 v-tolerant. september 02, 2007 588 preliminary electrical characteristics tck j14 j15 trst tdo output v alid tck tdo output v alid j12 tdo tdi tms tdi input v alid tdi input v alid j13 j9 j10 tms input v alid j9 j10 tms input v alid j1 1 j7 j8 j8 j7 tck j6 j5 j3 j4 j2 t able 24-25. gpio characteristics unit max nom min condition parameter name parameter ns 26 17 - 2-ma drive gpio rise t ime (from 20% to 80% of v dd ) t gpior ns 13 9 4-ma drive ns 9 6 8-ma drive ns 12 10 8-ma drive with slew rate control ns 25 17 - 2-ma drive gpio fall t ime (from 80% to 20% of v dd ) t gpiof ns 12 8 4-ma drive ns 10 6 8-ma drive ns 13 1 1 8-ma drive with slew rate control 24.2.1 1 reset t able 24-26. reset characteristics unit max nom min parameter name parameter parameter no. v - 2.0 - reset threshold v th r1 v 2.95 2.9 2.85 brown-out threshold v bth r2 ms - 10 - power-on reset timeout t por r3 s - 500 - brown-out timeout t bor r4 ms 1 1 - 6 internal reset timeout after por t irpor r5 s 1 - 0 internal reset timeout after bor a t irbor r6 ms 1 - 0 internal reset timeout after hardware reset ( rst pin) t irhwr r7 s 20 - 2.5 internal reset timeout after software-initiated system reset a t irswr r8 s 20 - 2.5 internal reset timeout after watchdog reset a t ir wdr r9 ms 100 - - supply voltage (v dd ) rise time (0v-3.3v) t vddrise r10 s - - 2 minimum rst pulse width t min r1 1 a. 20 * t mosc_per figure 24-1 1. external reset t iming ( rst ) 589 september 02, 2007 preliminary lm3s8962 microcontroller rst /reset ( internal) r7 r1 1 figure 24-12. power-on reset t iming figure 24-13. brown-out reset t iming figure 24-14. software reset t iming figure 24-15. w atchdog reset t iming september 02, 2007 590 preliminary electrical characteristics vdd /por ( internal) /reset ( internal) r3 r1 r5 vdd /bor ( internal) /reset ( internal) r2 r4 r6 r8 sw reset /reset ( internal) wdog reset ( internal) /reset ( internal) r9 25 package information figure 25-1. 100-pin lqfp package note: the following notes apply to the package drawing. 1. all dimensions shown in mm. 2. dimensions shown are nominal with tolerances indicated. 3. foot length 'l' is measured at gage plane 0.25 mm above seating plane. 591 september 02, 2007 preliminary lm3s8962 microcontroller body +2.00 mm footprint, 1.4 mm package thickness 100l leads symbols 1.60 max. a 0.05 min./0.15 max. a 1 1.40 0.05 a 2 16.00 0.20 d 14.00 0.05 d 1 16.00 0.20 e 14.00 0.05 e 1 0.60 0.15/-0.10 l 0.50 basic e 0.22 0.05 b 0?~7? === 0.08 max. ddd 0.08 max. ccc ms-026 jedec reference drawing bed v ariation designator september 02, 2007 592 preliminary package information a serial flash loader a.1 serial flash loader the stellaris ? serial flash loader is a preprogrammed flash-resident utility used to download code to the flash memory of a device without the use of a debug interface. the serial flash loader uses a simple packet interface to provide synchronous communication with the device. the flash loader runs of f the crystal and does not enable the pll, so its speed is determined by the crystal used. the two serial interfaces that can be used are the uar t0 and ssi0 interfaces. for simplicity , both the data format and communication protocol are identical for both serial interfaces. a.2 interfaces once communication with the flash loader is established via one of the serial interfaces, that interface is used until the flash loader is reset or new code takes over . for example, once you start communicating using the ssi port, communications with the flash loader via the uar t are disabled until the device is reset. a.2.1 uart the universal asynchronous receivers/t ransmitters (uar t) communication uses a fixed serial format of 8 bits of data, no parity , and 1 stop bit. the baud rate used for communication is automatically detected by the flash loader and can be any valid baud rate supported by the host and the device. the auto detection sequence requires that the baud rate should be no more than 1/32 the crystal frequency of the board that is running the serial flash loader . this is actually the same as the hardware limitation for the maximum baud rate for any uar t on a stellaris ? device which is calculated as follows: max baud rate = system clock frequency / 16 in order to determine the baud rate, the serial flash loader needs to determine the relationship between its own crystal frequency and the baud rate. this is enough information for the flash loader to configure its uar t to the same baud rate as the host. this automatic baud-rate detection allows the host to use any valid baud rate that it wants to communicate with the device. the method used to perform this automatic synchronization relies on the host sending the flash loader two bytes that are both 0x55. this generates a series of pulses to the flash loader that it can use to calculate the ratios needed to program the uar t to match the host s baud rate. after the host sends the pattern, it attempts to read back one byte of data from the uar t . the flash loader returns the value of 0xcc to indicate successful detection of the baud rate. if this byte is not received after at least twice the time required to transfer the two bytes, the host can resend another pattern of 0x55, 0x55, and wait for the 0xcc byte again until the flash loader acknowledges that it has received a synchronization pattern correctly . for example, the time to wait for data back from the flash loader should be calculated as at least 2*(20(bits/sync)/baud rate (bits/sec)). for a baud rate of 1 15200, this time is 2*(20/1 15200) or 0.35 ms. a.2.2 ssi the synchronous serial interface (ssi) port also uses a fixed serial format for communications, with the framing defined as motorola format with sph set to 1 and spo set to 1. see frame formats on page 340 in the ssi chapter for more information on formats for this transfer protocol. like the uar t , this interface has hardware requirements that limit the maximum speed that the ssi clock can run. this allows the ssi clock to be at most 1/12 the crystal frequency of the board running 593 september 02, 2007 preliminary lm3s8962 microcontroller the flash loader . since the host device is the master , the ssi on the flash loader device does not need to determine the clock as it is provided directly by the host. a.3 packet handling all communications, with the exception of the uar t auto-baud, are done via defined packets that are acknowledged (ack) or not acknowledged (nak) by the devices. the packets use the same format for receiving and sending packets, including the method used to acknowledge successful or unsuccessful reception of a packet. a.3.1 packet format all packets sent and received from the device use the following byte-packed format. struct { unsigned char ucsize; unsigned char ucchecksum; unsigned char data[]; }; ucsize the first byte received holds the total size of the transfer including the size and checksum bytes. ucchecksum this holds a simple checksum of the bytes in the data buf fer only . the algorithm is data[0]+data[1]++ data[ ucsize -3]. data this is the raw data intended for the device, which is formatted in some form of command interface. there should be ucsize C2 bytes of data provided in this buf fer to or from the device. a.3.2 sending packets the actual bytes of the packet can be sent individually or all at once; the only limitation is that commands that cause flash memory access should limit the download sizes to prevent losing bytes during flash programming. this limitation is discussed further in the section that describes the serial flash loader command, command_send_da t a (see command_send_da t a (0x24) on page 596 ). once the packet has been formatted correctly by the host, it should be sent out over the uar t or ssi interface. then the host should poll the uar t or ssi interface for the first non-zero data returned from the device. the first non-zero byte will either be an ack (0xcc) or a nak (0x33) byte from the device indicating the packet was received successfully (ack) or unsuccessfully (nak). this does not indicate that the actual contents of the command issued in the data portion of the packet were valid, just that the packet was received correctly . a.3.3 receiving packets the flash loader sends a packet of data in the same format that it receives a packet. the flash loader may transfer leading zero data before the first actual byte of data is sent out. the first non-zero byte is the size of the packet followed by a checksum byte, and finally followed by the data itself. there is no break in the data after the first non-zero byte is sent from the flash loader . once the device communicating with the flash loader receives all the bytes, it must either ack or nak the packet to indicate that the transmission was successful. the appropriate response after sending a nak to the flash loader is to resend the command that failed and request the data again. if needed, the host may send leading zeros before sending down the ack/nak signal to the flash loader , as the september 02, 2007 594 preliminary serial flash loader flash loader only accepts the first non-zero data as a valid response. this zero padding is needed by the ssi interface in order to receive data to or from the flash loader . a.4 commands the next section defines the list of commands that can be sent to the flash loader . the first byte of the data should always be one of the defined commands, followed by data or parameters as determined by the command that is sent. a.4.1 command_ping (0x20) this command simply accepts the command and sets the global status to success. the format of the packet is as follows: byte[0] = 0x03; byte[1] = checksum(byte[2]); byte[2] = command_ping; the ping command has 3 bytes and the value for command_ping is 0x20 and the checksum of one byte is that same byte, making byte[1] also 0x20. since the ping command has no real return status, the receipt of an ack can be interpreted as a successful ping to the flash loader . a.4.2 command_get_st a tus (0x23) this command returns the status of the last command that was issued. t ypically , this command should be sent after every command to ensure that the previous command was successful or to properly respond to a failure. the command requires one byte in the data of the packet and should be followed by reading a packet with one byte of data that contains a status code. the last step is to ack or nak the received data so the flash loader knows that the data has been read. byte[0] = 0x03 byte[1] = checksum(byte[2]) byte[2] = command_get_status a.4.3 command_download (0x21) this command is sent to the flash loader to indicate where to store data and how many bytes will be sent by the command_send_data commands that follow . the command consists of two 32-bit values that are both transferred msb first. the first 32-bit value is the address to start programming data into, while the second is the 32-bit size of the data that will be sent. this command also triggers an erase of the full area to be programmed so this command takes longer than other commands. this results in a longer time to receive the ack/nak back from the board. this command should be followed by a command_get_status to ensure that the program address and program size are valid for the device running the flash loader . the format of the packet to send this command is a follows: byte[0] = 11 byte[1] = checksum(bytes[2:10]) byte[2] = command_download byte[3] = program address [31:24] byte[4] = program address [23:16] byte[5] = program address [15:8] byte[6] = program address [7:0] byte[7] = program size [31:24] 595 september 02, 2007 preliminary lm3s8962 microcontroller byte[8] = program size [23:16] byte[9] = program size [15:8] byte[10] = program size [7:0] a.4.4 command_send_da t a (0x24) this command should only follow a command_download command or another command_send_data command if more data is needed. consecutive send data commands automatically increment address and continue programming from the previous location. the caller should limit transfers of data to a maximum 8 bytes of packet data to allow the flash to program successfully and not overflow input buf fers of the serial interfaces. the command terminates programming once the number of bytes indicated by the command_download command has been received. each time this function is called it should be followed by a command_get_status to ensure that the data was successfully programmed into the flash. if the flash loader sends a nak to this command, the flash loader does not increment the current address to allow retransmission of the previous data. byte[0] = 11 byte[1] = checksum(bytes[2:10]) byte[2] = command_send_data byte[3] = data[0] byte[4] = data[1] byte[5] = data[2] byte[6] = data[3] byte[7] = data[4] byte[8] = data[5] byte[9] = data[6] byte[10] = data[7] a.4.5 command_run (0x22) this command is used to tell the flash loader to execute from the address passed as the parameter in this command. this command consists of a single 32-bit value that is interpreted as the address to execute. the 32-bit value is transmitted msb first and the flash loader responds with an ack signal back to the host device before actually executing the code at the given address. this allows the host to know that the command was received successfully and the code is now running. byte[0] = 7 byte[1] = checksum(bytes[2:6]) byte[2] = command_run byte[3] = execute address[31:24] byte[4] = execute address[23:16] byte[5] = execute address[15:8] byte[6] = execute address[7:0] a.4.6 command_reset (0x25) this command is used to tell the flash loader device to reset. this is useful when downloading a new image that overwrote the flash loader and wants to start from a full reset. unlike the command_run command, this allows the initial stack pointer to be read by the hardware and set up for the new code. it can also be used to reset the flash loader if a critical error occurs and the host device wants to restart communication with the flash loader . september 02, 2007 596 preliminary serial flash loader byte[0] = 3 byte[1] = checksum(byte[2]) byte[2] = command_reset the flash loader responds with an ack signal back to the host device before actually executing the software reset to the device running the flash loader . this allows the host to know that the command was received successfully and the part will be reset. 597 september 02, 2007 preliminary lm3s8962 microcontroller b register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 system control base 0x400f .e000 did0, type ro, offset 0x000, reset - class ver minor major pborctl, type r/w , offset 0x030, reset 0x0000.7ffd borior ldopctl, type r/w , offset 0x034, reset 0x0000.0000 v adj ris, type ro, offset 0x050, reset 0x0000.0000 borris plllris imc, type r/w , offset 0x054, reset 0x0000.0000 borim plllim misc, type r/w1c, offset 0x058, reset 0x0000.0000 bormis plllmis resc, type r/w , offset 0x05c, reset - ext por bor wdt sw ldo rcc, type r/w , offset 0x060, reset 0x07ae.3ad1 pwmdiv usepwmdiv usesysdiv sysdiv acg moscdis ioscdis oscsrc xt al byp ass pwrdn pllcfg, type ro, offset 0x064, reset - r f od rcc2, type r/w , offset 0x070, reset 0x0780.2800 sysdiv2 usercc2 oscsrc2 byp ass2 pwrdn2 dslpclkcfg, type r/w , offset 0x144, reset 0x0780.0000 dsdivoride dsoscsrc did1, type ro, offset 0x004, reset - p ar tno f am ver qual rohs pkg temp pincount dc0, type ro, offset 0x008, reset 0x00ff .007f sramsz flashsz dc1, type ro, offset 0x010, reset 0x01 1 1.32ff adc pwm can0 jt ag swd swo wdt pll tempsns hib mpu maxadcspd minsysdiv dc2, type ro, offset 0x014, reset 0x010f .1313 timer0 timer1 timer2 timer3 comp0 uar t0 uar t1 ssi0 qei0 qei1 i2c0 dc3, type ro, offset 0x018, reset 0x030f .81ff adc0 adc1 adc2 adc3 ccp0 ccp1 pwm0 pwm1 pwm2 pwm3 pwm4 pwm5 c0minus c0plus c0o pwmf aul t september 02, 2007 598 preliminary register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 dc4, type ro, offset 0x01c, reset 0x5100.007f e1588 emac0 ephy0 gpioa gpiob gpioc gpiod gpioe gpiof gpiog rcgc0, type r/w , offset 0x100, reset 0x00000040 adc pwm can0 wdt hib maxadcspd scgc0, type r/w , offset 0x1 10, reset 0x00000040 adc pwm can0 wdt hib maxadcspd dcgc0, type r/w , offset 0x120, reset 0x00000040 adc pwm can0 wdt hib maxadcspd rcgc1, type r/w , offset 0x104, reset 0x00000000 timer0 timer1 timer2 timer3 comp0 uar t0 uar t1 ssi0 qei0 qei1 i2c0 scgc1, type r/w , offset 0x1 14, reset 0x00000000 timer0 timer1 timer2 timer3 comp0 uar t0 uar t1 ssi0 qei0 qei1 i2c0 dcgc1, type r/w , offset 0x124, reset 0x00000000 timer0 timer1 timer2 timer3 comp0 uar t0 uar t1 ssi0 qei0 qei1 i2c0 rcgc2, type r/w , offset 0x108, reset 0x00000000 emac0 ephy0 gpioa gpiob gpioc gpiod gpioe gpiof gpiog scgc2, type r/w , offset 0x1 18, reset 0x00000000 emac0 ephy0 gpioa gpiob gpioc gpiod gpioe gpiof gpiog dcgc2, type r/w , offset 0x128, reset 0x00000000 emac0 ephy0 gpioa gpiob gpioc gpiod gpioe gpiof gpiog srcr0, type r/w , offset 0x040, reset 0x00000000 adc pwm can0 wdt hib srcr1, type r/w , offset 0x044, reset 0x00000000 timer0 timer1 timer2 timer3 comp0 uar t0 uar t1 ssi0 qei0 qei1 i2c0 srcr2, type r/w , offset 0x048, reset 0x00000000 emac0 ephy0 gpioa gpiob gpioc gpiod gpioe gpiof gpiog hibernation module base 0x400f .c000 hibrtcc, type ro, offset 0x000, reset 0x0000.0000 r tcc r tcc hibrtcm0, type r/w , offset 0x004, reset 0xffff .ffff r tcm0 r tcm0 hibrtcm1, type r/w , offset 0x008, reset 0xffff .ffff r tcm1 r tcm1 hibrtcld, type r/w , offset 0x00c, reset 0xffff .ffff r tcld r tcld 599 september 02, 2007 preliminary lm3s8962 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 hibctl, type r/w , offset 0x010, reset 0x0000.0000 r tcen hibreq clksel r tcwen pinwen lowba ten clk32en v abor t hibim, type r/w , offset 0x014, reset 0x0000.0000 r tcal t0 r tcal t1 lowba t extw hibris, type ro, offset 0x018, reset 0x0000.0000 r tcal t0 r tcal t1 lowba t extw hibmis, type ro, offset 0x01c, reset 0x0000.0000 r tcal t0 r tcal t1 lowba t extw hibic, type r/w1c, offset 0x020, reset 0x0000.0000 r tcal t0 r tcal t1 lowba t extw hibrtct , type r/w , offset 0x024, reset 0x0000.7fff trim hibda t a, type r/w , offset 0x030-0x12c, reset 0x0000.0000 r td r td internal memory flash control offset base 0x400f .d000 fma, type r/w , offset 0x000, reset 0x0000.0000 offset offset fmd, type r/w , offset 0x004, reset 0x0000.0000 da t a da t a fmc, type r/w , offset 0x008, reset 0x0000.0000 wrkey write erase merase comt fcris, type ro, offset 0x00c, reset 0x0000.0000 aris pris fcim, type r/w , offset 0x010, reset 0x0000.0000 amask pmask fcmisc, type r/w1c, offset 0x014, reset 0x0000.0000 amisc pmisc internal memory system control offset base 0x400f .e000 usecrl, type r/w , offset 0x140, reset 0x31 usec fmpre0, type r/w , offset 0x130 and 0x200, reset 0xffff .ffff read_enable read_enable september 02, 2007 600 preliminary register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 fmppe0, type r/w , offset 0x134 and 0x400, reset 0xffff .ffff prog_enable prog_enable user_dbg, type r/w , offset 0x1d0, reset 0xffff .fffe da t a nw dbg0 dbg1 da t a user_reg0, type r/w , offset 0x1e0, reset 0xffff .ffff da t a nw da t a user_reg1, type r/w , offset 0x1e4, reset 0xffff .ffff da t a nw da t a fmpre1, type r/w , offset 0x204, reset 0xffff .ffff read_enable read_enable fmpre2, type r/w , offset 0x208, reset 0xffff .ffff read_enable read_enable fmpre3, type r/w , offset 0x20c, reset 0xffff .ffff read_enable read_enable fmppe1, type r/w , offset 0x404, reset 0xffff .ffff prog_enable prog_enable fmppe2, type r/w , offset 0x408, reset 0xffff .ffff prog_enable prog_enable fmppe3, type r/w , offset 0x40c, reset 0xffff .ffff prog_enable prog_enable general-purpose input/outputs (gpios) gpio port a base: 0x4000.4000 gpio port b base: 0x4000.5000 gpio port c base: 0x4000.6000 gpio port d base: 0x4000.7000 gpio port e base: 0x4002.4000 gpio port f base: 0x4002.5000 gpio port g base: 0x4002.6000 gpioda t a, type r/w , offset 0x000, reset 0x0000.0000 da t a gpiodir, type r/w , offset 0x400, reset 0x0000.0000 dir gpiois, type r/w , offset 0x404, reset 0x0000.0000 is gpioibe, type r/w , offset 0x408, reset 0x0000.0000 ibe gpioiev , type r/w , offset 0x40c, reset 0x0000.0000 iev 601 september 02, 2007 preliminary lm3s8962 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 gpioim, type r/w , offset 0x410, reset 0x0000.0000 ime gpioris, type ro, offset 0x414, reset 0x0000.0000 ris gpiomis, type ro, offset 0x418, reset 0x0000.0000 mis gpioicr, type w1c, offset 0x41c, reset 0x0000.0000 ic gpioafsel, type r/w , offset 0x420, reset - afsel gpiodr2r, type r/w , offset 0x500, reset 0x0000.00ff dr v2 gpiodr4r, type r/w , offset 0x504, reset 0x0000.0000 dr v4 gpiodr8r, type r/w , offset 0x508, reset 0x0000.0000 dr v8 gpioodr, type r/w , offset 0x50c, reset 0x0000.0000 ode gpiopur, type r/w , offset 0x510, reset - pue gpiopdr, type r/w , offset 0x514, reset 0x0000.0000 pde gpioslr, type r/w , offset 0x518, reset 0x0000.0000 srl gpioden, type r/w , offset 0x51c, reset - den gpiolock, type r/w , offset 0x520, reset 0x0000.0001 lock lock gpiocr, type -, offset 0x524, reset - cr gpioperiphid4, type ro, offset 0xfd0, reset 0x0000.0000 pid4 gpioperiphid5, type ro, offset 0xfd4, reset 0x0000.0000 pid5 september 02, 2007 602 preliminary register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 gpioperiphid6, type ro, offset 0xfd8, reset 0x0000.0000 pid6 gpioperiphid7, type ro, offset 0xfdc, reset 0x0000.0000 pid7 gpioperiphid0, type ro, offset 0xfe0, reset 0x0000.0061 pid0 gpioperiphid1, type ro, offset 0xfe4, reset 0x0000.0000 pid1 gpioperiphid2, type ro, offset 0xfe8, reset 0x0000.0018 pid2 gpioperiphid3, type ro, offset 0xfec, reset 0x0000.0001 pid3 gpiopcellid0, type ro, offset 0xff0, reset 0x0000.000d cid0 gpiopcellid1, type ro, offset 0xff4, reset 0x0000.00f0 cid1 gpiopcellid2, type ro, offset 0xff8, reset 0x0000.0005 cid2 gpiopcellid3, type ro, offset 0xffc, reset 0x0000.00b1 cid3 general-purpose t imers t imer0 base: 0x4003.0000 t imer1 base: 0x4003.1000 t imer2 base: 0x4003.2000 t imer3 base: 0x4003.3000 gptmcfg, type r/w , offset 0x000, reset 0x0000.0000 gptmcfg gptmt amr, type r/w , offset 0x004, reset 0x0000.0000 t amr t acmr t aams gptmtbmr, type r/w , offset 0x008, reset 0x0000.0000 tbmr tbcmr tbams gptmctl, type r/w , offset 0x00c, reset 0x0000.0000 t aen t ast all t aevent r tcen t aote t apwml tben tbst all tbevent tbote tbpwml gptmimr, type r/w , offset 0x018, reset 0x0000.0000 t a t oim camim caeim r tcim tbt oim cbmim cbeim gptmris, type ro, offset 0x01c, reset 0x0000.0000 t a t oris camris caeris r tcris tbt oris cbmris cberis 603 september 02, 2007 preliminary lm3s8962 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 gptmmis, type ro, offset 0x020, reset 0x0000.0000 t a t omis cammis caemis r tcmis tbt omis cbmmis cbemis gptmicr, type w1c, offset 0x024, reset 0x0000.0000 t a t ocint camcint caecint r tccint tbt ocint cbmcint cbecint gptmt ailr, type r/w , offset 0x028, reset 0x0000.ffff (16-bit mode) and 0xffff .ffff (32-bit mode) t ailrh t ailrl gptmtbilr, type r/w , offset 0x02c, reset 0x0000.ffff tbilrl gptmt ama tchr, type r/w , offset 0x030, reset 0x0000.ffff (16-bit mode) and 0xffff .ffff (32-bit mode) t amrh t amrl gptmtbma tchr, type r/w , offset 0x034, reset 0x0000.ffff tbmrl gptmt apr, type r/w , offset 0x038, reset 0x0000.0000 t apsr gptmtbpr, type r/w , offset 0x03c, reset 0x0000.0000 tbpsr gptmt apmr, type r/w , offset 0x040, reset 0x0000.0000 t apsmr gptmtbpmr, type r/w , offset 0x044, reset 0x0000.0000 tbpsmr gptmt ar, type ro, offset 0x048, reset 0x0000.ffff (16-bit mode) and 0xffff .ffff (32-bit mode) t arh t arl gptmtbr, type ro, offset 0x04c, reset 0x0000.ffff tbrl w atchdog t imer base 0x4000.0000 wdtload, type r/w , offset 0x000, reset 0xffff .ffff wdtload wdtload wdtv alue, type ro, offset 0x004, reset 0xffff .ffff wdtv alue wdtv alue wdtctl, type r/w , offset 0x008, reset 0x0000.0000 inten resen wdticr, type wo, offset 0x00c, reset - wdtintclr wdtintclr wdtris, type ro, offset 0x010, reset 0x0000.0000 wdtris september 02, 2007 604 preliminary register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 wdtmis, type ro, offset 0x014, reset 0x0000.0000 wdtmis wdttest , type r/w , offset 0x418, reset 0x0000.0000 st all wdtlock, type r/w , offset 0xc00, reset 0x0000.0000 wdtlock wdtlock wdtperiphid4, type ro, offset 0xfd0, reset 0x0000.0000 pid4 wdtperiphid5, type ro, offset 0xfd4, reset 0x0000.0000 pid5 wdtperiphid6, type ro, offset 0xfd8, reset 0x0000.0000 pid6 wdtperiphid7, type ro, offset 0xfdc, reset 0x0000.0000 pid7 wdtperiphid0, type ro, offset 0xfe0, reset 0x0000.0005 pid0 wdtperiphid1, type ro, offset 0xfe4, reset 0x0000.0018 pid1 wdtperiphid2, type ro, offset 0xfe8, reset 0x0000.0018 pid2 wdtperiphid3, type ro, offset 0xfec, reset 0x0000.0001 pid3 wdtpcellid0, type ro, offset 0xff0, reset 0x0000.000d cid0 wdtpcellid1, type ro, offset 0xff4, reset 0x0000.00f0 cid1 wdtpcellid2, type ro, offset 0xff8, reset 0x0000.0005 cid2 wdtpcellid3, type ro, offset 0xffc, reset 0x0000.00b1 cid3 analog-to-digital converter (adc) base 0x4003.8000 adcactss, type r/w , offset 0x000, reset 0x0000.0000 asen0 asen1 asen2 asen3 adcris, type ro, offset 0x004, reset 0x0000.0000 inr0 inr1 inr2 inr3 605 september 02, 2007 preliminary lm3s8962 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 adcim, type r/w , offset 0x008, reset 0x0000.0000 mask0 mask1 mask2 mask3 adcisc, type r/w1c, offset 0x00c, reset 0x0000.0000 in0 in1 in2 in3 adcost a t , type r/w1c, offset 0x010, reset 0x0000.0000 ov0 ov1 ov2 ov3 adcemux, type r/w , offset 0x014, reset 0x0000.0000 em0 em1 em2 em3 adcust a t , type r/w1c, offset 0x018, reset 0x0000.0000 uv0 uv1 uv2 uv3 adcsspri, type r/w , offset 0x020, reset 0x0000.3210 ss0 ss1 ss2 ss3 adcpssi, type wo, offset 0x028, reset - ss0 ss1 ss2 ss3 adcsac, type r/w , offset 0x030, reset 0x0000.0000 a vg adcssmux0, type r/w , offset 0x040, reset 0x0000.0000 mux4 mux5 mux6 mux7 mux0 mux1 mux2 mux3 adcssctl0, type r/w , offset 0x044, reset 0x0000.0000 d4 end4 ie4 ts4 d5 end5 ie5 ts5 d6 end6 ie6 ts6 d7 end7 ie7 ts7 d0 end0 ie0 ts0 d1 end1 ie1 ts1 d2 end2 ie2 ts2 d3 end3 ie3 ts3 adcssfifo0, type ro, offset 0x048, reset 0x0000.0000 da t a adcssfifo1, type ro, offset 0x068, reset 0x0000.0000 da t a adcssfifo2, type ro, offset 0x088, reset 0x0000.0000 da t a adcssfifo3, type ro, offset 0x0a8, reset 0x0000.0000 da t a adcssfst a t0, type ro, offset 0x04c, reset 0x0000.0100 tptr hptr empty full adcssfst a t1, type ro, offset 0x06c, reset 0x0000.0100 tptr hptr empty full adcssfst a t2, type ro, offset 0x08c, reset 0x0000.0100 tptr hptr empty full september 02, 2007 606 preliminary register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 adcssfst a t3, type ro, offset 0x0ac, reset 0x0000.0100 tptr hptr empty full adcssmux1, type ro, offset 0x060, reset 0x0000.0000 mux0 mux1 mux2 mux3 adcssmux2, type ro, offset 0x080, reset 0x0000.0000 mux0 mux1 mux2 mux3 adcssctl1, type ro, offset 0x064, reset 0x0000.0000 d0 end0 ie0 ts0 d1 end1 ie1 ts1 d2 end2 ie2 ts2 d3 end3 ie3 ts3 adcssctl2, type ro, offset 0x084, reset 0x0000.0000 d0 end0 ie0 ts0 d1 end1 ie1 ts1 d2 end2 ie2 ts2 d3 end3 ie3 ts3 adcssmux3, type r/w , offset 0x0a0, reset 0x0000.0000 mux0 adcssctl3, type r/w , offset 0x0a4, reset 0x0000.0002 d0 end0 ie0 ts0 adctmlb, type ro, offset 0x100, reset 0x0000.0000 mux ts diff cont cnt adctmlb, type wo, offset 0x100, reset 0x0000.0000 lb universal asynchronous receivers/t ransmitters (uart s) uar t0 base: 0x4000.c000 uar t1 base: 0x4000.d000 uartdr, type r/w , offset 0x000, reset 0x0000.0000 da t a fe pe be oe uartrsr/uartecr, type ro, offset 0x004, reset 0x0000.0000 fe pe be oe uartrsr/uartecr, type wo, offset 0x004, reset 0x0000.0000 da t a uartfr, type ro, offset 0x018, reset 0x0000.0090 busy rxfe txff rxff txfe uartilpr, type r/w , offset 0x020, reset 0x0000.0000 ilpdvsr uartibrd, type r/w , offset 0x024, reset 0x0000.0000 divint uartfbrd, type r/w , offset 0x028, reset 0x0000.0000 divfrac 607 september 02, 2007 preliminary lm3s8962 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 uartlcrh, type r/w , offset 0x02c, reset 0x0000.0000 brk pen eps stp2 fen wlen sps uartctl, type r/w , offset 0x030, reset 0x0000.0300 uar ten siren sirlp lbe txe rxe uartifls, type r/w , offset 0x034, reset 0x0000.0012 txiflsel rxiflsel uartim, type r/w , offset 0x038, reset 0x0000.0000 rxim txim r tim feim peim beim oeim uartris, type ro, offset 0x03c, reset 0x0000.000f rxris txris r tris feris peris beris oeris uartmis, type ro, offset 0x040, reset 0x0000.0000 rxmis txmis r tmis femis pemis bemis oemis uarticr, type w1c, offset 0x044, reset 0x0000.0000 rxic txic r tic feic peic beic oeic uartperiphid4, type ro, offset 0xfd0, reset 0x0000.0000 pid4 uartperiphid5, type ro, offset 0xfd4, reset 0x0000.0000 pid5 uartperiphid6, type ro, offset 0xfd8, reset 0x0000.0000 pid6 uartperiphid7, type ro, offset 0xfdc, reset 0x0000.0000 pid7 uartperiphid0, type ro, offset 0xfe0, reset 0x0000.001 1 pid0 uartperiphid1, type ro, offset 0xfe4, reset 0x0000.0000 pid1 uartperiphid2, type ro, offset 0xfe8, reset 0x0000.0018 pid2 uartperiphid3, type ro, offset 0xfec, reset 0x0000.0001 pid3 uartpcellid0, type ro, offset 0xff0, reset 0x0000.000d cid0 uartpcellid1, type ro, offset 0xff4, reset 0x0000.00f0 cid1 september 02, 2007 608 preliminary register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 uartpcellid2, type ro, offset 0xff8, reset 0x0000.0005 cid2 uartpcellid3, type ro, offset 0xffc, reset 0x0000.00b1 cid3 synchronous serial interface (ssi) ssi0 base: 0x4000.8000 ssicr0, type r/w , offset 0x000, reset 0x0000.0000 dss frf spo sph scr ssicr1, type r/w , offset 0x004, reset 0x0000.0000 lbm sse ms sod ssidr, type r/w , offset 0x008, reset 0x0000.0000 da t a ssisr, type ro, offset 0x00c, reset 0x0000.0003 tfe tnf rne rff bsy ssicpsr, type r/w , offset 0x010, reset 0x0000.0000 cpsdvsr ssiim, type r/w , offset 0x014, reset 0x0000.0000 rorim r tim rxim txim ssiris, type ro, offset 0x018, reset 0x0000.0008 rorris r tris rxris txris ssimis, type ro, offset 0x01c, reset 0x0000.0000 rormis r tmis rxmis txmis ssiicr, type w1c, offset 0x020, reset 0x0000.0000 roric r tic ssiperiphid4, type ro, offset 0xfd0, reset 0x0000.0000 pid4 ssiperiphid5, type ro, offset 0xfd4, reset 0x0000.0000 pid5 ssiperiphid6, type ro, offset 0xfd8, reset 0x0000.0000 pid6 ssiperiphid7, type ro, offset 0xfdc, reset 0x0000.0000 pid7 ssiperiphid0, type ro, offset 0xfe0, reset 0x0000.0022 pid0 ssiperiphid1, type ro, offset 0xfe4, reset 0x0000.0000 pid1 609 september 02, 2007 preliminary lm3s8962 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 ssiperiphid2, type ro, offset 0xfe8, reset 0x0000.0018 pid2 ssiperiphid3, type ro, offset 0xfec, reset 0x0000.0001 pid3 ssipcellid0, type ro, offset 0xff0, reset 0x0000.000d cid0 ssipcellid1, type ro, offset 0xff4, reset 0x0000.00f0 cid1 ssipcellid2, type ro, offset 0xff8, reset 0x0000.0005 cid2 ssipcellid3, type ro, offset 0xffc, reset 0x0000.00b1 cid3 inter-integrated circuit (i 2 c) interface i 2 c master i2c master 0 base: 0x4002.0000 i2cmsa, type r/w , offset 0x000, reset 0x0000.0000 r/s sa i2cmcs, type ro, offset 0x004, reset 0x0000.0000 busy error adrack da t ack arblst idle busbsy i2cmcs, type wo, offset 0x004, reset 0x0000.0000 run st ar t st op ack i2cmdr, type r/w , offset 0x008, reset 0x0000.0000 da t a i2cmtpr, type r/w , offset 0x00c, reset 0x0000.0001 tpr i2cmimr, type r/w , offset 0x010, reset 0x0000.0000 im i2cmris, type ro, offset 0x014, reset 0x0000.0000 ris i2cmmis, type ro, offset 0x018, reset 0x0000.0000 mis i2cmicr, type wo, offset 0x01c, reset 0x0000.0000 ic i2cmcr, type r/w , offset 0x020, reset 0x0000.0000 lpbk mfe sfe inter-integrated circuit (i 2 c) interface september 02, 2007 610 preliminary register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 i 2 c slave i2c slave 0 base: 0x4002.0800 i2csoar, type r/w , offset 0x000, reset 0x0000.0000 oar i2cscsr, type ro, offset 0x004, reset 0x0000.0000 rreq treq fbr i2cscsr, type wo, offset 0x004, reset 0x0000.0000 da i2csdr, type r/w , offset 0x008, reset 0x0000.0000 da t a i2csimr, type r/w , offset 0x00c, reset 0x0000.0000 im i2csris, type ro, offset 0x010, reset 0x0000.0000 ris i2csmis, type ro, offset 0x014, reset 0x0000.0000 mis i2csicr, type wo, offset 0x018, reset 0x0000.0000 ic controller area network (can) module can0 base: 0x4004.0000 canctl, type r/w , offset 0x000, reset 0x0000.0001 init ie sie eie dar cce t est cansts, type r/w , offset 0x004, reset 0x0000.0000 lec txok rxok epass ew arn bof f canerr, type ro, offset 0x008, reset 0x0000.0000 tec rec rp canbit , type r/w , offset 0x00c, reset 0x0000.2301 brp sjw tseg1 tseg2 canint , type ro, offset 0x010, reset 0x0000.0000 intid cantst , type r/w , offset 0x014, reset 0x0000.0000 basic silent lback tx rx canbrpe, type r/w , offset 0x018, reset 0x0000.0000 brpe canif1crq, type ro, offset 0x020, reset 0x0000.0001 mnum busy 61 1 september 02, 2007 preliminary lm3s8962 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 canif2crq, type ro, offset 0x080, reset 0x0000.0001 mnum busy canif1cmsk, type ro, offset 0x024, reset 0x0000.0000 datab dataa txrqst/newdat clrintpnd control arb mask wrnrd canif2cmsk, type ro, offset 0x084, reset 0x0000.0000 datab dataa txrqst/newdat clrintpnd control arb mask wrnrd canif1msk1, type ro, offset 0x028, reset 0x0000.ffff msk canif2msk1, type ro, offset 0x088, reset 0x0000.ffff msk canif1msk2, type ro, offset 0x02c, reset 0x0000.ffff msk mdir mxtd canif2msk2, type ro, offset 0x08c, reset 0x0000.ffff msk mdir mxtd canif1arb1, type ro, offset 0x030, reset 0x0000.0000 id canif2arb1, type ro, offset 0x090, reset 0x0000.0000 id canif1arb2, type ro, offset 0x034, reset 0x0000.0000 id dir xtd msgv al canif2arb2, type ro, offset 0x094, reset 0x0000.0000 id dir xtd msgv al canif1mctl, type ro, offset 0x038, reset 0x0000.0000 dlc eob txrqst rmten rxie txie umask intpnd msglst newdat canif2mctl, type ro, offset 0x098, reset 0x0000.0000 dlc eob txrqst rmten rxie txie umask intpnd msglst newdat canif1da1, type r/w , offset 0x03c, reset 0x0000.0000 data canif1da2, type r/w , offset 0x040, reset 0x0000.0000 data canif1db1, type r/w , offset 0x044, reset 0x0000.0000 data canif1db2, type r/w , offset 0x048, reset 0x0000.0000 data september 02, 2007 612 preliminary register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 canif2da1, type r/w , offset 0x09c, reset 0x0000.0000 data canif2da2, type r/w , offset 0x0a0, reset 0x0000.0000 data canif2db1, type r/w , offset 0x0a4, reset 0x0000.0000 data canif2db2, type r/w , offset 0x0a8, reset 0x0000.0000 data cantxrq1, type ro, offset 0x100, reset 0x0000.0000 txrqst cantxrq2, type ro, offset 0x104, reset 0x0000.0000 txrqst cannwda1, type ro, offset 0x120, reset 0x0000.0000 newdat cannwda2, type ro, offset 0x124, reset 0x0000.0000 newdat canmsg1int , type ro, offset 0x140, reset 0x0000.0000 intpnd canmsg2int , type ro, offset 0x144, reset 0x0000.0000 intpnd canmsg1v al, type ro, offset 0x160, reset 0x0000.0000 msgv al canmsg2v al, type ro, offset 0x164, reset 0x0000.0000 msgv al ethernet controller ethernet mac base 0x4004.8000 macris, type ro, offset 0x000, reset 0x0000.0000 rxint txer txemp fov rxer mdint phyint maciack, type w1c, offset 0x000, reset 0x0000.0000 rxint txer txemp fov rxer mdint phyint macim, type r/w , offset 0x004, reset 0x0000.007f rxintm txerm txempm fovm rxerm mdintm phyintm macrctl, type r/w , offset 0x008, reset 0x0000.0008 rxen amul prms badcrc rstfifo 613 september 02, 2007 preliminary lm3s8962 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 mactctl, type r/w , offset 0x00c, reset 0x0000.0000 txen p aden crc duplex macda t a, type ro, offset 0x010, reset 0x0000.0000 rxda t a rxda t a macda t a, type wo, offset 0x010, reset 0x0000.0000 txda t a txda t a macia0, type r/w , offset 0x014, reset 0x0000.0000 macoct3 macoct4 macoct1 macoct2 macia1, type r/w , offset 0x018, reset 0x0000.0000 macoct5 macoct6 macthr, type r/w , offset 0x01c, reset 0x0000.003f thresh macmctl, type r/w , offset 0x020, reset 0x0000.0000 st ar t write regadr macmdv , type r/w , offset 0x024, reset 0x0000.0080 div macmtxd, type r/w , offset 0x02c, reset 0x0000.0000 mdtx macmrxd, type r/w , offset 0x030, reset 0x0000.0000 mdrx macnp , type ro, offset 0x034, reset 0x0000.0000 npr mactr, type r/w , offset 0x038, reset 0x0000.0000 newtx macts, type r/w , offset 0x03c, reset 0x0000.0000 tsen ethernet controller mii management base 0x4004.8000 mr0, type r/w , address 0x00, reset 0x3100 col t duplex raneg iso pwrdn anegen speedsl loopbk reset mr1, type ro, address 0x01, reset 0x7849 extd jab link anega rf aul t anegc mfps 10t_h 10t_f 100x_h 100x_f mr2, type ro, address 0x02, reset 0x000e oui[21:6] mr3, type ro, address 0x03, reset 0x7237 rn mn oui[5:0] mr4, type r/w , address 0x04, reset 0x01e1 s[4:0] a0 a1 a2 a3 rf np september 02, 2007 614 preliminary register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 mr5, type ro, address 0x05, reset 0x0000 s[4:0] a[7:0] rf ack np mr6, type ro, address 0x06, reset 0x0000 lp anega prx lpnp a pdf mr16, type r/w , address 0x10, reset 0x0140 rxcc pcsbp r vspol apol nl10 sqei txhim inpol rptr mr17, type r/w , address 0x1 1, reset 0x0000 anegcomp_int rf aul t_int lschg_int lp ack_int pdf_int prx_int rxer_int jabber_int anegcomp_ie rf aul t_ie lschg_ie lp ack_ie pdf_ie prx_ie rxer_ie jabber_ie mr18, type ro, address 0x12, reset 0x0000 rx_lock rxsd ra te dplx anegf mr19, type r/w , address 0x13, reset 0x4000 txo[1:0] mr23, type r/w , address 0x17, reset 0x0010 led0[3:0] led1[3:0] mr24, type r/w , address 0x18, reset 0x00c0 mdix_sd mdix_cm mdix aut o_sw pd_mode analog comparator base 0x4003.c000 acmis, type r/w1c, offset 0x00, reset 0x0000.0000 in0 acris, type ro, offset 0x04, reset 0x0000.0000 in0 acinten, type r/w , offset 0x08, reset 0x0000.0000 in0 acrefctl, type r/w , offset 0x10, reset 0x0000.0000 vref rng en acst a t0, type ro, offset 0x20, reset 0x0000.0000 ov al acctl0, type r/w , offset 0x24, reset 0x0000.0000 cinv isen isl v al tsen tsl v al asrcp t oen pulse w idth modulator (pwm) base 0x4002.8000 pwmctl, type r/w , offset 0x000, reset 0x0000.0000 globalsync0 globalsync1 globalsync2 pwmsync, type r/w , offset 0x004, reset 0x0000.0000 sync0 sync1 sync2 pwmenable, type r/w , offset 0x008, reset 0x0000.0000 pwm0en pwm1en pwm2en pwm3en pwm4en pwm5en pwminvert , type r/w , offset 0x00c, reset 0x0000.0000 pwm0inv pwm1inv pwm2inv pwm3inv pwm4inv pwm5inv 615 september 02, 2007 preliminary lm3s8962 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pwmf aul t , type r/w , offset 0x010, reset 0x0000.0000 fault0 fault1 fault2 fault3 fault4 fault5 pwminten, type r/w , offset 0x014, reset 0x0000.0000 intfault intpwm0 intpwm1 intpwm2 pwmris, type ro, offset 0x018, reset 0x0000.0000 intfault intpwm0 intpwm1 intpwm2 pwmisc, type r/w1c, offset 0x01c, reset 0x0000.0000 intfault intpwm0 intpwm1 intpwm2 pwmst a tus, type ro, offset 0x020, reset 0x0000.0000 fault pwm0ctl, type r/w , offset 0x040, reset 0x0000.0000 enable mode debug loadupd cmpaupd cmpbupd pwm1ctl, type r/w , offset 0x080, reset 0x0000.0000 enable mode debug loadupd cmpaupd cmpbupd pwm2ctl, type r/w , offset 0x0c0, reset 0x0000.0000 enable mode debug loadupd cmpaupd cmpbupd pwm0inten, type r/w , offset 0x044, reset 0x0000.0000 intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd t rcntzero t rcntload t rcmpau t rcmpad t rcmpbu t rcmpbd pwm1inten, type r/w , offset 0x084, reset 0x0000.0000 intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd t rcntzero t rcntload t rcmpau t rcmpad t rcmpbu t rcmpbd pwm2inten, type r/w , offset 0x0c4, reset 0x0000.0000 intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd t rcntzero t rcntload t rcmpau t rcmpad t rcmpbu t rcmpbd pwm0ris, type ro, offset 0x048, reset 0x0000.0000 intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd pwm1ris, type ro, offset 0x088, reset 0x0000.0000 intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd pwm2ris, type ro, offset 0x0c8, reset 0x0000.0000 intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd pwm0isc, type r/w1c, offset 0x04c, reset 0x0000.0000 intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd pwm1isc, type r/w1c, offset 0x08c, reset 0x0000.0000 intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd pwm2isc, type r/w1c, offset 0x0cc, reset 0x0000.0000 intcntzero intcntload intcmpau intcmpad intcmpbu intcmpbd september 02, 2007 616 preliminary register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pwm0load, type r/w , offset 0x050, reset 0x0000.0000 load pwm1load, type r/w , offset 0x090, reset 0x0000.0000 load pwm2load, type r/w , offset 0x0d0, reset 0x0000.0000 load pwm0count , type ro, offset 0x054, reset 0x0000.0000 count pwm1count , type ro, offset 0x094, reset 0x0000.0000 count pwm2count , type ro, offset 0x0d4, reset 0x0000.0000 count pwm0cmp a, type r/w , offset 0x058, reset 0x0000.0000 compa pwm1cmp a, type r/w , offset 0x098, reset 0x0000.0000 compa pwm2cmp a, type r/w , offset 0x0d8, reset 0x0000.0000 compa pwm0cmpb, type r/w , offset 0x05c, reset 0x0000.0000 compb pwm1cmpb, type r/w , offset 0x09c, reset 0x0000.0000 compb pwm2cmpb, type r/w , offset 0x0dc, reset 0x0000.0000 compb pwm0gena, type r/w , offset 0x060, reset 0x0000.0000 actzero actload actcmpau actcmpad actcmpbu actcmpbd pwm1gena, type r/w , offset 0x0a0, reset 0x0000.0000 actzero actload actcmpau actcmpad actcmpbu actcmpbd pwm2gena, type r/w , offset 0x0e0, reset 0x0000.0000 actzero actload actcmpau actcmpad actcmpbu actcmpbd pwm0genb, type r/w , offset 0x064, reset 0x0000.0000 actzero actload actcmpau actcmpad actcmpbu actcmpbd pwm1genb, type r/w , offset 0x0a4, reset 0x0000.0000 actzero actload actcmpau actcmpad actcmpbu actcmpbd 617 september 02, 2007 preliminary lm3s8962 microcontroller 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 pwm2genb, type r/w , offset 0x0e4, reset 0x0000.0000 actzero actload actcmpau actcmpad actcmpbu actcmpbd pwm0dbctl, type r/w , offset 0x068, reset 0x0000.0000 enable pwm1dbctl, type r/w , offset 0x0a8, reset 0x0000.0000 enable pwm2dbctl, type r/w , offset 0x0e8, reset 0x0000.0000 enable pwm0dbrise, type r/w , offset 0x06c, reset 0x0000.0000 risedelay pwm1dbrise, type r/w , offset 0x0ac, reset 0x0000.0000 risedelay pwm2dbrise, type r/w , offset 0x0ec, reset 0x0000.0000 risedelay pwm0dbf all, type r/w , offset 0x070, reset 0x0000.0000 falldelay pwm1dbf all, type r/w , offset 0x0b0, reset 0x0000.0000 falldelay pwm2dbf all, type r/w , offset 0x0f0, reset 0x0000.0000 falldelay quadrature encoder interface (qei) qei0 base: 0x4002.c000 qei1 base: 0x4002.d000 qeictl, type r/w , offset 0x000, reset 0x0000.0000 enable swap sigmode capmode resmode v elen v eldiv inv a invb invi st allen qeist a t , type ro, offset 0x004, reset 0x0000.0000 error direction qeipos, type r/w , offset 0x008, reset 0x0000.0000 position position qeimaxpos, type r/w , offset 0x00c, reset 0x0000.0000 maxpos maxpos qeiload, type r/w , offset 0x010, reset 0x0000.0000 load load qeitime, type ro, offset 0x014, reset 0x0000.0000 t ime t ime september 02, 2007 618 preliminary register quick reference 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 1 1 12 13 14 15 qeicount , type ro, offset 0x018, reset 0x0000.0000 count count qeispeed, type ro, offset 0x01c, reset 0x0000.0000 speed speed qeiinten, type r/w , offset 0x020, reset 0x0000.0000 intindex intt imer intdir interror qeiris, type ro, offset 0x024, reset 0x0000.0000 intindex intt imer intdir interror qeiisc, type r/w1c, offset 0x028, reset 0x0000.0000 intindex intt imer intdir interror 619 september 02, 2007 preliminary lm3s8962 microcontroller c ordering and contact information c.1 ordering information t able c-1. part ordering information description orderable part number stellaris ? lm3s8962 microcontroller lm3s8962-iqc50 stellaris ? lm3s8962 microcontroller lm3s8962-iqc50(t) c.2 company information luminary micro, inc. designs, markets, and sells arm cortex-m3-based microcontrollers (mcus). austin, t exas-based luminary micro is the lead partner for the cortex-m3 processor , delivering the world's first silicon implementation of the cortex-m3 processor . luminary micro's introduction of the stellaris? family of products provides 32-bit performance for the same price as current 8- and 16-bit microcontroller designs. with entry-level pricing at $1.00 for an arm technology-based mcu, luminary micro's stellaris product line allows for standardization that eliminates future architectural upgrades or software tool changes. luminary micro, inc. 108 wild basin, suite 350 austin, tx 78746 main: +1-512-279-8800 fax: +1-512-279-8879 http://www .luminarymicro.com sales@luminarymicro.com c.3 support information for support on luminary micro products, contact: support@luminarymicro.com +1-512-279-8800, ext. 3 september 02, 2007 620 preliminary ordering and contact information l m 3 s n n n n C g p p s s C r r m part number t emperature package speed revision shipping medium i = -40 c to 85 c t = t ape-and-reel omitted = default shipping (tray or tube) omitted = default to current shipping revision a 0 = first all-layer mask a 1 = metal layers update to a0 a 2 = metal layers update to a1 b 0 = second all-layer mask revision rn = 28-pin soic qn = 48-pin lqfp qc = 100-pin lqfp 20 = 20 mhz 25 = 25 mhz 50 = 50 mhz |
Price & Availability of LM3S8962-IQC50T
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